CN100508111C - 封装装置及其形成方法 - Google Patents
封装装置及其形成方法 Download PDFInfo
- Publication number
- CN100508111C CN100508111C CNB2005800362209A CN200580036220A CN100508111C CN 100508111 C CN100508111 C CN 100508111C CN B2005800362209 A CNB2005800362209 A CN B2005800362209A CN 200580036220 A CN200580036220 A CN 200580036220A CN 100508111 C CN100508111 C CN 100508111C
- Authority
- CN
- China
- Prior art keywords
- tube core
- integrated circuit
- ball
- lead
- conducting sphere
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 150000001875 compounds Chemical class 0.000 claims abstract description 25
- 238000003825 pressing Methods 0.000 claims description 27
- 238000005538 encapsulation Methods 0.000 claims description 21
- 238000005516 engineering process Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 6
- 238000011068 loading method Methods 0.000 abstract description 3
- LNUFLCYMSVYYNW-ZPJMAFJPSA-N [(2r,3r,4s,5r,6r)-2-[(2r,3r,4s,5r,6r)-6-[(2r,3r,4s,5r,6r)-6-[(2r,3r,4s,5r,6r)-6-[[(3s,5s,8r,9s,10s,13r,14s,17r)-10,13-dimethyl-17-[(2r)-6-methylheptan-2-yl]-2,3,4,5,6,7,8,9,11,12,14,15,16,17-tetradecahydro-1h-cyclopenta[a]phenanthren-3-yl]oxy]-4,5-disulfo Chemical compound O([C@@H]1[C@@H](COS(O)(=O)=O)O[C@@H]([C@@H]([C@H]1OS(O)(=O)=O)OS(O)(=O)=O)O[C@@H]1[C@@H](COS(O)(=O)=O)O[C@@H]([C@@H]([C@H]1OS(O)(=O)=O)OS(O)(=O)=O)O[C@@H]1[C@@H](COS(O)(=O)=O)O[C@H]([C@@H]([C@H]1OS(O)(=O)=O)OS(O)(=O)=O)O[C@@H]1C[C@@H]2CC[C@H]3[C@@H]4CC[C@@H]([C@]4(CC[C@@H]3[C@@]2(C)CC1)C)[C@H](C)CCCC(C)C)[C@H]1O[C@H](COS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@H](OS(O)(=O)=O)[C@H]1OS(O)(=O)=O LNUFLCYMSVYYNW-ZPJMAFJPSA-N 0.000 description 12
- 239000000463 material Substances 0.000 description 9
- 239000010931 gold Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 230000003321 amplification Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 4
- 239000011295 pitch Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000001746 injection moulding Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- XRWSZZJLZRKHHD-WVWIJVSJSA-N asunaprevir Chemical compound O=C([C@@H]1C[C@H](CN1C(=O)[C@@H](NC(=O)OC(C)(C)C)C(C)(C)C)OC1=NC=C(C2=CC=C(Cl)C=C21)OC)N[C@]1(C(=O)NS(=O)(=O)C2CC2)C[C@H]1C=C XRWSZZJLZRKHHD-WVWIJVSJSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229940125961 compound 24 Drugs 0.000 description 2
- 229940127573 compound 38 Drugs 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- PIDFDZJZLOTZTM-KHVQSSSXSA-N ombitasvir Chemical compound COC(=O)N[C@@H](C(C)C)C(=O)N1CCC[C@H]1C(=O)NC1=CC=C([C@H]2N([C@@H](CC2)C=2C=CC(NC(=O)[C@H]3N(CCC3)C(=O)[C@@H](NC(=O)OC)C(C)C)=CC=2)C=2C=CC(=CC=2)C(C)(C)C)C=C1 PIDFDZJZLOTZTM-KHVQSSSXSA-N 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000011575 calcium Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- UCHOFYCGAZVYGZ-UHFFFAOYSA-N gold lead Chemical compound [Au].[Pb] UCHOFYCGAZVYGZ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/45164—Palladium (Pd) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/45169—Platinum (Pt) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/4569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01076—Osmium [Os]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一种封装集成电路管芯(12)的方法包括将软导电球(12)的阵列装载到形成于压板(50)中的凹部中并将压板(50)定位在模具腔的第一部分中的步骤。抵靠球(12)对模具的第二部分加压以使球的表面平坦化。然后将第一成型化合物(18)注入模具腔,使得成型化合物(18)围绕球(12)的露出部分。从压板移除球并将集成电路管芯(20)的第一侧附装到球(12)。将管芯第二侧上的管芯接合盘(28)电连接到围绕管芯(20)的相应多个球(12),随后用第二成型化合物(24)封装管芯(20)、电连接(30)、和导电球(12)的顶部。
Description
技术领域
本发明涉及集成电路封装,更具体而言,涉及用于制造球栅阵列(BGA)封装装置的改进工艺。
背景技术
集成电路(IC)管芯是形成在半导体晶片例如硅晶片上的小装置。引线框作为金属框架通常包括支承已从晶片切下的IC管芯的叶片(paddle)。引线框还具有提供外部电连接的引线指(lead finger)。就是说,管芯附装到管芯叶片,然后将管芯的接合盘经由导线接合或倒装芯片突起接合(flip chip bumping)而连接到引线指,以提供外部电连接。利用保护材料封住管芯以及导线接合或倒装芯片突起就形成了封装。取决于封装类型,外部电连接可以就这样使用,例如在薄型小尺寸封装(TSOP)中,或者例如对于BGA通过附装球形焊球来进一步处理。这些端子点使得管芯能够与例如在印刷电路板上的其它电路电连接。但是,如果需要像化学刻蚀和回蚀的步骤,则形成引线框和封装就可能是昂贵且耗时的。
因此,期望省去这些刻蚀步骤并进一步不再需要引线框。还期望有一种减小封装IC的尺寸的方法。
发明内容
本发明提供了一种封装集成电路管芯的方法,其包括以下步骤:
将多个导电球装载到形成于压板中的多个凹部中;
将所述压板转移到模具的第一部分的腔;
抵靠所述导电球对所述模具的第二部分加压,由此至少部分使所述导电球的顶表面平坦化;
将第一成型化合物注入所述模具中,其中所述第一成型化合物围绕所述导电球的露出部分;
从压板移除导电球,其中导电球由第一成型化合物保持在一起;
将集成电路管芯的第一侧附装到多个所述导电球,其中所述管芯被所述导电球中的其余多个围绕;
将所述管芯的第二侧上的多个管芯接合盘电连接到围绕所述管芯的相应多个导电球;以及
用第二成型化合物封装所述管芯的至少第二侧、电连接、以及至少部分所述导电球。
在另一实施例中,散热器可以定位成于导电球和附装到散热器表面的管芯共面。
附图说明
在结合附图阅读时将更好地理解下面对本发明优选实施例的详细说明。本发明通过示例示出而不受附图限制,附图中类似的标号指示类似的元件。
图1是根据本发明第一实施例的封装集成电路的放大剖视图;
图2是根据本发明第二实施例的封装集成电路的放大剖视图;
图3是根据本发明第三实施例的封装集成电路的放大剖视图;
图4A-4H是示出根据本发明制造封装半导体器件的步骤的透视图;
图5A和5B是示出根据本发明所形成的多个封装半导体器件剖视图。
具体实施方式
下面结合附图进行的详细说明是对本发明目前的优选实施例的说明,而非表示可以实现本发明的唯一形式。应该理解到相同或等同的功能可以由包括在本发明的精神和范围内的不同实施例实现。另外,本领域技术人员将理解到附图已被简化而并不按比例绘制。
本发明还提供了一种封装集成电路管芯,其包括具有平坦顶表面的多个导电球、和将所述多个导电球保持在一起的第一成型化合物。这些球的平坦顶表面与所述第一成型化合物的顶表面大体共面,并且这些球的相反的底表面被露出。具有第一侧的集成电路管芯被附装到多个所述导电球。所述管芯被所述导电球中的其余多个围绕。所述管芯电连接到所述导电球中的其余多个。第二成型化合物至少封装所述管芯的与管芯第一侧相反的第二侧以及所述导电球的顶表面。
现在参照图1,示出了根据本发明实施例形成的封装半导体器件10的放大剖视图。封装器件10包括多个具有平坦顶表面14和相反底表面16的导电球12。第一成型化合物(mold compound)18将多个导电球12保持在一起。球12的平坦顶表面14大体与第一成型化合物18的顶表面共面,并且球12的相反底表面16露出。集成电路管芯20具有附装到多个导电球12的第一侧22。管芯20被其余的导电球12围绕,并且管芯20电联接到其余的导电球12。第二成型化合物24至少封住管芯20的与管芯第一侧22相反的第二侧26以及导电球12的顶表面14。第二成型化合物24是本领域技术人员已知的用于封装集成电路的类型。
导电球12优选是C5(受控芯片载体塌陷连接)焊球。球12利用导电材料制成以使得电信号可以从其通过。导电材料可以是例如铜或金的金属或者金属合金,或者是软焊料,例如63/37材料(63%的锡,37%的铅)或90/10(90%的铅,10%的锡)。或者,软焊球14可以由具有光洁金属表面的聚合物基材形成。可以通过使用无铅金属球来实现无铅封装。
球12的底表面16被露出,使得集成电路管芯12能够连接到印刷电路板。球12用于向/从管芯20以及衬底或印刷电路板(未示出)传输数据、功率和接地信号,这是本领域技术人员已知的,而管芯20所附装到的其余的球12可以传导来自管芯20的热(即,热控制)并提高板级焊接强度。就是说,管芯20下方的球12提供了提高板级焊接强度的可焊接表面。注意,位于角部和甚至沿着封装边缘的球也可以提供提高封装机械强度的连接。
球12的顶表面16是平坦且共面的。顶表面16可以通过压制而平坦化,这将在下面更详细讨论。球12利用第一成型化合物18保持在一起。第一成型化合物18是本领域技术人员已知常用于封装集成电路的类型。
集成电路管芯20可以是任何已知类型的管芯,例如从硅晶片切下的一个管芯,并且可以是任何类型的电路,例如数字信号处理器、专用电路等等。这样的电路是本领域技术人员熟知的。管芯20的底表面22利用附装材料(未示出)附装到导电球12中一个或多个的平坦顶表面14。管芯附装材料可以是半导体技术中熟知类型的用于将管芯附装到衬底的粘合剂,例如环氧树脂。
集成电路管芯20的顶表面26包括多个管芯接合盘28。管芯接合盘28电连接到围绕管芯20的多个导电球12。在一个实施例中,管芯接合盘28通过导线接合利用导线30连接到导电球12。已知的导线接合工艺例如热超声导线接合可以用于将导线30连接到管芯接合盘28和球12的顶表面14。
本领域技术人员已知,各种尺寸的导线可用于将管芯连接到衬底,根据盘间距作为决定因素之一来选择导线尺寸。接合导线30的直径在约15μm到约55μm之间,尽管可以使用其它直径的接合导线并且本发明不应限于一个具体的接合导线直径。例如,63μm间距的应用使用25μm直径的导线,而52μm和44μm间距的应用使用20.3μm直径的导线。正在使用17μm直径的导线进行对于37μm间距的应用的开发。因此,正如本领域中已知的,可以根据盘间距进行精细间距和超精细间距导线接合工艺。在本发明的一个实施例中,使用绝缘接合导线。绝缘接合导线包括涂有电绝缘材料的导电芯,并适合于精细间距和超精细间距导线接合。绝缘材料防止导线与其它导线或其它导电结构短接。一般而言,金和铝是最常用于制造接合导线的导电芯的元素。金和铝都是强度高且易延展的,并在大多数环境中具有类似的电阻。金导线有时掺杂有例如铍、钙的掺杂剂以使其稳定。小直径铝导线常掺杂有硅或有时掺杂有镁,以提高其断裂载荷和拉伸参数。除了金和铝之外,还已知铜、钯合金、铂和银接合导线。在本发明的一个实施例中,使用直径小于约25μm的绝缘导线。绝缘涂层优选是可以在无空气球形成期间热分解的厚度约0.5μm到约2.0μm的有机绝缘涂层。另外,导线30优选具有约180°到350°的熔融温度(Tg)。
球12由软材料制成以使得导线30可以容易地导线接合到其上。优选地,导线30由更硬或更刚性的材料例如铜或硬的金合金制成,使得在导线接合过程中导线30穿透嵌入球12内。使用更硬的材料用于导线30使得导线30能够穿透进入球12,由此通过将硬导线30嵌入较软的球12而形成连接。
现在参照图2,示出封装器件32的另一实施例。在此实施例中,不将管芯20附装到球12,而将管芯20附装到散热器34。散热器34优选与多个球12共面且由其围绕。更具体而言,管芯所附装到的散热器34的第一表面与球12的顶表面共面,并且散热器34的相反的第二表面与球12的底表面16共面。于是,散热器34的第二侧被露出。散热器34的厚度优选等于球12的从平坦的顶表面14到底表面16测得的直径。管芯20可以利用管芯附装粘合剂或焊剂(未示出)附装到散热器34。为了提供好的热特性,散热器34优选由固体金属板例如铜片形成。散热器34进一步改善了热性能并增大了封装32的可焊接面积。
现在参照图3,示出封装器件36的另一替代方案。封装器件36类似于封装器件32(图2),除了第二成型化合物38已作为顶部封装体(glob top)形成在管芯20、导线30和球12的顶表面14上。为了进行顶部封装体封装工艺,在封装的两侧形成障碍物或凸缘40以保持第二成型化合物38。障碍物40可以由第一成型化合物18形成。将认识到可以在有或没有散热器34的封装上进行顶部封装体封装工艺。就是说,尽管封装器件36包括散热器34,但散热器34并不是必要的。
现在参照图4A-4H,将描述根据本发明实施例的用于封装IC管芯的方法。图4A和4B是示出装载多个导电球12的压板或固定装置50的放大剖视图。压板50是具有一个大的平坦表面的金属块,该表面具有多个装载球12的腔或凹部52。腔52在压板50的表面上布置成栅格或阵列。图4A示出球12正在装载到压板50中,而图4B示出布置在腔52内的球12。如图所示,腔52大体是圆形的。但是,腔52可以具有平坦或部分平坦的底表面,使得球12的底部可以被平坦化或部分平坦化(例如通过压制)。球12可以使用已知技术例如摇动器装载到凹部52中。凹部52以与封装器件的所需球间距匹配的间距间隔开,例如1.27mm。一旦球被装载到凹部52中,则整个压板50被转移到模具腔中。使用压板50的一种替代方案是将球12装载到位于模具腔底部的孔阵列中。球12可以以多种方式例如用掩模布置这些孔中。图4C示出球12被布置在具有凹部52和用于散热器34的空间56的压板54中。在此实施例中,在将球12装载到凹部52中之前将散热器34布置在空间56中。
如前所述,球14由可以变形的软导电材料形成,例如软金属。示例金属是焊剂或金。如本领域技术人员所知,大多数BGA球用非常软的63/37材料(63%的锡,37%的铅)制成。即使在使用90/10(90%的铅,10%的锡)材料时,球的形状也可以变形。现在参照图4D和4E,在球12被装载到压板50中之后,用球12的顶表面14用模具的第一顶部58或通过机械模压工艺由压制机平坦化。就是说,模具顶部58被压靠压板50的腔52内的球12的顶表面14,而使球12的顶表面14平坦化。如果腔52也具有平坦或部分平坦的底表面,则球12的底表面16以与顶表面14相同的方式平坦化。于是,球12的顶表面14和底表面16中之一或两者被平坦化或部分平坦化。
现在参照图4F,在机械模压工艺之后,进行第一注入成型工艺,使得第一成型化合物18围绕球12。就是说,第一成型化合物18被注入模具中,并且第一成型化合物18围绕球12的露出部分。注入成型使本领域熟知的,并且其进一步描述对于完整理解本发明并不是必要的。
参照图4G,在第一成型化合物18固化后,移除模具的第一顶部58。此时,球12可以从压板50移除,或者球12可以保留在压板50中用于进一步处理,如下所述。用于说明目的,在图4G中球12示出与压板50拆开或分离。但是,在当前优选实施例中,球12还未从压板50移除。
参照图4H,集成电路管芯20在预定位置处附装到多个球12。管芯20具有底表面22和包括多个导线接合盘28的顶表面26。在当前优选实施例中,管芯20的底表面22利用管芯附装粘合剂(未示出)直接附装到球12。在使得管芯20被多个球12围绕的位置处附装管芯20。使用I/O的数量确定围绕管芯20的球12的数量。将管芯20附装在多个球12的顶表面14上使得球12所装载到的压板能够大小均匀并具有单一球矩阵图案。单一球矩阵图案使得可以形成不同尺寸的管芯和不同的封装尺寸而不必改变压板的尺寸。另外,如上所述,管芯20所附装到的球12用作管芯20的热路径,并提供提高板级焊接强度的可焊接表面。
如前所述,还有管芯附装的其它选择。例如,代替管芯附装粘合剂,管芯可以焊接到球12。另外,如图2和3所示,管芯20可以利用环氧树脂或焊接附装到散热器34(例如固体金属板)。散热器34可以进一步改善封装的热性能并增大封装的可焊接面积。
再参照图4H,在如上所述已经将管芯20附装到球12之后,管芯20上的导线接合盘28电连接到球12中围绕管芯20的相应多个球。更具体而言,接合导线30从管芯导线接合盘28连接到相应的多个球12。使用本领域已知的导线接合工艺,将导线30的一端连接到管芯接合盘28,并将另一端连接到球12。但是,由于球12利用第一成型化合物18保持在一起,所以为了不影响第一成型化合物18的结构,可以使用在传统热超声导线接合工艺中使用的超声力的替代方案。例如,代替应用传统的热超声接合,使用由铜或硬的金合金制成的硬导线来穿透进入球12,这通过将导线30嵌入球12中而形成连接。如图4H所示,导线30的尖端被嵌入球12内。尖端的形状为大体圆形,并由导线接合机通过导线30的电烧融(electric flame off,EFO)来形成。
再参照图1,在进行导线接合工艺之后,用第二成型化合物24封装电连接、导线30和球12的一部分。同样,使用已知的注入成型工艺。第二成型化合物优选是塑料材料,这是封装集成电路领域已知的。
在封装工艺之后,将现在封装好的管芯20从模具和压板50移除,由此露出球12的阵列的底表面,如图1所示。为确保可靠的互连性能,球12的露出底表面16可以涂有或镀有抗腐蚀且提供低接触阻力的光洁贵金属表面(例如NI/Au)。球12的露出部分可以通过选择性沉积电解Ni/Au的电镀物来施加涂层。
现在参照图5A,不是形成单个封装,而是同时形成多个封装。图5A示出三个这样的封装60。优选使用熟知的划割单片化(sawsingulation)工艺,通过沿着划割间隔(saw street)62切割来分离封装60,以形成如图5B所示的单个封装器件10。划割间隔62是在第一成型注入工艺期间有第一成型化合物18形成的凸缘。划割间隔(凸缘)62在管芯附装、导线接合和第二成型注入工艺过程中保护嵌入第一成型化合物18中的球12。
在划割单片化工艺之前,可以进行可选的电子功能测试。因为封装器件的所有I/O端子在整个封装工艺中都是分离的,所以可以进行条格式(strip format)电子测试,因此在没有附加工艺或成本的情况下提高了测试器利用率并能够进行并行测试。
封装器件具有改善的高频电子性能,因为从管芯20到板的信号路径被缩短。另外,通过提高对由系统板的弯曲引起的应力故障的焊接抵抗,而改善了系统可靠性。对于手机制造者,改善的RF性能和对机械应力故障的抵抗是重要的问题。
本发明提高了封装集成电路的容易且便宜的方法。使用两层成型化合物,其中C5球嵌入第一层成型化合物中。C5球的顶表面用作接合指,而底表面在PCB上提供隔离。封装器件可以包括用于更好热性能的热片。另外,器件可以使用顶部封装体封装形成。器件成本很低,因为既不需要衬底也不需要端接(外部引脚)。因为没有金属引线框,所以在单片化步骤中使用的划割刀不必切割通过金属,从而划割刀将具有更长的寿命。而且,因为不需要引线框,所以不必进行衬底迹线布线。该封装工艺不需要任何可能昂贵的化学回蚀。该封装工艺可以使用当前可用的设备进行。该封装也具有非常小的尺寸,小到约0.4mm。尽管描述了LGA封装,但也可以使用上述方法形成其它封装类型,例如QFN(方形扁平无引线)。堆叠管芯器件也可以利用此方法封装。矩栅阵列(LGA)提供了高互连密度,例如200+I/O是可能的。
虽然对本发明优选实施例进行了解释和说明,很清楚本发明并不仅限于这些实施例。不偏离由权利要求描述的本发明的精神和范围的多个修改、改变、变化、替代和等同方案对本领域技术人员是明显的。
Claims (19)
1.一种封装集成电路管芯的方法,包括以下步骤:
将多个导电球装载到形成于压板中的多个凹部中;
将所述压板转移到模具的第一部分的腔;
抵靠所述导电球对所述模具的第二部分加压,由此封闭所述模具并至少部分使所述导电球的顶表面平坦化;
将第一成型化合物注入所述模具中,其中所述第一成型化合物围绕所述导电球的露出部分并将所述导电球保持在一起;
移除所述模具的所述第二部分以露出所述导电球的所述顶表面;
将集成电路管芯的第一侧附装到多个所述导电球,其中所述管芯被所述导电球中的其余多个围绕;
将所述管芯的第二侧上的多个管芯接合盘电连接到围绕所述管芯的相应多个导电球;以及
用第二成型化合物封装所述管芯的至少第二侧、电连接、以及所述导电球的至少部分顶表面。
2.根据权利要求1所述的封装集成电路管芯的方法,其中使用掩模来将所述导电球转移并定位到所述模具的底腔中。
3.根据权利要求1所述的封装集成电路管芯的方法,其中所述导电球包括焊球。
4.根据权利要求1所述的封装集成电路管芯的方法,其中所述压板具有用于接纳所述导电球的凹部阵列。
5.根据权利要求4所述的封装集成电路管芯的方法,其中所述凹部以预定间距间隔开。
6.根据权利要求5所述的封装集成电路管芯的方法,其中所述压板包括用于接纳散热器的空间,所述方法还包括将散热器布置在散热器接纳区域内的步骤。
7.根据权利要求6所述的封装集成电路管芯的方法,其中所述散热器具有与所述导电球的平坦顶表面大体共面的第一侧,并且其中管芯附装步骤包括将所述管芯的第一侧附装到所述散热器的第一侧。
8.根据权利要求1所述的封装集成电路管芯的方法,其中在管芯附装步骤中,所述管芯附装到多个所述导电球的平坦顶表面。
9.根据权利要求1所述的封装集成电路管芯的方法,其中电连接步骤包括利用相应多根导线将所述管芯接合盘导线接合到相应多个球。
10.根据权利要求9所述的封装集成电路管芯的方法,其中在导线接合步骤中,所述导线穿透进入所述球并嵌入在其中。
11.根据权利要求10所述的封装集成电路管芯的方法,其中所述导线是绝缘导线。
12.根据权利要求10所述的封装集成电路管芯的方法,其中所述球由比所述导线更软的金属形成,使得所述导线嵌入所述球中。
13.根据权利要求9所述的封装集成电路管芯的方法,其中所述导线附装到所述球的平坦顶表面。
14.根据权利要求1所述的封装集成电路管芯的方法,还包括将封装管芯与相邻的封装管芯划割单片化的步骤。
15.根据权利要求1所述的封装集成电路管芯的方法,其中所述导电球嵌入所述第一成型化合物中,所述球的平坦表面与所述第一成型化合物的顶表面基本共面。
16.根据权利要求15所述的封装集成电路管芯的方法,其中所述导电球的与球的平坦表面相反的表面突出超出所述第一成型化合物的底表面。
17.根据权利要求1所述的封装集成电路管芯的方法,其中封装步骤包括进行顶部封装体封装工艺。
18.根据权利要求1组装的封装集成电路管芯。
19.一种封装多个集成电路管芯的方法,包括以下步骤:
将多个导电球装载到形成于压板中的多个凹部中;
将所述压板转移到模具的第一部分的腔;
抵靠所述导电球对所述模具的第二部分加压,由此至少部分使所述导电球的顶表面平坦化;
将第一成型化合物注入所述模具中,其中所述第一成型化合物围绕所述导电球的露出部分;
将多个集成电路管芯的第一侧在预定位置处附装到多个所述导电球上,其中所述管芯被所述导电球中的其余多个围绕;
将所述管芯的第二侧上的多个管芯接合盘电连接到围绕所述管芯的相应多个导电球;
用第二成型化合物封装所述管芯的至少第二侧、电连接、以及至少部分所述导电球;以及
单片化相邻的封装管芯以形成单个的封装器件。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
MYPI20044381A MY136179A (en) | 2004-10-23 | 2004-10-23 | Packaged device and method of forming same |
MYPI20044381 | 2004-10-23 | ||
US11/191,132 | 2005-07-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101044592A CN101044592A (zh) | 2007-09-26 |
CN100508111C true CN100508111C (zh) | 2009-07-01 |
Family
ID=36205477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005800362209A Expired - Fee Related CN100508111C (zh) | 2004-10-23 | 2005-09-27 | 封装装置及其形成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7179682B2 (zh) |
CN (1) | CN100508111C (zh) |
MY (1) | MY136179A (zh) |
TW (1) | TWI280643B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102738019A (zh) * | 2012-06-13 | 2012-10-17 | 华天科技(西安)有限公司 | 一种基于框架载体开孔和模具贴膜的aaqfn产品的二次塑封制作工艺 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7372133B2 (en) * | 2005-12-01 | 2008-05-13 | Intel Corporation | Microelectronic package having a stiffening element and method of making same |
TW200908246A (en) * | 2007-08-07 | 2009-02-16 | Chipmos Technologies Inc | Adhesion structure for a package apparatus |
TWI470460B (zh) * | 2009-12-30 | 2015-01-21 | Synopsys Inc | 覆晶封裝之繞線方法及其電腦化裝置 |
CN102738022B (zh) | 2011-04-15 | 2017-05-17 | 飞思卡尔半导体公司 | 组装包括绝缘衬底和热沉的半导体器件的方法 |
CN102738018A (zh) * | 2012-06-13 | 2012-10-17 | 华天科技(西安)有限公司 | 一种基于框架载体开孔和锡球贴膜的aaqfn产品的二次塑封制作工艺 |
US10204814B1 (en) * | 2017-07-28 | 2019-02-12 | Stmicroelectronics, Inc. | Semiconductor package with individually molded leadframe and die coupled at solder balls |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6025650A (en) * | 1994-08-24 | 2000-02-15 | Fujitsu Limited | Semiconductor device including a frame terminal |
CN1282982A (zh) * | 1997-07-30 | 2001-02-07 | 株式会社日立制作所 | 半导体器件的制造方法 |
US6551862B2 (en) * | 2000-11-02 | 2003-04-22 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5695109A (en) * | 1995-11-22 | 1997-12-09 | Industrial Technology Research Institute | Solder paste inter-layer alignment apparatus for area-array on-board rework |
JP3116273B2 (ja) * | 1996-04-26 | 2000-12-11 | 日本特殊陶業株式会社 | 中継基板、その製造方法、基板と中継基板と取付基板とからなる構造体、基板と中継基板の接続体 |
JP2000022044A (ja) * | 1998-07-02 | 2000-01-21 | Mitsubishi Electric Corp | 半導体装置とその製造方法 |
US6992380B2 (en) * | 2003-08-29 | 2006-01-31 | Texas Instruments Incorporated | Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area |
US7056766B2 (en) * | 2003-12-09 | 2006-06-06 | Freescale Semiconductor, Inc. | Method of forming land grid array packaged device |
US7160755B2 (en) * | 2005-04-18 | 2007-01-09 | Freescale Semiconductor, Inc. | Method of forming a substrateless semiconductor package |
-
2004
- 2004-10-23 MY MYPI20044381A patent/MY136179A/en unknown
-
2005
- 2005-07-27 US US11/191,132 patent/US7179682B2/en not_active Expired - Fee Related
- 2005-08-16 TW TW094127964A patent/TWI280643B/zh not_active IP Right Cessation
- 2005-09-27 CN CNB2005800362209A patent/CN100508111C/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6025650A (en) * | 1994-08-24 | 2000-02-15 | Fujitsu Limited | Semiconductor device including a frame terminal |
CN1282982A (zh) * | 1997-07-30 | 2001-02-07 | 株式会社日立制作所 | 半导体器件的制造方法 |
US6551862B2 (en) * | 2000-11-02 | 2003-04-22 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102738019A (zh) * | 2012-06-13 | 2012-10-17 | 华天科技(西安)有限公司 | 一种基于框架载体开孔和模具贴膜的aaqfn产品的二次塑封制作工艺 |
Also Published As
Publication number | Publication date |
---|---|
CN101044592A (zh) | 2007-09-26 |
TWI280643B (en) | 2007-05-01 |
TW200620589A (en) | 2006-06-16 |
US7179682B2 (en) | 2007-02-20 |
MY136179A (en) | 2008-08-29 |
US20060087038A1 (en) | 2006-04-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7285855B2 (en) | Packaged device and method of forming same | |
US7564137B2 (en) | Stackable integrated circuit structures and systems devices and methods related thereto | |
US7205178B2 (en) | Land grid array packaged device and method of forming same | |
US6884652B2 (en) | Semiconductor package free of substrate and fabrication method thereof | |
KR101119708B1 (ko) | 집적 회로 다이를 패키징하는 방법 | |
US7704800B2 (en) | Semiconductor assembly with one metal layer after base metal removal | |
US5747874A (en) | Semiconductor device, base member for semiconductor device and semiconductor device unit | |
US7423340B2 (en) | Semiconductor package free of substrate and fabrication method thereof | |
CN100508111C (zh) | 封装装置及其形成方法 | |
US7939383B2 (en) | Method for fabricating semiconductor package free of substrate | |
US7750465B2 (en) | Packaged integrated circuit | |
US20090039509A1 (en) | Semiconductor device and method of manufacturing the same | |
US7271493B2 (en) | Semiconductor package free of substrate and fabrication method thereof | |
US6075281A (en) | Modified lead finger for wire bonding | |
US20050194665A1 (en) | Semiconductor package free of substrate and fabrication method thereof | |
CN104183577A (zh) | 具有压接互连的柔性基板 | |
US20050184368A1 (en) | Semiconductor package free of substrate and fabrication method thereof | |
US6534337B1 (en) | Lead frame type plastic ball grid array package with pre-assembled ball type contacts | |
JP3386967B2 (ja) | 基板の検査法 | |
KR100489476B1 (ko) | 엠씨엠 볼 그리드 어레이 패키지 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090701 Termination date: 20160927 |
|
CF01 | Termination of patent right due to non-payment of annual fee |