CN100490113C - 金属互连结构及其制作方法 - Google Patents

金属互连结构及其制作方法 Download PDF

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Publication number
CN100490113C
CN100490113C CNB028120493A CN02812049A CN100490113C CN 100490113 C CN100490113 C CN 100490113C CN B028120493 A CNB028120493 A CN B028120493A CN 02812049 A CN02812049 A CN 02812049A CN 100490113 C CN100490113 C CN 100490113C
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CN
China
Prior art keywords
copper
layer
alloying element
solid solution
conductive plug
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB028120493A
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English (en)
Chinese (zh)
Other versions
CN1516896A (zh
Inventor
P·R·贝塞尔
L·赵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN1516896A publication Critical patent/CN1516896A/zh
Application granted granted Critical
Publication of CN100490113C publication Critical patent/CN100490113C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
    • H10W20/0526—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by thermal treatment thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
CNB028120493A 2001-06-20 2002-04-02 金属互连结构及其制作方法 Expired - Lifetime CN100490113C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/884,027 US6656834B1 (en) 2001-06-20 2001-06-20 Method of selectively alloying interconnect regions by deposition process
US09/884,027 2001-06-20

Publications (2)

Publication Number Publication Date
CN1516896A CN1516896A (zh) 2004-07-28
CN100490113C true CN100490113C (zh) 2009-05-20

Family

ID=25383816

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028120493A Expired - Lifetime CN100490113C (zh) 2001-06-20 2002-04-02 金属互连结构及其制作方法

Country Status (7)

Country Link
US (1) US6656834B1 (https=)
EP (1) EP1407488A2 (https=)
JP (1) JP4886165B2 (https=)
KR (1) KR20040012912A (https=)
CN (1) CN100490113C (https=)
TW (1) TW575909B (https=)
WO (1) WO2003001589A2 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4647184B2 (ja) * 2002-12-27 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR100573897B1 (ko) * 2003-12-30 2006-04-26 동부일렉트로닉스 주식회사 반도체 제조 방법
JP4764606B2 (ja) * 2004-03-04 2011-09-07 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7327033B2 (en) * 2004-08-05 2008-02-05 International Business Machines Corporation Copper alloy via bottom liner
US8164190B2 (en) * 2009-06-25 2012-04-24 International Business Machines Corporation Structure of power grid for semiconductor devices and method of making the same
KR101131352B1 (ko) 2009-08-31 2012-04-04 삼성전기주식회사 인쇄회로기판의 제조방법
CN102005384B (zh) * 2010-09-16 2012-02-01 哈尔滨工程大学 铜金属化自形成阻挡层低温退火方法
US10461026B2 (en) 2016-06-30 2019-10-29 International Business Machines Corporation Techniques to improve reliability in Cu interconnects using Cu intermetallics

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6160315A (en) * 1997-05-08 2000-12-12 Applied Materials, Inc. Copper alloy via structure
US6242349B1 (en) * 1998-12-09 2001-06-05 Advanced Micro Devices, Inc. Method of forming copper/copper alloy interconnection with reduced electromigration
US6249055B1 (en) * 1998-02-03 2001-06-19 Advanced Micro Devices, Inc. Self-encapsulated copper metallization

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2850380B2 (ja) * 1989-07-11 1999-01-27 セイコーエプソン株式会社 半導体装置の製造方法
KR0165813B1 (ko) * 1995-04-12 1999-02-01 문정환 접속홀의 플러그 형성 방법
KR19980032463A (ko) * 1996-10-03 1998-07-25 윌리엄비.켐플러 개선된 전자이주 능력을 위한 비아(ｖｉａ) 패드와 캡
US5913147A (en) * 1997-01-21 1999-06-15 Advanced Micro Devices, Inc. Method for fabricating copper-aluminum metallization
JP3479199B2 (ja) * 1997-03-19 2003-12-15 沖電気工業株式会社 半導体素子の多層配線の製造方法
US5930669A (en) * 1997-04-03 1999-07-27 International Business Machines Corporation Continuous highly conductive metal wiring structures and method for fabricating the same
JPH10294317A (ja) 1997-04-18 1998-11-04 Matsushita Electric Ind Co Ltd 積層配線構造体およびその製造方法
US6387805B2 (en) * 1997-05-08 2002-05-14 Applied Materials, Inc. Copper alloy seed layer for copper metallization
US6130161A (en) 1997-05-30 2000-10-10 International Business Machines Corporation Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity
US6069068A (en) * 1997-05-30 2000-05-30 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
US5981382A (en) * 1998-03-13 1999-11-09 Texas Instruments Incorporated PVD deposition process for CVD aluminum liner processing
US6268289B1 (en) * 1998-05-18 2001-07-31 Motorola Inc. Method for protecting the edge exclusion of a semiconductor wafer from copper plating through use of an edge exclusion masking layer
US6144096A (en) 1998-10-05 2000-11-07 Advanced Micro Devices, Inc. Low resistivity semiconductor barrier layers and manufacturing method therefor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6160315A (en) * 1997-05-08 2000-12-12 Applied Materials, Inc. Copper alloy via structure
US6249055B1 (en) * 1998-02-03 2001-06-19 Advanced Micro Devices, Inc. Self-encapsulated copper metallization
US6242349B1 (en) * 1998-12-09 2001-06-05 Advanced Micro Devices, Inc. Method of forming copper/copper alloy interconnection with reduced electromigration

Also Published As

Publication number Publication date
JP4886165B2 (ja) 2012-02-29
TW575909B (en) 2004-02-11
KR20040012912A (ko) 2004-02-11
CN1516896A (zh) 2004-07-28
US6656834B1 (en) 2003-12-02
US20030216029A1 (en) 2003-11-20
WO2003001589A2 (en) 2003-01-03
JP2004531900A (ja) 2004-10-14
EP1407488A2 (en) 2004-04-14
WO2003001589A3 (en) 2003-03-20

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