CN100490100C - 制造半导体器件的鳍式场效应晶体管的方法 - Google Patents

制造半导体器件的鳍式场效应晶体管的方法 Download PDF

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CN100490100C
CN100490100C CNB2006101724171A CN200610172417A CN100490100C CN 100490100 C CN100490100 C CN 100490100C CN B2006101724171 A CNB2006101724171 A CN B2006101724171A CN 200610172417 A CN200610172417 A CN 200610172417A CN 100490100 C CN100490100 C CN 100490100C
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朴正浩
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    • H01L29/7851Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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    • H01L29/66409Unipolar field-effect transistors
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    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

一种制造半导体器件的鳍式FET的方法。该方法包括以下步骤:在半导体衬底上依次沉积第一绝缘膜和第二绝缘膜;通过使用第一掩模蚀刻该第一绝缘膜和该第二绝缘膜,以形成沟槽;以及在该沟槽中沉积第一导体。该方法能够简化鳍式FET的制造过程,并且通过降低源区和漏区的电阻能够最大化鳍式FET的载流性能。

Description

制造半导体器件的鳍式场效应晶体管的方法
技术领域
本发明涉及一种制造半导体器件的方法,尤其涉及一种制造半导体器件的鳍式FET(场效应晶体管)的方法。
背景技术
信息技术和通信设备的发展以及计算机的普及导致半导体器件的改进。半导体器件的大规模集成促使研究各种方法,以在最大化性能的同时减小在衬底上形成的单个器件的特征尺寸。
CMOS(互补金属氧化物半导体)是一种能使场效应晶体管(FET)更大规模集成的技术。然而,由于更大规模集成,使得FET的尺寸降低,从而引起器件的性能和可靠性降低。为了改善这些问题,已经提出“鳍式”FET设计,其特征在于具有像鱼的背鳍形状的垂直体结构。
三维鳍式FET可具有多种结构变化,例如,DELTA(fully depletedlean-channel transistor,全耗尽倾向沟道晶体管)和GAA(gate all around,全环栅)。DELTA结构具有有源鳍形区,其中将形成沟道。有源鳍形区垂直突出并具有预定的宽度。栅电极围绕垂直突出的沟道部分。因此,突出部分的高度变为沟道的宽度,而突出部分的宽度变为沟道的厚度。由于突出部分的两侧起到沟道的作用,因此该结构具有使沟道宽度加倍的效果。从而,能够在仍然减小晶体管的总体尺寸的同时防止有效沟道宽度减小。此外,由于在两侧形成彼此交叠的沟道耗尽层,因此即使在减小器件的特征尺寸时,沟道的导电性仍然可以提高。
例如,在具有双栅极结构的鳍式FET中,在沟道的上侧和下侧或者左侧和右侧分别具有栅电极显著提高了沟道中的电流控制特性。与单栅极器件相比,这意味着显著减少了源极与漏极之间的漏电流,从而改善了DIBL(drain-induced barrier lowering,漏致势垒降低)特性。此外,由于在沟道的两侧均具有栅极,因此器件的阈值电压可动态变化。因此,与单栅极结构相比,显著改善了沟道的开关特性,从而使短沟道效应得到抑制。
然而,鳍式FET的制造方法复杂,并且由于半导体器件的进一步小型化而使载流性能需折衷处理。
发明内容
本发明的实施例涉及一种制造半导体器件的鳍式FET(场效应晶体管)的方法,该半导体器件具有从硅衬底突出的鳍形有源区。
本发明的实施例涉及一种制造鳍式FET的方法,该方法能够简化制造过程,并且通过降低源区和漏区的电阻而能够最大化FET的载流性能。这可通过增加将形成自对准硅化物的源区和漏区的面积来实现。
本发明的实施例涉及一种制造鳍式FET(场效应晶体管)的方法,该方法包括以下步骤:在半导体衬底上依次沉积第一绝缘膜和第二绝缘膜;通过使用第一掩模蚀刻该第一绝缘膜和该第二绝缘膜,以形成其上将形成鳍形导体的沟槽;在形成有该沟槽的第一绝缘膜和第二绝缘膜上沉积第一导体,从而形成鳍形导体;在该第一绝缘膜和该鳍形导体上沉积栅极绝缘膜和栅极导电层;通过使用第二掩模干蚀刻该栅极导电层以形成栅极导体;沉积间隔膜,通过全蚀刻方法在该栅极导体的侧壁上形成间隔部件,然后通过源极和漏极离子注入工艺形成源极和漏极;以及在形成的栅极导体和鳍形导体的暴露部分上执行自对准硅化物工艺,以形成自对准硅化物膜。
附图说明
图1至图10以横截面图示出根据本发明实施例的制造鳍式FET的工艺。
具体实施方式
在图中,为了清楚起见,放大了层、膜、板、区等的厚度。在整个说明书中,相同的标号表示相同的元件。应理解,当提到一元件例如层、膜、区或衬底位于另一元件“上”时,该元件可以直接位于该另一元件上或者也可以存在中间元件。相对地,当提到一元件“直接”位于另一元件“上”时,则不存在中间元件。
图1至图10以横截面图示出根据本发明实施例的制造半导体器件的鳍式FET的方法的一系列工艺。参照图1,在半导体衬底10的上部依次沉积第一绝缘膜30和第二绝缘膜50。然后,在第二绝缘膜50上形成第一光致抗蚀剂,并通过显影和曝光工艺图案化第一光致抗蚀,以形成暴露将形成鳍形导体的区域的第一光致抗蚀剂图案100。氧化物膜可用作第一绝缘膜30。第一绝缘膜30的厚度范围可从约1,000
Figure C200610172417D0006130040QIETU
至约5,000,然而本领域的技术人员应知道也可使用其它范围。第一绝缘膜30用作器件隔离氧化物膜。氮化物膜可用作第二绝缘膜50。第二绝缘膜50的厚度范围可从约500
Figure C200610172417D0006130051QIETU
至约3,000
Figure C200610172417D0006130059QIETU
,然而本领域的技术人员应知道也可使用其它范围。第二绝缘膜50可调节鳍式FET的鳍高度。
以下,参照图2,通过使用第一光致抗蚀剂图案100作为掩模,蚀刻第二绝缘膜50和第一绝缘膜30以形成将形成鳍形导体的沟槽70,然后去除第一光致抗蚀剂图案100。对于上述用途,可采用干蚀刻方法。
然后,沉积第一导体并通过CMP(chemical mechanical polishing,化学机械抛光)使其平坦化以形成填充沟槽70的鳍形导体90。在CMP过程中第二绝缘膜50用作蚀刻停止层。第一导体可通过使用CVD(化学气相沉积)或选择性多晶硅沉积方法形成。
如图3所示,通过离子注入工艺在平坦化的表面上执行阱注入和Vt调节注入110。如图4所示,去除第二绝缘膜50,并在获得的结构上依次沉积栅极绝缘膜130和栅极导电层。磷酸溶液可用于去除第二绝缘膜50。作为栅极导电层,可以使用多晶硅、TiN、Ti和TiN、以及WxNy(即钨和氮的化合物)中的任一种。栅极绝缘膜可通过氧化、PVD(物理气相沉积)、CVD或ALD(原子层沉积)方法形成。在栅极导电层的上部形成第二光致抗蚀剂图案(未示出),并使用该第二光致抗蚀剂图案作为掩模执行干蚀刻,从而形成栅极导体150。然后,去除第二光致抗蚀剂图案。
接着,如图5所示,执行轻掺杂离子(LDD)注入工艺170,以形成LDD注入区。接下来,参照图6,在执行LDD注入工艺170之后,沉积间隔膜。之后,通过全蚀刻方法形成间隔部件190,然后,通过源极和漏极离子注入工艺210形成源极和漏极。间隔部件190可包括例如氮化物膜或氧化物膜、或者氮化物和氧化物的混合膜。
然后,如图7所示,进行自对准硅化物工艺,用于在预定的温度下热处理栅极导体150和鳍形导体90的暴露部分,以形成自对准硅化物膜230和栅极自对准硅化物膜250。这种自对准硅化物膜的形成稳定了LDD注入区以及源区和漏区。因此,能够大面积地形成自对准硅化物部分,以降低晶体管的电阻。自对准硅化物膜可由钛基自对准硅化物、钴基自对准硅化物或镍基自对准硅化物中的任一种形成。与传统鳍式FET的自对准硅化物区的面积相比,本发明的鳍式FET的自对准硅化物区的面积显著增加。
图8为示出本发明的鳍式FET的布局的俯视图,在该鳍式FET上执行了源极和漏极离子注入工艺210。图9为沿着图8的线A-A的横截面图,图10为沿着图8的线B-B的横截面图。
如上文所阐述的,本发明的实施例通过使用第一绝缘膜和第二绝缘膜简化了形成鳍形导体的工艺,并通过增加将形成源区和漏区的自对准硅化物的区域面积降低了源区和漏区的电阻,从而最大化晶体管的载流性能。
显然,对本领域的技术人员来说可对本发明的实施例进行各种修改和变换。因此,本发明的实施例涵盖了落入所附权利要求范围内的对其进行的修改和变换。

Claims (17)

1.一种制造鳍式场效应晶体管的方法,包括以下步骤:
在半导体衬底上依次沉积第一绝缘膜和第二绝缘膜;
使用第一掩模蚀刻该第一绝缘膜和该第二绝缘膜,以形成其上将形成鳍形导体的沟槽;
在形成有该沟槽的该第一绝缘膜和该第二绝缘膜上沉积第一导体,从而形成该鳍形导体;
在该第一绝缘膜和该鳍形导体上沉积栅极绝缘膜和栅极导电层;
使用第二掩模干蚀刻该栅极导电层,以形成栅极导体;
沉积间隔膜,通过全蚀刻方法在该栅极导体的侧壁上形成间隔部件,然后通过源极和漏极离子注入工艺形成源极和漏极;以及
在该栅极导体和该鳍形导体的暴露部分上执行自对准硅化物工艺,以形成自对准硅化物膜。
2.如权利要求1所述的方法,其中该第一绝缘膜为氧化物膜。
3.如权利要求1所述的方法,其中该第一绝缘膜的厚度范围从
Figure C200610172417C00021
Figure C200610172417C00022
4.如权利要求1所述的方法,其中该第一绝缘膜用作器件隔离氧化物膜。
5.如权利要求1所述的方法,其中该第二绝缘膜为氮化物膜。
6.如权利要求1所述的方法,其中该第二绝缘膜的厚度范围从
Figure C200610172417C00023
Figure C200610172417C00024
7.如权利要求1所述的方法,其中该第一绝缘膜和该第二绝缘膜被干蚀刻。
8.如权利要求1所述的方法,还包括以下步骤:
在该第一绝缘膜和该第二绝缘膜上沉积该第一导体之后,使用化学机械抛光工艺平坦化沉积的该第一导体,以形成该鳍形导体。
9.如权利要求8所述的方法,其中在该化学机械抛光工艺中,该第二绝缘膜用作蚀刻停止层。
10.如权利要求1所述的方法,其中该第一导体通过使用化学气相沉积和选择性多晶硅沉积方法中的至少一种方法形成。
11.如权利要求1所述的方法,其中使用磷酸溶液去除该第二绝缘膜。
12.如权利要求1所述的方法,其中该栅极导电层包含多晶硅、TiN、Ti和TiN、以及钨和氮所共同组成的化合物中的一种。
13.如权利要求1所述的方法,其中该栅极绝缘膜通过氧化、物理气相沉积、化学气相沉积和原子层沉积方法中的至少一种方法形成。
14.如权利要求1所述的方法,其中该间隔部件包括氮化物膜和氧化物膜中的至少一种。
15.如权利要求1所述的方法,其中该间隔部件包括氮化物和氧化物的混合膜。
16.如权利要求1所述的方法,还包括以下步骤:
在沉积该栅极绝缘膜和该栅极导电层之前,通过离子注入工艺在平坦化的表面上执行阱注入和Vt调节注入。
17.如权利要求1所述的方法,还包括以下步骤:
在沉积该间隔膜之前,在形成有该栅极导体的衬底上执行轻掺杂离子注入工艺,以形成轻掺杂离子注入区。
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WO2013006989A1 (zh) * 2011-07-08 2013-01-17 中国科学院微电子研究所 一种全硅化金属栅体硅多栅鳍型场效应晶体管的制备方法

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