CN100481036C - 具备总线存取收回的数据处理系统 - Google Patents

具备总线存取收回的数据处理系统 Download PDF

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Publication number
CN100481036C
CN100481036C CNB2005800326734A CN200580032673A CN100481036C CN 100481036 C CN100481036 C CN 100481036C CN B2005800326734 A CNB2005800326734 A CN B2005800326734A CN 200580032673 A CN200580032673 A CN 200580032673A CN 100481036 C CN100481036 C CN 100481036C
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China
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master
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Expired - Lifetime
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CNB2005800326734A
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English (en)
Chinese (zh)
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CN101027655A (zh
Inventor
威廉·C·莫耶
吉米·谷穆佳
布雷特·W·默多克
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Zenith Investment LLC
Apple Inc
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Freescale Semiconductor Inc
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Publication of CN101027655A publication Critical patent/CN101027655A/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Executing Machine-Instructions (AREA)
CNB2005800326734A 2004-09-30 2005-09-01 具备总线存取收回的数据处理系统 Expired - Lifetime CN100481036C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/954,809 2004-09-30
US10/954,809 US7130943B2 (en) 2004-09-30 2004-09-30 Data processing system with bus access retraction

Publications (2)

Publication Number Publication Date
CN101027655A CN101027655A (zh) 2007-08-29
CN100481036C true CN100481036C (zh) 2009-04-22

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Family Applications (1)

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CNB2005800326734A Expired - Lifetime CN100481036C (zh) 2004-09-30 2005-09-01 具备总线存取收回的数据处理系统

Country Status (6)

Country Link
US (1) US7130943B2 (https=)
EP (1) EP1805631A2 (https=)
JP (1) JP2008515091A (https=)
KR (1) KR20070053310A (https=)
CN (1) CN100481036C (https=)
WO (1) WO2006039040A2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006172256A (ja) * 2004-12-17 2006-06-29 Renesas Technology Corp 情報処理装置
KR100725417B1 (ko) * 2006-02-22 2007-06-07 삼성전자주식회사 우선 순위에 따른 플래시 메모리의 연산 처리 장치 및 방법
US20080034146A1 (en) * 2006-08-04 2008-02-07 Via Technologies, Inc. Systems and Methods for Transactions Between Processor and Memory
US20080040590A1 (en) * 2006-08-11 2008-02-14 Lea Hwang Lee Selective branch target buffer (btb) allocaiton
US20080040591A1 (en) * 2006-08-11 2008-02-14 Moyer William C Method for determining branch target buffer (btb) allocation for branch instructions
US10521329B2 (en) * 2015-05-08 2019-12-31 Intergral GmbH Debugging system
US20260010373A1 (en) * 2024-07-02 2026-01-08 Qualcomm Incorporated Memory prefetch mechanism based on instruction sets

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5021950A (en) * 1984-12-27 1991-06-04 Kabushiki Kaisha Toshiba Multiprocessor system with standby function
US5297292A (en) * 1990-05-11 1994-03-22 Hitachi, Ltd. Bus system wherein a bus-using request signal is issued in advance of a determination that a bus is to be used and is thereafter cancelled if the bus is not used
US5553247A (en) * 1988-12-30 1996-09-03 Alcatel Cit Method for unblocking a multibus multiprocessor system
US20020144054A1 (en) * 2001-03-30 2002-10-03 Fanning Blaise B. Prefetch canceling based on most recent accesses

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4620278A (en) * 1983-08-29 1986-10-28 Sperry Corporation Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus
CA1248239A (en) * 1984-10-30 1989-01-03 Kenneth R. Jaskowiak Equal access bus arbiter
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US5467295A (en) * 1992-04-30 1995-11-14 Intel Corporation Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
US5647057A (en) * 1992-08-24 1997-07-08 Texas Instruments Incorporated Multiple block transfer mechanism
JP2765484B2 (ja) * 1994-07-06 1998-06-18 日本電気株式会社 システムバス制御回路
US6098115A (en) * 1998-04-08 2000-08-01 International Business Machines Corporation System for reducing storage access latency with accessing main storage and data bus simultaneously
JP2002041445A (ja) * 2000-05-19 2002-02-08 Matsushita Electric Ind Co Ltd 高性能ｄｍａコントローラ
CN1318993C (zh) * 2001-10-16 2007-05-30 皇家飞利浦电子股份有限公司 计算机系统和操作计算机系统的方法
JP2005158035A (ja) * 2003-11-05 2005-06-16 Matsushita Electric Ind Co Ltd 調停回路及びこれに備える機能処理回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5021950A (en) * 1984-12-27 1991-06-04 Kabushiki Kaisha Toshiba Multiprocessor system with standby function
US5553247A (en) * 1988-12-30 1996-09-03 Alcatel Cit Method for unblocking a multibus multiprocessor system
US5297292A (en) * 1990-05-11 1994-03-22 Hitachi, Ltd. Bus system wherein a bus-using request signal is issued in advance of a determination that a bus is to be used and is thereafter cancelled if the bus is not used
US20020144054A1 (en) * 2001-03-30 2002-10-03 Fanning Blaise B. Prefetch canceling based on most recent accesses

Also Published As

Publication number Publication date
KR20070053310A (ko) 2007-05-23
WO2006039040A2 (en) 2006-04-13
CN101027655A (zh) 2007-08-29
WO2006039040A3 (en) 2006-11-30
US20060069830A1 (en) 2006-03-30
EP1805631A2 (en) 2007-07-11
JP2008515091A (ja) 2008-05-08
US7130943B2 (en) 2006-10-31

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Address after: American California

Patentee after: APPLE Inc.

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Patentee before: Zenith investment LLC

Effective date of registration: 20150623

Address after: American California

Patentee after: Zenith investment LLC

Address before: Texas in the United States

Patentee before: FREESCALE SEMICONDUCTOR, Inc.

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Granted publication date: 20090422