CN101027655A - 具备总线存取收回的数据处理系统 - Google Patents
具备总线存取收回的数据处理系统 Download PDFInfo
- Publication number
- CN101027655A CN101027655A CNA2005800326734A CN200580032673A CN101027655A CN 101027655 A CN101027655 A CN 101027655A CN A2005800326734 A CNA2005800326734 A CN A2005800326734A CN 200580032673 A CN200580032673 A CN 200580032673A CN 101027655 A CN101027655 A CN 101027655A
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- CN
- China
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- access request
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- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000012545 processing Methods 0.000 title description 5
- 238000000034 method Methods 0.000 claims description 63
- 230000008569 process Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 10
- 239000004020 conductor Substances 0.000 description 8
- WABPQHHGFIMREM-YPZZEJLDSA-N lead-205 Chemical compound [205Pb] WABPQHHGFIMREM-YPZZEJLDSA-N 0.000 description 8
- 230000002457 bidirectional effect Effects 0.000 description 7
- 229910003460 diamond Inorganic materials 0.000 description 7
- 239000010432 diamond Substances 0.000 description 7
- 230000007246 mechanism Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 210000004247 hand Anatomy 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000005224 forefinger Anatomy 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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Images
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
Description
Claims (46)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/954,809 | 2004-09-30 | ||
US10/954,809 US7130943B2 (en) | 2004-09-30 | 2004-09-30 | Data processing system with bus access retraction |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101027655A true CN101027655A (zh) | 2007-08-29 |
CN100481036C CN100481036C (zh) | 2009-04-22 |
Family
ID=36100525
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005800326734A Active CN100481036C (zh) | 2004-09-30 | 2005-09-01 | 具备总线存取收回的数据处理系统 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7130943B2 (zh) |
EP (1) | EP1805631A2 (zh) |
JP (1) | JP2008515091A (zh) |
KR (1) | KR20070053310A (zh) |
CN (1) | CN100481036C (zh) |
WO (1) | WO2006039040A2 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006172256A (ja) * | 2004-12-17 | 2006-06-29 | Renesas Technology Corp | 情報処理装置 |
KR100725417B1 (ko) * | 2006-02-22 | 2007-06-07 | 삼성전자주식회사 | 우선 순위에 따른 플래시 메모리의 연산 처리 장치 및 방법 |
US20080034146A1 (en) * | 2006-08-04 | 2008-02-07 | Via Technologies, Inc. | Systems and Methods for Transactions Between Processor and Memory |
US20080040591A1 (en) * | 2006-08-11 | 2008-02-14 | Moyer William C | Method for determining branch target buffer (btb) allocation for branch instructions |
US20080040590A1 (en) * | 2006-08-11 | 2008-02-14 | Lea Hwang Lee | Selective branch target buffer (btb) allocaiton |
US10521329B2 (en) * | 2015-05-08 | 2019-12-31 | Intergral GmbH | Debugging system |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4620278A (en) * | 1983-08-29 | 1986-10-28 | Sperry Corporation | Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus |
CA1248239A (en) * | 1984-10-30 | 1989-01-03 | Kenneth R. Jaskowiak | Equal access bus arbiter |
JPS61156338A (ja) * | 1984-12-27 | 1986-07-16 | Toshiba Corp | マルチプロセツサシステム |
US4987529A (en) * | 1988-08-11 | 1991-01-22 | Ast Research, Inc. | Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters |
FR2642246B1 (fr) * | 1988-12-30 | 1991-04-05 | Cit Alcatel | Procede de deblocage d'un systeme multiprocesseurs multibus |
JP2986176B2 (ja) * | 1990-05-11 | 1999-12-06 | 株式会社日立製作所 | バス権制御方式およびバスシステム |
US5467295A (en) * | 1992-04-30 | 1995-11-14 | Intel Corporation | Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit |
US5647057A (en) * | 1992-08-24 | 1997-07-08 | Texas Instruments Incorporated | Multiple block transfer mechanism |
JP2765484B2 (ja) * | 1994-07-06 | 1998-06-18 | 日本電気株式会社 | システムバス制御回路 |
US6098115A (en) * | 1998-04-08 | 2000-08-01 | International Business Machines Corporation | System for reducing storage access latency with accessing main storage and data bus simultaneously |
JP2002041445A (ja) * | 2000-05-19 | 2002-02-08 | Matsushita Electric Ind Co Ltd | 高性能dmaコントローラ |
US20020144054A1 (en) * | 2001-03-30 | 2002-10-03 | Fanning Blaise B. | Prefetch canceling based on most recent accesses |
CN1318993C (zh) * | 2001-10-16 | 2007-05-30 | 皇家飞利浦电子股份有限公司 | 计算机系统和操作计算机系统的方法 |
JP2005158035A (ja) * | 2003-11-05 | 2005-06-16 | Matsushita Electric Ind Co Ltd | 調停回路及びこれに備える機能処理回路 |
-
2004
- 2004-09-30 US US10/954,809 patent/US7130943B2/en not_active Expired - Lifetime
-
2005
- 2005-09-01 EP EP05793539A patent/EP1805631A2/en not_active Withdrawn
- 2005-09-01 WO PCT/US2005/031115 patent/WO2006039040A2/en not_active Application Discontinuation
- 2005-09-01 JP JP2007534610A patent/JP2008515091A/ja active Pending
- 2005-09-01 KR KR1020077007211A patent/KR20070053310A/ko not_active Withdrawn
- 2005-09-01 CN CNB2005800326734A patent/CN100481036C/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN100481036C (zh) | 2009-04-22 |
US20060069830A1 (en) | 2006-03-30 |
JP2008515091A (ja) | 2008-05-08 |
WO2006039040A2 (en) | 2006-04-13 |
US7130943B2 (en) | 2006-10-31 |
KR20070053310A (ko) | 2007-05-23 |
EP1805631A2 (en) | 2007-07-11 |
WO2006039040A3 (en) | 2006-11-30 |
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Legal Events
Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: APPLE COMPUTER, INC. Free format text: FORMER OWNER: TIANDING INVESTMENT CO., LTD. Effective date: 20150623 Owner name: TIANDING INVESTMENT CO., LTD. Free format text: FORMER OWNER: FISICAL SEMICONDUCTOR INC. Effective date: 20150623 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150623 Address after: American California Patentee after: APPLE Inc. Address before: American California Patentee before: Zenith investment LLC Effective date of registration: 20150623 Address after: American California Patentee after: Zenith investment LLC Address before: Texas in the United States Patentee before: FREESCALE SEMICONDUCTOR, Inc. |