CN100479151C - 多芯片封装体 - Google Patents

多芯片封装体 Download PDF

Info

Publication number
CN100479151C
CN100479151C CNB2006101727466A CN200610172746A CN100479151C CN 100479151 C CN100479151 C CN 100479151C CN B2006101727466 A CNB2006101727466 A CN B2006101727466A CN 200610172746 A CN200610172746 A CN 200610172746A CN 100479151 C CN100479151 C CN 100479151C
Authority
CN
China
Prior art keywords
circuit
semiconductor chip
chip
analog circuit
characteristic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2006101727466A
Other languages
English (en)
Other versions
CN101034699A (zh
Inventor
竹泽良典
长谷川和弘
浅野隆浩
中田崇司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN101034699A publication Critical patent/CN101034699A/zh
Application granted granted Critical
Publication of CN100479151C publication Critical patent/CN100479151C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

在半导体芯片(1)上，形成数字电路(2)以及模拟电路(3)。并且，在半导体芯片(1)上，还形成非易失性寄存器(4)以保存用于调整模拟电路(3)的电路特性的信息。根据保存在该非易失性寄存器(4)中的信息，调整模拟电路(3)的电路特性。于是，经由粘合剂(12)按照与模拟电路(3)的电路区域重叠的方式安装其它半导体假芯片(11)，从而形成多芯片封装体。

Description

多芯片封装体
技术领域
本发明涉及一种在半导体芯片上形成的模拟电路的特性的稳定性。
背景技术
如今，半导体芯片为模拟电路与数字电路混装的情况较多。所谓模拟电路是指采用模拟值的信号作为数据的电路的总称，例如包括：基准电压产生电路、锁相环路(PLL)、模拟/数字变换电路、数字/模拟变换电路、相位比较电路等。所谓数字电路是指采用数字值的信号作为数据的电路的总称，包含由各种逻辑电路构成的运算电路或存储器等。
一般，数字电路处理数字信号，从而抗噪音能力强并且能够以微弱的信号执行动作，因此高速且低消耗功率。另一方面，模拟电路处理模拟信号，从而是一种由电源电压、温度、制造偏差等易于使动作特性变动的电路。因此，通过由保护(fuse)电路或EEPROM等构成的非易失性寄存器，调整模拟电路的特性。
图5表示过去的半导体芯片封装的俯视图，图6表示图5的半导体芯片封装中的C-C线剖视图。在半导体芯片101上形成数字电路102以及模拟电路103。并且，在半导体芯片101上，还形成非易失性寄存器104以保存用于调整模拟电路103的电路特性的信息。根据保存在该非易失性寄存器104中的信息，调整模拟电路103的电路特性。在数字电路102、模拟电路103以及非易失性寄存器104上涂敷绝缘膜。
并且，在半导体芯片101的周边部分，具有与这些数字电路102、模拟电路103及半导体芯片的外部进行信号收发的焊盘(pad)107。焊盘107是用于将金属线109与引线架108(图5中未图示)引线接合的电极。
图7为半导体芯片101的模拟电路103以及非易失性寄存器104的示例。在模拟电路103中，将由带隙基准(BGR：bandgap reference)电路111所生成的电压Vin由运算放大器112的+输入端子输入，并从运算放大器112输出输出电压Vout。在输出电压Vout与接地电压GND之间，串联连接电阻R1、R2、R3、R4、R5。电阻R1与电阻R2之间的端子电压，经由开关S1由运算放大器112的-输入端子输入。同样地，电阻R2与电阻R3之间的端子电压，经由开关S2由运算放大器112的-输入端子输入；电阻R3与电阻R4之间的端子电压，经由开关S3由运算放大器112的-输入端子输入；电阻R4和电阻R5之间的端子电压，经由开关S4由运算放大器112的-输入端子输入。开关S1、S2、S3、S4，根据保存在非易失性寄存器104中的信息，仅接通(ON)其中任一个而将其它三个断开(OFF)。
在此，令Rtotal＝R1+R2+R3+R4+R5。例如，当开关S1接通时，输出电压Vout成为Vout＝Vin×Rtotal/(R2+R3+R4+R5)。同样，当开关S2接通时，输出电压Vout成为Vout＝Vin×Rtotal/(R3+R4+R5)。当开关S3接通时，输出电压Vout成为Vout＝Vin×Rtotal/(R4+R5)。当开关S4接通时，输出电压Vout成为Vout＝Vin×Rtotal/(R5)。这样，通过对使S1、S2、S3、S4中的哪一个接通进行选择，可调整模拟电路103的电路特性即输出电压Vout。
非易失性寄存器104由通过保护电路或EEPROM等非易失性存储器保存信息的存储电路构成，该保护电路或EEPROM根据有无因激光照射引起的熔丝元件的切断来保存信息。非易失性寄存器104，根据所保存的信息，输出仅使开关S1、S2、S3、S4中的任一个接通的信号。
在图5所例示的半导体芯片101的生产工序中，优选早期筛选出(screening)模拟电路103的电路特性的劣质品。因此，在晶片上形成半导体芯片101的状态下，在所谓的晶片分类(sort)的阶段，根据保存在非易失性寄存器104中的信息判定模拟电路103的电路特性是否进入许可范围内。
但是，由此可知，如果在晶片阶段将调整了模拟电路103的电路特性的半导体芯片101封装并由模压树脂密封，则在晶片阶段所调整的电路特性会产生变化。
专利文献1：特开2002-100729号公报
发明内容
本发明是鉴于上述问题而产生的，其目的在于适当抑制由封装改变非易失性寄存器所特性调整的模拟电路的电路特性。
并且，本发明的目的还在于，即使在根据保存在非易失性寄存器中的信息没有调整模拟电路的电路特性的情况下，也适当抑制由封装改变模拟电路的电路特性。
本发明是一种多芯片封装体，具有：第一半导体芯片；形成在所述第一半导体芯片上的模拟电路；形成在所述第一半导体芯片上的数字电路；形成在所述第一半导体芯片上且对所述模拟电路进行调整的非易失性寄存器；和按照完全重叠所述模拟电路的方式经由粘合剂与所述第一半导体芯片粘接的第二半导体芯片。
进而，本发明是上述粘合剂不包含填充剂的多芯片封装体，或者是上述第二半导体芯片为假芯片的多芯片封装体。
并且，本发明是上述第二半导体芯片在其表面上形成电路区域的多芯片封装体。
另外，本发明是一种多芯片封装体，具有：第一半导体芯片；形成在所述第一半导体芯片上的模拟电路；形成在所述第一半导体芯片上的数字电路；和按照完全重叠所述模拟电路的方式经由粘合剂与所述第一半导体芯片粘接的第二半导体芯片。
通过采用本发明，可以适当抑制由封装改变非易失性寄存器所特性调整的模拟电路的电路特性。
附图说明
图1为本发明涉及的芯片封装的第一实施方式的俯视图。
图2为图1的实施方式的A-A线剖视图。
图3为本发明涉及的芯片封装的第二实施方式的俯视图。
图4为图3的实施方式的B-B线剖视图。
图5为过去的半导体封装的俯视图。
图6为图5的半导体芯片封装的C-C线剖视图。
图7为半导体芯片的模拟电路及非易失性寄存器的例子。
图中：1、21-半导体芯片(第一半导体芯片)，2-数字电路，3-模拟电路，4-非易失性寄存器，5-焊盘，7-焊盘，8-引线架，9-金属线，11、31-半导体芯片(第二半导体芯片)，12-粘合剂，37-焊盘，39-金属线。
具体实施方式
图1表示本发明的第一实施方式的半导体多芯片封装体的俯视图，图2表示图1的半导体多芯片封装体的A-A线剖视图。在半导体芯片1上形成数字电路2以及模拟电路3。并且，在半导体芯片1上，还形成非易失性寄存器4以保存用于调整模拟电路3的电路特性的信息。根据保存在该非易失性寄存器4中的信息，调整模拟电路3的电路特性。在数字电路2、模拟电路3以及非易失性寄存器4上涂敷绝缘膜。
本实施方式的特征在于，按照与由非易失性寄存器调整了电路特性的模拟电路3的电路区域重叠的方式经由粘合剂12安装其它半导体假(dummy)芯片11的多芯片封装体。半导体假芯片11，通过配置在其背面的粘合剂12、例如特特殊双面胶带(ダイアタツチテ一プ)安装在半导体芯片1的模拟电路3的电路区域上。此外，粘合剂12也可以是环氧类树脂等非导电性膏剂。
在半导体芯片1的周边部分，具有与这些数字电路2、模拟电路3及半导体芯片1的外部进行信号收发的焊盘7。焊盘7是用于将金属线9与引线架8(在图1中未图示)引线接合的电极。半导体芯片1的模拟电路3以及非易失性寄存器4例如与图7相同。其后，用模压树脂密封半导体芯片1以及半导体假芯片11，形成多芯片封装体。
通过采用这样的多芯片封装体的结构，可以适当抑制由封装改变非易失性寄存器所特性调整的模拟电路的电路特性。其原因之一可认为是基于模压树脂密封的模拟电路3的电路区域表面中的应力被缓和。
另外，粘合剂优选不含填充剂。因为如果粘合剂12包含填充剂，则模拟电路3的区域上的填充剂会局部影响对模拟电路3的应力。
图3表示本发明的第二实施方式的半导体多芯片封装体的俯视图，图4表示图3的半导体多芯片封装体的B-B线剖视图。有关与第一实施方式相同的结构附加相同的号码，并省略说明。
第二实施方式与第一实施方式的不同点在于，在半导体芯片21的模拟电路3的电路区域上安装的不是半导体假芯片11，而替换为半导体芯片31。在半导体芯片31上形成有电路区域。半导体芯片31可认为是例如由DRAM或SRAM等各种存储器芯片或各种运算电路构成的多半导体集成电路芯片。通过金属线39将半导体芯片31上的焊盘37与半导体芯片21上的焊盘5之间引线接合，从而半导体芯片31上的电路与半导体芯片21上的电路电连接。
由此，在本实施方式中，不仅可适当抑制由封装改变非易失性寄存器所特性调整的模拟电路3的电路特性，并且因为还能将多芯片封装体内的层叠芯片作为电路区域有效地进行利用，所以作为多芯片封装体整体可以提高电路的集成度。
另外，第一实施方式的半导体假芯片11和半导体芯片1，优选由相同的材料组成的基板例如由硅基板构成，同样地，第二实施方式的半导体芯片31和半导体芯片21，也优选由相同材料组成的基板构成。这是因为所层叠的半导体芯片为相同材料组成的基板一方将缓和基于模压树脂密封的模拟电路3的电路区域表面的应力。
在上述实施方式中，虽然例示了可适当抑制由封装改变非易失性寄存器所特性调整的模拟电路3的电路特性，但并非限于此。即使在根据保存在非易失性寄存器中的信息没有调整模拟电路的电路特性的情况下，通过经由粘合剂12按照与该模拟电路的电路区域重叠的方式安装其它的半导体假芯片11，也可适当抑制由封装改变模拟电路的电路特性。

Claims (5)

1、一种多芯片封装体，具有：
第一半导体芯片；
形成在所述第一半导体芯片上的模拟电路；
形成在所述第一半导体芯片上的数字电路；
形成在所述第一半导体芯片上且对所述模拟电路进行调整的非易失性寄存器；和
按照完全重叠所述模拟电路的方式经由粘合剂与所述第一半导体芯片粘接的第二半导体芯片。
2、根据权利要求1所述的多芯片封装体，其特征在于，
所述第二半导体芯片是假芯片。
3、根据权利要求1所述的多芯片封装体，其特征在于，
所述第二半导体芯片，在其表面上形成有电路区域。
4、一种多芯片封装体，具有：
第一半导体芯片；
形成在所述第一半导体芯片上的模拟电路；
形成在所述第一半导体芯片上的数字电路；和
按照完全重叠所述模拟电路的方式经由粘合剂与所述第一半导体芯片粘接的第二半导体芯片。
5、根据权利要求1～4中任一项所述的多芯片封装体，其特征在于，
所述第二半导体芯片，由与所述第一半导体芯片相同材料组成的基板构成。
CNB2006101727466A 2006-03-06 2006-12-30 多芯片封装体 Expired - Fee Related CN100479151C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006059772 2006-03-06
JP2006059772A JP4958257B2 (ja) 2006-03-06 2006-03-06 マルチチップパッケージ

Publications (2)

Publication Number Publication Date
CN101034699A CN101034699A (zh) 2007-09-12
CN100479151C true CN100479151C (zh) 2009-04-15

Family

ID=38478125

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101727466A Expired - Fee Related CN100479151C (zh) 2006-03-06 2006-12-30 多芯片封装体

Country Status (3)

Country Link
US (1) US7701068B2 (zh)
JP (1) JP4958257B2 (zh)
CN (1) CN100479151C (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8779599B2 (en) * 2011-11-16 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages including active dies and dummy dies and methods for forming the same
KR101936355B1 (ko) * 2012-11-22 2019-01-08 에스케이하이닉스 주식회사 멀티-칩 시스템 및 반도체 패키지
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
KR102477352B1 (ko) * 2017-09-29 2022-12-15 삼성전자주식회사 반도체 패키지 및 이미지 센서

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3175981B2 (ja) * 1992-10-28 2001-06-11 株式会社東芝 トリミング回路
JPH08204582A (ja) * 1995-01-20 1996-08-09 Fujitsu Ltd 半導体集積回路
JP3268740B2 (ja) 1997-08-20 2002-03-25 株式会社東芝 Ａｓｉｃの設計製造方法、スタンダードセル、エンベッテドアレイ、及びマルチ・チップ・パッケージ
JPH11168185A (ja) * 1997-12-03 1999-06-22 Rohm Co Ltd 積層基板体および半導体装置
JP3224796B2 (ja) * 1999-09-20 2001-11-05 ローム株式会社 半導体装置
JP3831593B2 (ja) 2000-09-21 2006-10-11 三洋電機株式会社 マルチチップモジュール
JP4243077B2 (ja) * 2002-07-23 2009-03-25 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP2004146816A (ja) * 2002-09-30 2004-05-20 Matsushita Electric Ind Co Ltd 固体撮像装置およびこれを用いた機器
JP4615189B2 (ja) * 2003-01-29 2011-01-19 シャープ株式会社 半導体装置およびインターポーザチップ
JP3948430B2 (ja) * 2003-04-03 2007-07-25 ソニー株式会社 半導体集積回路の製造方法
JP2004363187A (ja) 2003-06-02 2004-12-24 Denso Corp 半導体パッケージ
JP4366472B2 (ja) * 2003-11-19 2009-11-18 Ｏｋｉセミコンダクタ株式会社 半導体装置
JP2006186375A (ja) * 2004-12-27 2006-07-13 Samsung Electronics Co Ltd 半導体素子パッケージ及びその製造方法
KR100843137B1 (ko) * 2004-12-27 2008-07-02 삼성전자주식회사 반도체 소자 패키지
TWI263314B (en) * 2005-10-26 2006-10-01 Advanced Semiconductor Eng Multi-chip package structure
TWI305410B (en) * 2005-10-26 2009-01-11 Advanced Semiconductor Eng Multi-chip package structure

Also Published As

Publication number Publication date
JP2007242705A (ja) 2007-09-20
US20070210456A1 (en) 2007-09-13
JP4958257B2 (ja) 2012-06-20
CN101034699A (zh) 2007-09-12
US7701068B2 (en) 2010-04-20

Similar Documents

Publication Publication Date Title
US6337579B1 (en) Multichip semiconductor device
US6603196B2 (en) Leadframe-based semiconductor package for multi-media card
KR101239271B1 (ko) 집적 회로 디바이스 내에서의 테스트를 위한 패턴을내부적으로 생성하는 시스템 및 방법
CN100592509C (zh) 半导体装置及胶囊型半导体封装
US6476474B1 (en) Dual-die package structure and method for fabricating the same
US6768660B2 (en) Multi-chip memory devices and modules including independent control of memory chips
US20010028114A1 (en) Semiconductor device including memory unit and semiconductor module including memory units
CN100479151C (zh) 多芯片封装体
US20050140022A1 (en) Multi-chip package structure
US9922959B2 (en) Semiconductor device
JP2004128363A (ja) 半導体装置及び入力ピン容量の設定方法
US5353250A (en) Pin programmable dram that provides customer option programmability
US11594522B2 (en) Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
KR100837823B1 (ko) 온도 정보를 공유하는 다수의 반도체 칩을 포함하는 멀티칩 패키지
US5303180A (en) Pin programmable dram that allows customer to program option desired
US8350374B2 (en) Multi-chip package including chip address circuit
JPS63132459A (ja) 容量内蔵半導体パツケ−ジ
JPH04162657A (ja) 半導体装置用リードフレーム
US6826067B2 (en) Double capacity stacked memory and fabrication method thereof
US6437629B1 (en) Semiconductor device with circuit for adjusting input/output terminal capacitance
JPH10294429A (ja) 半導体装置
KR101977145B1 (ko) 멀티 칩 패키지
US20050253259A1 (en) Integrated circuit packaging method and structure for redistributing configuration thereof
US20170364115A1 (en) Semiconductor device
JP2001035994A (ja) 半導体集積回路装置およびシステム基板

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090415

Termination date: 20121230