CN100477123C - 用于减小多晶硅高度的SOI底部预掺杂合并e-SiGe - Google Patents

用于减小多晶硅高度的SOI底部预掺杂合并e-SiGe Download PDF

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Publication number
CN100477123C
CN100477123C CNB200610075110XA CN200610075110A CN100477123C CN 100477123 C CN100477123 C CN 100477123C CN B200610075110X A CNB200610075110X A CN B200610075110XA CN 200610075110 A CN200610075110 A CN 200610075110A CN 100477123 C CN100477123 C CN 100477123C
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silicon body
doping
layer
transistor
boron
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Expired - Fee Related
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CNB200610075110XA
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Chinese (zh)
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CN1855391A (zh
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幸山裕亮
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H10D30/875—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] having thin-film semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface

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  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CNB200610075110XA 2005-04-18 2006-04-18 用于减小多晶硅高度的SOI底部预掺杂合并e-SiGe Expired - Fee Related CN100477123C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/107,843 2005-04-18
US11/107,843 US7605042B2 (en) 2005-04-18 2005-04-18 SOI bottom pre-doping merged e-SiGe for poly height reduction

Publications (2)

Publication Number Publication Date
CN1855391A CN1855391A (zh) 2006-11-01
CN100477123C true CN100477123C (zh) 2009-04-08

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Country Status (4)

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US (1) US7605042B2 (https=)
JP (1) JP2006319326A (https=)
CN (1) CN100477123C (https=)
TW (1) TWI307532B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104425281B (zh) * 2013-09-09 2018-08-24 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
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JP2007281038A (ja) * 2006-04-03 2007-10-25 Toshiba Corp 半導体装置
JP5287621B2 (ja) * 2009-09-10 2013-09-11 富士通セミコンダクター株式会社 半導体装置
CN103794559A (zh) * 2012-10-29 2014-05-14 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
CN104217953B (zh) * 2013-06-05 2017-06-13 中芯国际集成电路制造(上海)有限公司 Pmos晶体管及其制作方法
US9281196B2 (en) * 2013-12-31 2016-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method to reduce etch variation using ion implantation
CN105990142A (zh) * 2015-02-03 2016-10-05 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其制作方法

Citations (7)

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US5663570A (en) * 1993-07-12 1997-09-02 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip
US5869359A (en) * 1997-08-20 1999-02-09 Prabhakar; Venkatraman Process for forming silicon on insulator devices having elevated source and drain regions
US6051509A (en) * 1997-03-25 2000-04-18 Kabushiki Kaisha Toshiba Semiconductor integrated circuit manufacturing method and device
CN1437769A (zh) * 1999-12-30 2003-08-20 英特尔公司 具有部分隔离的源/漏结的场效应晶体管结构及其制造方法
CN1444281A (zh) * 2002-03-11 2003-09-24 日本电气株式会社 薄膜半导体器件及其制造该器件的方法
CN1527379A (zh) * 2003-03-04 2004-09-08 ̨������·����ɷ����޹�˾ 具有晶格不相称区的变形沟道晶体管结构及其制造方法
CN1595624A (zh) * 2004-06-18 2005-03-16 北京大学 一种准soi场效应晶体管器件的制备方法

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EP0459763B1 (en) * 1990-05-29 1997-05-02 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistors
JPH06310719A (ja) * 1993-04-19 1994-11-04 Sharp Corp Ｇｅ−ＳｉのＳＯＩ型ＭＯＳトランジスタ及びその製造方法
US6633066B1 (en) 2000-01-07 2003-10-14 Samsung Electronics Co., Ltd. CMOS integrated circuit devices and substrates having unstrained silicon active layers
US6303450B1 (en) * 2000-11-21 2001-10-16 International Business Machines Corporation CMOS device structures and method of making same
US6593625B2 (en) 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6780686B2 (en) * 2002-03-21 2004-08-24 Advanced Micro Devices, Inc. Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions
TW530385B (en) 2002-03-27 2003-05-01 Taiwan Semiconductor Mfg CMOS with strain-balanced structure and method of manufacturing the same
US6911379B2 (en) 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
US7138309B2 (en) * 2005-01-19 2006-11-21 Sharp Laboratories Of America, Inc. Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer

Patent Citations (7)

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Publication number Priority date Publication date Assignee Title
US5663570A (en) * 1993-07-12 1997-09-02 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip
US6051509A (en) * 1997-03-25 2000-04-18 Kabushiki Kaisha Toshiba Semiconductor integrated circuit manufacturing method and device
US5869359A (en) * 1997-08-20 1999-02-09 Prabhakar; Venkatraman Process for forming silicon on insulator devices having elevated source and drain regions
CN1437769A (zh) * 1999-12-30 2003-08-20 英特尔公司 具有部分隔离的源/漏结的场效应晶体管结构及其制造方法
CN1444281A (zh) * 2002-03-11 2003-09-24 日本电气株式会社 薄膜半导体器件及其制造该器件的方法
CN1527379A (zh) * 2003-03-04 2004-09-08 ̨������·����ɷ����޹�˾ 具有晶格不相称区的变形沟道晶体管结构及其制造方法
CN1595624A (zh) * 2004-06-18 2005-03-16 北京大学 一种准soi场效应晶体管器件的制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104425281B (zh) * 2013-09-09 2018-08-24 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法

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TW200644129A (en) 2006-12-16
US7605042B2 (en) 2009-10-20
JP2006319326A (ja) 2006-11-24
US20060234432A1 (en) 2006-10-19
TWI307532B (en) 2009-03-11
CN1855391A (zh) 2006-11-01

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