CN100470839C - Semiconductor device employing an extension spacer - Google Patents

Semiconductor device employing an extension spacer Download PDF

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Publication number
CN100470839C
CN100470839C CNB2005101232562A CN200510123256A CN100470839C CN 100470839 C CN100470839 C CN 100470839C CN B2005101232562 A CNB2005101232562 A CN B2005101232562A CN 200510123256 A CN200510123256 A CN 200510123256A CN 100470839 C CN100470839 C CN 100470839C
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semiconductor substrate
dielectric
semiconductor element
extension spacer
grid
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CN1812126A (en
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陈光鑫
钟堂轩
黄健朝
温政国
李迪弘
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention provides a semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.

Description

Utilize the semiconductor element of extension spacer
Technical field
The present invention relates to a kind of semiconductor element, particularly relevant for a kind of semiconductor element that utilizes extension spacer.
Background technology
In the past in decades, the size of semiconductor element (for example MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)) and the reduction of internal characteristics can continue to make moderate progress on speed, usefulness, density and cost on the integrated circuit of per unit function.According to one of transistorized design and intrinsic characteristic thereof, adjust the length of grid below channel region between transistor source and the drain electrode, can change the relevant resistance of channel region, influence transistorized usefulness by this.Particularly, suppose that other parameters all are maintained at definite value, the length that shortens channel region can reduce the resistance of source transistor best drain electrode, therefore when applying enough voltage at transistor gate, can increase the magnitude of current between source electrode and the drain electrode.
(meaning is that source electrode is the below that is positioned at the base material upper surface with drain electrode, forms the basis of base material upper surface exactly) can add the length of clearance wall with the definition channel region around grid in the transistor environment with indent source electrode and drain electrode.Particularly, the source electrode of source electrode and drain electrode and drain region form by ion implantation technology usually, its be utilization grid and clearance wall as mask to define source electrode and drain region separately.Therefore, the width of the clearance wall around the grid directly influences the source electrode of source electrode and drain electrode and the size and the position of drain region.Clearance wall is thinner or thinner thin, and the source electrode that forms around the channel region and the source electrode of drain electrode and drain region are just more approaching.Therefore, the length of reduction channel region is just reduced the resistance of source electrode to drain electrode, in potential mode and then improve transistorized usefulness
In order more to strengthen performance of transistors, can import tension force (Strain) to improve carrier transport factor at transistor channel region.In general, having need be at (the N-Type Metal OxideSemiconductor of N type metal-oxide-semiconductor (MOS); NMOS) direction of the channel region of element along source electrode to drain electrode imports tensile stress (Tensile Stress), and imports compression stress (Compressive Stress) in the direction of channel region along source electrode to drain electrode of P type metal-oxide-semiconductor (MOS) (PMOS) element.
The general technology that produces tension force is included in after the construction transistor, deposits heavily stressed film on the transistor and in base material.Heavily stressed film or stress riser (Stressor) apply appreciable impact to channel region, change the silicon crystal lattice spacing of channel region, thereby import tension force herein.In this example, stress riser is to be deposited on the transistor.The method is to be described in detail in clear water people such as (Shimizu) to publish the 433rd page to 436 pages, exercise question at the technical papers summary of international electronic component meeting of calendar year 2001 be " zone machines Tension Control (Local Mechanical Stress Control; LMC): a kind of innovative techniques that is used to promote CMOS usefulness ", also classify list of references of the present invention herein as.
According to transistorized design feature, the thin thin clearance wall of utilization can increase the tension force in the channel region around transistor gate.From the above, a kind of common method that imports tension force is the heavily stressed film of deposition on transistor.Therefore, if the clearance wall around the grid is thin more, the heavily stressed film that is then deposited (for example contact etch stop layer) is just more near channel region.So heavily stressed film can apply the higher tension force of degree in channel region, thereby increase the interior tension effect of transistorized channel region.
Be and show conclusive feature although add thin thin clearance wall, yet the clearance wall around the transistor gate still has relevant restriction at transistor.The metal silication district that one of more general restriction forms for the clearance wall around the grid can make transistor source and drain electrode go up is near transistorized channel region.If pass the lightly doped drain (it is generally to be adjacent to channel region) of source electrode or drain electrode and spreads in the metal silication district, can produce electrical passage and pass source electrode or drain electrode via metal silication district to channel region.Therefore, the metal silication district can produce short circuit in channel region, thereby provides metal silicide spike thing (Spike) in potential mode in transistor.
In view of the above, in fact be necessary to provide a kind of semiconductor element in known techniques, it is to add thin thin clearance wall around the grid, is beneficial to reduce the length of channel region, simultaneously and solve the many disadvantages of known techniques.
This shows that above-mentioned conventional semiconductor element obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem that semiconductor element exists, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new semiconductor element, just become the current industry utmost point to need improved target.
Because the defective that above-mentioned conventional semiconductor element exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of new semiconductor element that utilizes extension spacer, can improve general conventional semiconductor element, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to, overcoming the defective that the conventional semiconductor element exists, is to make it reduce the length of channel region and a kind of semiconductor element that utilizes extension spacer of new structure, technical problem to be solved are provided, reach technical advantage, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of semiconductor element that is formed on the semiconductor substrate that the present invention proposes, it comprises at least: a grid, and this grid is on this semiconductor substrate; One dielectric underlay, this dielectric underlay is on the pair of sidewalls of this grid; On a pair of horizontal side wall of the formation of one clearance wall and this dielectric underlay, wherein this clearance wall is to be formed by dielectric material, and an outer rim of this clearance wall is the outer rim of aiming at this dielectric underlay; One extension spacer, this extension spacer are to adjoin the outer rim of this dielectric underlay and extend laterally along this semiconductor substrate to cross this dielectric underlay; One source pole and drain region, this source electrode and drain region are below the upper surface of this semiconductor substrate and be adjacent to a channel region below this grid, and this source electrode and drain region are the belows that extends to this dielectric underlay and this extension spacer; And a metal silication district, this metal silication district extends laterally to cross this extension spacer above this source electrode of part and drain region and along this semiconductor substrate.
The object of the invention to solve the technical problems also adopts following technical measures further to realize.
The aforesaid semiconductor element that is formed on the semiconductor substrate, wherein said semiconductor substrate are silicon substrate on the insulating barrier, and silicon substrate comprises a base material, a flush type insulating barrier that is positioned at the below and a silicon layer that is positioned at the top on this insulating barrier.
The aforesaid semiconductor element that is formed on the semiconductor substrate, wherein a plurality of shallow-channel isolation regions are to be formed on this flush type insulating barrier.
The aforesaid semiconductor element that is formed on the semiconductor substrate, wherein said grid comprise a gate dielectric layer and a gate electrode.
The aforesaid semiconductor element that is formed on the semiconductor substrate, wherein said source electrode and drain region comprise: a lightly doped drain, this lightly doped drain is in the below of this upper surface of this semiconductor substrate and is adjacent to this channel region of this grid below, and this lightly doped drain is the below that extends to this dielectric underlay and this extension spacer; And one source pole and drain region, this source electrode and drain region are in the below of this upper surface of this semiconductor substrate and are adjacent to this lightly doped drain.
The aforesaid semiconductor element that is formed on the semiconductor substrate, it comprises that at least a contact etch stop layer is positioned on a plurality of parts of this semiconductor element.
The aforesaid semiconductor element that is formed on the semiconductor substrate, it comprises that at least an inner layer dielectric layer is positioned on this contact etch stop layer.
The aforesaid semiconductor element that is formed on the semiconductor substrate, the thickness of wherein said extension spacer are that essence is between 30 dust to 100 dusts.
The aforesaid semiconductor element that is formed on the semiconductor substrate, the integral thickness of wherein said this dielectric underlay are the integral thickness that is different from this extension spacer, and this integral thickness comprises horizontal direction thickness and vertical direction thickness.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, can reach technical advantage usually by an advantageous embodiment of the invention, method wherein of the present invention comprises the semiconductor element that is formed on the semiconductor substrate.In one embodiment, this semiconductor element is included in grid on the semiconductor substrate and the dielectric underlay on gate lateral wall.This semiconductor element also comprises extension spacer, and this extension spacer is to adjoin dielectric underlay and extend laterally along semiconductor substrate to cross dielectric underlay.This semiconductor element more comprises source electrode and drain region, this source electrode and drain region be positioned at semiconductor substrate upper surface the below and be adjacent to the channel region of grid below.Aforementioned source electrode and drain region extend to the below of dielectric underlay and extension spacer.This semiconductor element comprises the metal silication district in addition, and this metal silication district extends laterally to cross extension spacer above the source electrode of part and drain region and along semiconductor substrate.Therefore, the metal silication district then is positioned at the source electrode of part and the top of drain region, and extension spacer is between dielectric underlay and metal silication district.
Look it with another viewpoint, the invention provides a kind of method that forms semiconductor element on semiconductor substrate, in one embodiment, the method comprises the formation grid on semiconductor substrate, and forms dielectric underlay on the sidewall of grid.The method also comprises the formation extension spacer, and this extension spacer is to adjoin dielectric underlay and extend laterally along semiconductor substrate to cross dielectric underlay.The method more comprises and forms source electrode and drain region in the below of the upper surface of semiconductor substrate and be adjacent to the channel region of grid below.Aforementioned source electrode and drain region are the belows that extends to dielectric underlay and extension spacer.The method comprises that again forming the metal silication district extends laterally in the top of the source electrode of part and drain region and along semiconductor substrate and cross extension spacer.
Look it with another viewpoint, semiconductor element is presented as the transistor that is formed on the semiconductor substrate.In one embodiment, this transistor is included in the grid on the semiconductor substrate, and is positioned at first dielectric underlay and second dielectric underlay on the relative a plurality of sidewalls of grid.This transistor also comprises.This transistor comprises first extension spacer and second extension spacer again, and this first extension spacer and this second extension spacer are to adjoin first dielectric underlay and second dielectric underlay respectively and extend laterally respectively along semiconductor substrate to cross first dielectric underlay and second dielectric underlay.This transistor more comprises source electrode, and this source electrode is below the upper surface of semiconductor substrate and be adjacent to channel region below the grid.Aforementioned source electrode extends to the below of first dielectric underlay and first extension spacer.This transistor comprises drain electrode in addition, and this drain electrode is below the upper surface of semiconductor substrate and be adjacent to channel region below the grid.This drain electrode extends to the below of second dielectric underlay and second extension spacer.This transistor comprises the first metal silication district and the second metal silication district again, this first metal silication district and this second metal silication district are respectively above the source electrode of part and drain electrode, and extend laterally respectively along semiconductor substrate and to cross first extension spacer and second extension spacer.
In sum, the semiconductor element that utilizes extension spacer that the present invention is special, the length of minimizing channel region is reached technical advantage.It has above-mentioned many advantages and practical value, and in like product and method, do not see have similar structural design and method to publish or use and really genus innovation, no matter it all has bigger improvement on product structure, method or function, have large improvement technically, and produced handy and practical effect, and the multinomial effect that has enhancement than the conventional semiconductor element, thereby be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 to Fig. 7 is the profile that illustrates the embodiment of principle construction semiconductor element according to the present invention.
110: base material 115: the flush type insulating barrier
120: silicon layer 125: shallow-channel isolation region
130: gate dielectric layer 135: gate electrode
140: lightly doped drain 145: channel region
150: dielectric underlay 160: clearance wall
170: extension spacer 180: source electrode and drain region
190: metal silication district 194: the contact etch stop layer
198: inner layer dielectric layer
Embodiment
The manufacturing and the use of several preferred embodiments of the present invention below are described in detail in detail.Yet what can know from experience is the invention provides many applicable inventive concepts, and aforesaid inventive concept to be embodied in the various specified conditions.The specific embodiment of being inquired into only exemplifies with the ad hoc fashion manufacturing and uses the present invention, but not in order to limit category of the present invention.
The present invention will narrate about several preferred embodiments in the specified conditions, i.e. transistor and relevant formation method thereof.Only generally speaking, principle of the present invention also can be applicable to the semiconductor element of other similar construction and similar integrated circuit.For example, embodiments of the invention can be used for forming NOR gate (NORGate), gate (Logic Gate), inverter (Inverter), XOR gate (XOR Gate), NAND gate (NAND Gate), draw high (the P-Type MetalOxide Semiconductor of (Pull-Up) transistorized P type metal-oxide-semiconductor (MOS); PMOS) circuit of N type metal-oxide-semiconductor (MOS) (NMOS) element of element, pulled transistor etc.
See also Fig. 1 to Fig. 7, it is the profile that illustrates the embodiment of principle construction semiconductor element (for example transistor) according to the present invention.In the transition step of Fig. 1, transistor is partly to be established on the semiconductor substrate (also to be called " base material "), this semiconductor substrate is silicon (Silicon-On-Insulator) " or body silicon (Bulk Silicon) " base material on the insulating barrier for example, (110) or the quartz of (111) surface crystallization direction (SurfaceOrientation) comprise that the base material 110 that is positioned at the below " has (100);; the P type of pottery etc. or N type silicon substrate " such as, flush type insulating barrier 115 " for example " insulator "; the flush type oxide layer of 3500 dusts " and the silicon layer 120 that is positioned at the top, wherein about 1500 dusts of the thickness of silicon layer 120 and being positioned on a plurality of parts of flush type insulating barrier 115 according to appointment.Flush type insulating barrier 115 and be positioned at the top silicon layer 120 be utilize conventional process be formed at the below base material 110 on.Another kind of mode, base material can be formed by the body silicon with (100) surface crystallization direction.
A plurality of shallow-channel isolation regions 125 are the tops that are formed at flush type insulating barrier 115, pass be positioned at the top silicon layer 120 and around transistor.Can utilize the photoresist mask on flush type insulating barrier 115, to define each other zone and form a plurality of shallow-channel isolation regions 125.Then, etch shallow-channel isolation region 125 and with the dielectric material back-filling in shallow-channel isolation region 125, dielectric material silicon dioxide, silicon nitride, above-mentioned combination or other dielectric materials that is fit to such as wherein.In this technical field any have know that usually the knowledgeable can utilize other prior art method to form when understanding isolated area, the regional oxidizing process of silicon technology for example.
Transistorized grid is to be formed by gate dielectric layer 130 and gate electrode 135 construction, its be utilize the silicon layer 120 of known techniques above being positioned at above form and patterned gate dielectric layer 130 and gate electrode 135.Gate dielectric layer 130 is preferable with high " dielectric constant " dielectric material, such as silica, silicon oxynitride, silicon nitride, oxide, nitrogen-containing oxide or above-mentioned combination etc.Gate dielectric layer 130 is preferable to have relative dielectric constant (Relative Permittivity) value greater than about 4.The example of other dielectric materials comprises aluminium oxide, lanthana, hafnium oxide, zirconia, nitrogen hafnium oxide or above-mentioned combination.
In an advantageous embodiments, gate dielectric layer 130 comprises oxide layer, and gate dielectric layer 130 can form by any oxidation technology, allly in the atmosphere that contains oxide, water, nitric oxide or above-mentioned combination, carry out damp and hot oxidizing process or xeothermic oxidizing process, perhaps utilize tetraethyl ortho silicate (Tetraethyl Orthosilicate) and oxygen to carry out the chemical gaseous phase deposition technology as predecessor.In an illustrative embodiments, the thickness of gate dielectric layer 130 is extremely about 50 dusts of about 8 dusts, and its thickness is preferable with about 16 dusts.
Gate electrode 135 comprises conductor material,, metal (as tantalum, titanium, molybdenum, tungsten, platinum, aluminium, hafnium, ruthenium), metal silicide (as titanium silicide, cobalt silicide, nickle silicide, tantalum silicide), metal nitride (as titanium nitride, tantalum nitride), polysilicon (Polycrystalline Silicon), other conductor materials or above-mentioned combination such as through mixing.In an example, amorphous silicon is deposition and recrystallizes to produce polysilicon (that also claim is " Polysilicon ").In an advantageous embodiments, gate electrode 135 is a polysilicon, and this gate electrode 135 can form through doping or undoped polycrystalline silicon by Low Pressure Chemical Vapor Deposition deposition, make its thickness between about 400 dusts between about 2500 dusts, and be preferable with about 1500 dusts.
Gate dielectric layer 130 and gate electrode 135 can be by the patternings in addition of the little shadow technology known to the known techniques.By and large, little shadow technology comprises the deposition photoresist, and this photoresist is through shade, exposure and development then.After the photoresist mask patternization, can carry out etch process to remove the undesired part of grid dielectric material and gate electrode material, to form gate dielectric layer 130 and gate electrode 135.In one embodiment, gate electrode 135 is to be formed by polysilicon, and gate dielectric layer 130 is an oxide, and etch process can be wet type or dry type, anisotropy or etc. the phasic property etch process, be preferable so with the anisotropy dry etch process.
The width of gate electrode 135 is the functions that are about to the pattern of construction semiconductor element.For example, the ratio in hole mobility of the reducible grade of the grid width at the NMOS element of the grid width of PMOS element electron mobility in body silicon or strained silicon (Strained Silicon).In brief, the grid of semiconductor element described herein and the size of other features are according to the pattern that is about to the construction semiconductor element and application and different.
Seeing also Fig. 2, is the profile of the embodiment of the lightly doped drain (Lightly Doped Drain) 140 that principle forms transistor source and drain electrode according to the present invention.Purpose for clarity, source electrode or drain electrode also can refer to " source electrode and drain region ".A plurality of lightly doped drains 140 be the upper surface below that is arranged in silicon substrate 110 on the insulating barrier, the silicon layer above being positioned at 120 and be adjacent to channel region 145 below the grid.Lightly doped drain 140 forms shallow joint and is adjacent to channel region 145 below the transistor gate in the silicon substrate 110 on insulating barrier.
Generally speaking, in order to form transistorized lightly doped drain 140, it is to be mask with the grid, and the boron ion (or other P shape admixtures) of PMOS element or the arsenic ion (or other N shape admixtures) of NMOS element are injected the silicon layer 120 that is positioned at the top.The ion implantation technology of P shape admixture or N shape admixture can in about 1 kilo electron volt (keV) to about 5keV the energy rank, 2 * 10 14Atom/square centimeter is to 3 * 10 15The dosage of atom/square centimeter carries out.The illustration degree of depth of lightly doped drain 140 is about 100 dusts.According to transistor orientation described herein, lightly doped drain 140 has (100) surface crystallization direction.
See also Fig. 3, it is the profile that illustrates the embodiment of a plurality of clearance walls of principle formation transistor according to the present invention.Further it, transistor comprises that dielectric underlay 150, clearance wall 160 and extension spacer 170 are around the grid and above the upper surface of silicon substrate on the insulating barrier 110.Dielectric underlay 150 (also being called " first dielectric underlay and second dielectric underlay ") is on the sidewall (being relative sidewall) that is formed at grid, and clearance wall 160 (also being called " first clearance wall and second clearance wall ") then is formed on the dielectric underlay 150.Dielectric underlay 150 and clearance wall 160 no matter be indivedual or its combination, can refer to above-mentioned transistor gate thin thin clearance wall on every side.
For more obvious so, formed extension spacer 170 (also being called " first extension spacer and second extension spacer ") be adjoin dielectric underlay 150 and on the insulating barrier silicon substrate 110 extend laterally respectively and cross dielectric underlay 150 and clearance wall 160.Dielectric underlay 150 and extension spacer 170 are generally the one layer or more oxide layer, this oxide layer is to form by any oxidation technology, such as in the atmosphere that contains oxide, water, nitric oxide or above-mentioned combination, carry out damp and hot oxidizing process or xeothermic oxidizing process, perhaps utilize tetraethyl ortho silicate and oxygen to carry out the chemical gaseous phase deposition technology as predecessor.In an illustrative embodiments, the width of dielectric underlay 150 is about 50 dusts to about 400 dusts, and is preferable with about 150 dusts.In an illustrative embodiments, the thickness of extension spacer 170 is about 10 dusts to about 150 dusts, and is preferable with about 30 dusts to about 100 dusts, and about 50 dusts of its width are to about 400 dusts.
The clearance wall 160 that forms another ion infusion generally comprises silicon nitride, silicon oxynitride or above-mentioned combination.In an illustrative embodiments, clearance wall 160 is to be formed by silicon nitride layer, and wherein this silicon nitride layer is to have utilized silicomethane and ammonia to carry out the chemical gaseous phase deposition technology as predecessor and form.The ratio of the thickness of the width of clearance wall 160 and dielectric underlay 150 is less than 5, and being preferable less than 3.
By waiting tropism or anisotropic etch process patternable clearance wall 160.When using isotropic etching technology, can utilize phosphoric acid solution and be etch-stop with dielectric underlay 150.In view of in the zone of adjacent gate electrode 135, the thickness of clearance wall 160 is bigger, therefore isotropic etching is removed the silicon nitride (it is to form clearance wall 160) of gate electrode 135 tops, and the zone of silicon substrate 110 non-direct adjacent gate electrodes 135 on the removal insulating barrier, and stay taper (Tapered) clearance wall 160.Clearance wall 160 width are to look transistor gate length and different.In an illustrative embodiments, the ratio of clearance wall 160 width and gate electrode length is about 0.8 to about 1.5.
For example utilize hydrofluoric acid solution to wait tropism's wet etching process, patternable dielectric underlay 150.Also can use other etchants, for example the mixture of the concentrated sulfuric acid and hydrogen peroxide is commonly referred to as Piranha (Piranha) solution.The phosphoric acid solution of phosphoric acid and water also can be used for patterned dielectric sark 150.For example utilize hydrofluoric acid solution to carry out wet etching process such as tropism such as another grade, patternable extension spacer 170.Also can use other etchants, the mixture of the concentrated sulfuric acid and hydrogen peroxide for example is with patterning extension spacer 170.
What should be careful is herein, and the width of clearance wall generally is to look the pattern of semiconductor element and different.For example, found that relatively large clearance wall is more favourable for the I/O element, this is that the magnitude of current because of the I/O element is that expection is accessible.Relatively large clearance wall is also more favourable for the PMOS element, and the relatively large clearance wall of particularly having found the PMOS element helps to reduce tensile stress thereon.In above-mentioned example, clearance wall is that design is into about greater than 10 percentages.In order to make the clearance wall of different in width, must add extra masking piece, deposition and etching step.
See also Fig. 4, it is to illustrate the profile that according to the present invention principle forms the embodiment of the source electrode of transistor source and drain electrode and drain region 180.Carrying out ion implantation technology and Rapid Thermal tempering process more than 1000 ℃, (mention once more to produce source electrode and drain region 180, though be shallow junction), this source electrode and drain region 180 are below and silicon layers 120 above being arranged in of the upper surface of silicon substrate 110 on insulating barrier.Generally speaking, source electrode and drain region 180 for the doped crystal pipe, it is to be mask with grid and clearance wall 160, and the boron ion (or other P shape admixtures) of PMOS element or the arsenic ion (or other N shape admixtures) of NMOS element are injected the silicon layer 120 that is positioned at the top.Ion implantation technology can in about 5keV to about 40keV the energy rank, 1 * 10 14Atom/square centimeter is to 5 * 10 15The dosage of atom/square centimeter carries out.The illustration degree of depth of source electrode and drain region 180 is about 200 dusts.According to transistor orientation described herein, source electrode and drain region 180 have (100) surface crystallization direction.Moreover, can carry out extra ion infusion connects face with the generation different brackets configuration.
Therefore, transistor provides shallow junction relevant advantage in conjunction with the insulating barrier of source electrode and drain electrode in the silicon substrate 110.Shown in graphic, lightly doped drain 140 is the belows that extend to dielectric underlay 150, clearance wall 160 and extension spacer 170, (extends to the below of dielectric underlay 150 and extension spacer 170) and be adjacent to the channel region 145 of grid below below the upper surface that is positioned at silicon substrate 110 on the insulating barrier.It is very shallow that yet this connects the face degree of depth, thereby keep the relevant advantage of transistor, under the situation of transistor " unlatching (On) " electric current, can present shallow junction, especially reduces short-channel effect and " closing (Off) " electric current or electric leakage.
See also Fig. 5, it is to illustrate the profile that according to the present invention principle forms the embodiment in transistorized metal silication district 190.Generally, silication technique for metal comprises depositing metal layers, and nickel, cobalt, palladium, platinum, copper, molybdenum, titanium, tantalum, tungsten, erbium, zirconium or above-mentioned combination etc. make metal level and pasc reaction then, thereby form metal silicide such as.In an illustrative embodiments, the metal of silication technique for metal utilization comprises nickel, cobalt, platinum, palladium or above-mentioned combination etc. at least.Metal level can form by conventional deposition technique, such as vapour deposition method, sputter-deposited method or chemical vapour deposition technique etc.
Before depositing metal layers, be preferable to remove native oxide (Native Oxide) by cleaning wafer.Cleaning solution can use and comprise hydrofluoric acid, sulfuric acid, hydrogen peroxide, Ammonia or above-mentioned combination etc.When carrying out silication technique for metal, can make the silicon area (for example source electrode and drain region 180) and polysilicon region (gate electrode 135) reaction of metal level selectivity and exposure by tempering step, to form metal silicide.In an advantageous embodiments, metal level comprises nickel, platinum, palladium, cobalt at least, and silication technique for metal then forms nickle silicide, platinum silicide, palladium silicide or cobalt silicide respectively.The excessive material of metal level can be removed by the infiltration of for example wetting (Wet Dip) method, and wherein wet infusion method is to carry out in solution such as sulfuric acid, hydrogen peroxide or ammonium hydroxide.
Shown in graphic, metal silication district 190 is positioned at the source electrode of part and the top of drain region 180 (also be called " the first metal silication district and the second metal silication district " and lay respectively at the source electrode of part and the top of drain electrode), and silicon substrate 110 is crossed dielectric underlay 150 and extension spacer 170 to extend laterally away from the direction of grid on the insulating barrier.Therefore, metal silication district 190 is positioned at the source electrode of part and the top of drain region 180, and extension spacer 170 is then between dielectric underlay 150 and metal silication district 190.The length of transistor channel region 145 can be reduced in the width range of dielectric underlay 150, and near the clearance wall 160 the grid is just thinner relatively.Thus, can have the short advantage of channel region 145 length according to transistor of the present invention.In addition, the distance between extension spacer 170 control channel regions 145 and the metal silication district 190 is to reduce the possibility of above-mentioned metal silicide spike thing.According to the above, transistor is benefited by other situations, for example strengthen the strain effect (relevant) in the transistorized channel region 145 with following contact etch stop layer, and the width that can optionally adjust extension spacer 170 is to reduce ill-effect, for example the metal silicide spike thing in transistor.
In another embodiment, metal silication district 190 can remove extension spacer 170 from transistor, or remove its major part after being formed at the top of source electrode partly and drain region 180.Extension spacer 170 already defines and keep a segment distance between channel region 145 and metal silication district 190, just need not keep extension spacer 170 afterwards.In this example, for example utilize hydrofluoric acid solution to wait tropism's wet etching process, can remove extension spacer 170.Also can use other etchants, for example the mixture of the concentrated sulfuric acid and hydrogen peroxide is commonly referred to as Piranha solution.The phosphoric acid solution of phosphoric acid and water also can be used for removing extension spacer 170.
See also Fig. 6, it is to illustrate according to the present invention principle forms contact etch stop layer 194 on transistor profile.Contact etch stop layer 194 (generally being presented as high voltage thin film) is to be formed on transistorized a plurality of part, with along＜100〉crystallization direction produce tensile stress.Contact etch stop layer 194 can be silicon nitride or any other tensile stress material, and can form by chemical vapor deposition method.Just as known to the general known techniques and employed, chemical vapor deposition method can be low-pressure chemical vapor deposition process, rapid heat chemical gas-phase deposition, atomic layer chemical vapor deposition technology or the reinforced chemical vapor deposition method of plasma.
In an advantageous embodiments, the direction of the tensile stress of contact etch stop layer 194 utilizations along source electrode to drain electrode is between about 2.0 ten hundred million handkerchiefs (GigaPascal) between about 5,000 ten thousand handkerchiefs (Mega Pascal).The thickness of contact etch stop layer 194 is between about 1000 dusts between about 300 dusts.In one embodiment, contact etch stop layer 194 can comprise that wherein low-pressure chemical vapor deposition process has the intensity of about 1.2 ten hundred million handkerchiefs by the silicon nitride of low-pressure chemical vapor deposition process deposition; And in another embodiment, contact etch stop layer 194 can comprise that by the silicon nitride of the reinforced chemical vapor deposition method deposition of plasma, wherein the reinforced chemical vapor deposition method of plasma has the intensity of about 0.7 ten hundred million handkerchiefs.
When the contact etch stop layer 194 of NMOS element was the tensile stress film, the contact etch stop layer 194 of PMOS element can be compression stress film or unstressed film.The compression stress film causes the direction of channel region along source electrode to drain electrode of PMOS element to produce compression stress, and increases hole mobility.By and large, 194 pairs of channel regions 145 of contact etch stop layer apply remarkable influence, not only change channel region 145 silicon crystal lattice spacings, thereby import strain in wherein.The strain effect that imports gained at transistorized channel region 145 improves carrier transport factor, and then promotes transistorized usefulness.
See also Fig. 7, it is the profile that illustrates the inner layer dielectric layer 198 of the principle according to the present invention.Inner layer dielectric layer 198 is to be formed on the contact etch stop layer 194.Inner layer dielectric layer 198 generally has flat surfaces and can comprise the silica that forms by deposition technique, wherein deposition technique chemical vapour deposition technique for example.The thickness of inner layer dielectric layer 198 can be between about 1500 dusts between about 8000 dusts, and are preferable with about 3000 dusts to about 4000 dusts.Moreover in an advantageous embodiments, inner layer dielectric layer 198 is along＜100〉crystallization direction apply tensile stress, its intensity between about 0.1 ten hundred million handkerchiefs between about 2.0 ten hundred million handkerchiefs.Afterwards, can utilize standard process techniques, comprise the treatment step that forms a plurality of plain conductors and metal level, formation interlayer hole and connector and encapsulation etc., to finish transistorized manufacturing.
So far, introduced to have easily and obtained and a kind of semiconductor element of measurable advantage and forming method thereof.In this technical field any have know that usually the knowledgeable should understand, this semiconductor element is in aforesaid embodiment and relevant formation method thereof for the purpose of illustration usefulness only, and other embodiment that semiconductor element that utilizes the thin thin clearance wall with extension spacer can be provided are also in broad scope of the present invention.
Moreover, though the present invention and advantage thereof describe in detail as above, yet be understandable that, in the spirit and scope that attached claim defined after not breaking away from the present invention, when doing various changes to the present invention, replace and retouch.For example, many technologies of above-mentioned discussion can be implemented or replace or aforesaid combination with other technologies by distinct methods.
In addition, scope of the present invention be not limited in the specific embodiment, this technical field of technology, mechanism, goods, constituent, means, method and step that specification addresses any have know that usually the knowledgeable should know from experience easily from disclosure of the present invention, according to the present invention and utilize related embodiment described herein, can make existing or future technology, mechanism, goods, constituent, means, method or step, carry out the essence identical function or reach the essence identical result development.Therefore, the present invention means the category that comprises above-mentioned technology, mechanism, goods, constituent, means, method or step.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.

Claims (9)

1, a kind of semiconductor element that is formed on the semiconductor substrate is characterized in that it comprises at least:
One grid, this grid is on this semiconductor substrate;
One dielectric underlay, this dielectric underlay is on the pair of sidewalls of this grid;
On a pair of horizontal side wall of the formation of one clearance wall and this dielectric underlay, wherein this clearance wall is to be formed by dielectric material, and an outer rim of this clearance wall is the outer rim of aiming at this dielectric underlay;
One extension spacer, this extension spacer are to adjoin this outer rim of this dielectric underlay and extend laterally along this semiconductor substrate to cross this dielectric underlay;
One source pole and drain region, this source electrode and drain region are below the upper surface of this semiconductor substrate and be adjacent to a channel region below this grid, and this source electrode and drain region are the belows that extends to this dielectric underlay and this extension spacer; And
One metal silication district, wherein this metal silication district extends laterally to cross this extension spacer above this source electrode partly and drain region and along this semiconductor substrate.
2, the semiconductor element that is formed on the semiconductor substrate according to claim 1, it is characterized in that wherein said semiconductor substrate is a silicon substrate on the insulating barrier, and silicon substrate comprises a base material, a flush type insulating barrier that is positioned at the below and a silicon layer that is positioned at the top on this insulating barrier.
3, the semiconductor element that is formed on the semiconductor substrate according to claim 2 is characterized in that wherein a plurality of shallow-channel isolation regions are to be formed on this flush type insulating barrier.
4, the semiconductor element that is formed on the semiconductor substrate according to claim 1 is characterized in that wherein said grid comprises a gate dielectric layer and a gate electrode.
5, the semiconductor element that is formed on the semiconductor substrate according to claim 1 is characterized in that wherein said source electrode and drain region comprise:
One lightly doped drain, this lightly doped drain are in the below of this upper surface of this semiconductor substrate and are adjacent to this channel region of this grid below, and this lightly doped drain is the below that extends to this dielectric underlay and this extension spacer; And
One source pole and drain region, this source electrode and drain region are in the below of this upper surface of this semiconductor substrate and are adjacent to this lightly doped drain.
6, the semiconductor element that is formed on the semiconductor substrate according to claim 1 is characterized in that it comprises that at least a contact etch stop layer is positioned on a plurality of parts of this semiconductor element.
7, the semiconductor element that is formed on the semiconductor substrate according to claim 6 is characterized in that it comprises that at least an inner layer dielectric layer is positioned on this contact etch stop layer.
8, the semiconductor element that is formed on the semiconductor substrate according to claim 1, the thickness that it is characterized in that wherein said extension spacer are between 30 dust to 100 dusts.
9, the semiconductor element that is formed on the semiconductor substrate according to claim 1, the integral thickness that it is characterized in that wherein said this dielectric underlay is the integral thickness that is different from this extension spacer, and this integral thickness comprises horizontal direction thickness and vertical direction thickness.
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