TW201318032A - Semiconductor device and method of forming epitaxial layer - Google Patents

Abstract

A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.

Description

Semiconductor device and method of fabricating epitaxial layer

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having an epitaxial layer and a method of fabricating the epitaxial layer thereof.

As semiconductors move toward miniaturized sizes, the size of the gate, source, and drain of the transistor continues to shrink as the feature size decreases. However, due to the limitation of the physical properties of the material, the reduction of the size of the gate, the source and the drain may cause a decrease in the amount of the current-determining carrier in the transistor element, thereby affecting the performance of the transistor. Therefore, increasing the carrier mobility to increase the speed of the MOS transistor has become a major issue in the field of semiconductor technology.

In the currently known technique, a strained germanium layer can be formed using a selective epitaxial growth (SEG) process. For example, after the gate is formed, a germanium epitaxial layer is formed in a predetermined region of the source/drain, wherein the lattice constant of germanium is 5.431 angstroms (angstrom, A), and the lattice constant of germanium is 5.646 angstroms. The lattice constant of the germanium epitaxial layer is larger than that of the germanium, so that the band structure of the germanium changes, and the strained germanium layer is formed. The strained ruthenium layer helps to provide stress to the channel region of the PMOS transistor to improve its carrier mobility.

In addition, since electronic products currently need to have a plurality of component regions of different functions at the same time to meet the diversified needs of consumers, and each component region has a different pattern density due to different specifications, characteristics, and the like. In order to reduce the process variability caused by the micro-loading effect, a semiconductor process such as a selective epitaxial growth process of a corresponding region may be separately performed according to the element pattern density, however, this method will increase the production cost and time. Therefore, how to overcome the micro-load effect and simultaneously complete the component regions having different pattern densities in the same semiconductor process is a problem that the related art desires to improve.

It is an object of the present invention to provide a semiconductor device having an epitaxial layer and a method of fabricating the epitaxial layer thereof to overcome process variability caused by a micro-loading effect caused by element pattern density.

A preferred embodiment of the present invention provides a method of making an epitaxial layer, the steps of which are as follows. A semiconductor substrate is provided and the semiconductor substrate has at least one recess. Performing a first selective epitaxial growth (SEG) process to form a first epitaxial layer in the recess, wherein the first selective epitaxial growth process has an operating pressure, and the operating pressure is substantially Less than or equal to 10 torr.

A preferred embodiment of the present invention provides a method of making an epitaxial layer, the steps of which are as follows. A semiconductor substrate is provided and the semiconductor substrate has at least one recess. Performing a first selective epitaxial growth process to form a first epitaxial layer in the recess, wherein the first selective epitaxial growth process comprises introducing a gas, the gas comprising Dichlorosilane (DCS), Hydrane (GeH ₄ ), hydrogen chloride (HCl), etc., and gases such as dichloromethane, decane, and hydrogen chloride have a concentration ratio (0.5-2.1): (1.5-3.3):1.

A preferred embodiment of the present invention provides a semiconductor device including a semiconductor substrate and a plurality of transistors. The semiconductor substrate has at least one iso region or open region, and at least one dense region. A plurality of transistors are respectively disposed in the wide area and the dense area, and each of the transistors includes at least one source/drain region, wherein the source/drain regions each include a first portion having a bottom thickness and a side thickness The epitaxial layer, and the bottom thickness of the first epitaxial layer is substantially greater than or equal to the thickness of the side of the first epitaxial layer.

The invention provides a selective epitaxial growth process with low operating pressure to form an epitaxial layer having a bottom thickness greater than a side thickness in the groove, and further applying the low operating pressure selective epitaxial growth process to the semiconductor substrate a plurality of regions having different pattern densities to simultaneously form an epitaxial layer having a structural feature having a bottom thickness substantially greater than or equal to the thickness of the side edges in the recess to avoid process variability caused by microloading effects, such as avoiding wide An epitaxial layer having a bottom thickness substantially smaller than the thickness of the side is formed in the groove of the sparse region, which contributes to improving the reliability of the electrical performance of the semiconductor device.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to Figures 1 to 6. 1 to 6 are schematic views showing a method of fabricating an epitaxial layer according to a first preferred embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 10 including at least one recess 12 is provided. The semiconductor substrate 10 can define a plurality of regions (not shown) thereon, and each region has a respective pattern density. To simplify the description, it is now exemplified to form a transistor in a region having any element density. The semiconductor substrate 10 can comprise, for example, a substrate comprised of a gallium arsenide, a blanket overlying (SOI) layer, an epitaxial layer, a germanium layer, or other semiconductor substrate material. The semiconductor substrate 10 can further include at least one gate structure 14 and at least one shallow trench isolation 16 and the recess 12 is located in the active region between the gate structure 14 and the shallow trench isolation 16. The gate structure 14 includes a gate dielectric layer 18, a gate conductive layer 20 disposed on the gate dielectric layer 18, and a cap layer 22 disposed on the gate conductive layer 20. The gate dielectric layer 18 may be formed of an insulating material such as tantalum oxide, oxynitride or a high-k dielectric layer having a dielectric constant greater than 4 formed by a process such as thermal oxidation or deposition. The gate conductive layer 20 may be composed of a conductive material such as polysilicon, metal halide or a metal material having a specific work function. The selectively formed cap layer 22 may be composed of a dielectric material such as tantalum nitride, hafnium oxide or hafnium oxynitride. The shallow trench isolation 16 may comprise an insulating material such as tantalum oxide. The method of forming the gate structure 14 and the shallow trench isolation 16 is well known to those skilled in the art and will not be further described herein.

The method of forming the recess 12 may include the following steps: first, selectively forming a first sidewall 24 on the sidewall of each gate structure 14; thereafter, using the formed gate structure 14 and the first sidewall spacer 24 as a mask The mask is subjected to an etching process, such as an anisotropic dry etching process, in which the recesses 12 are formed in the semiconductor substrate 10 on both sides of the gate structure 14. In addition, a dry and wet etching process may be mixed to form various shapes such as a barrel shape (a straight shape), a hexagonal shape, and a polygonal groove 12, which are formed in the groove 12 of such a shape in a subsequent process. The epitaxial layer in the layer will provide greater stress to the channel region. The material of the first sidewall 24 may include a single film layer or a composite film layer structure such as yttrium oxide or tantalum nitride, and the first sidewall 24 may serve as a temporary spacer spacer, and thus the first sidewall The sub- 24 is selectively partially or completely removed after the selective epitaxial growth process is completed, but is not limited thereto.

In order to form a better quality epitaxial layer in the recess 12, a pre-clean step may be performed before the subsequent epitaxial layer process, for example, by diluting a hydrofluoric acid aqueous solution or containing sulfuric acid. A cleaning solution such as hydrogen peroxide or a SPM mixed solution of deionized water to remove an impurity such as a native oxide layer on the surface of the groove 12. In addition, a pre-bake may be performed, such as heating the semiconductor substrate 10 in a chamber in which hydrogen is introduced to remove the native oxide layer or residual cleaning liquid on the surface of the recess 12.

As shown in FIG. 2, a first selective epitaxial growth (SEG) process is performed to form a first epitaxial layer 26 on the surface of the recess 12. The first selective epitaxial growth process of the preferred embodiment includes an operating pressure and the operating pressure is substantially less than or equal to 10 torr. For example, in a chamber having an operating pressure substantially less than or equal to 10 Torr, a gas including Dichlorosilane (DCS), decane (GeH ₄ ), and hydrogen chloride (HCl) is introduced to form a first epitaxial layer. 26 is within the recess 12 such that the first epitaxial layer 26 comprises a first material having a lattice constant different from the lattice constant of the semiconductor substrate 10, for example including germanium (SiGe). Among them, dichlorosilane (DCS) is a helium source material gas, decane (GeH ₄ ) is a source material gas, and the concentration ratio of dichlorosilane to the concentration of decane can determine one of the first materials. The first enthalpy (Ge) concentration, preferably, the concentration ratio of chlorin is substantially less than the concentration ratio of decane. In addition, hydrogen chloride is used to assist in the selective formation of the first epitaxial layer, so that the germanium epitaxial layer is formed only on the germanium substrate on the surface of the recess 12, and is not formed of a material such as oxide or tantalum nitride. The shallow trench isolation 16 or the first sidewall sub-section 24. Preferably, the concentration ratio of hydrogen chloride is substantially between the concentration ratio of dichlorosilane and the concentration ratio of decane. In the mixed gas forming the first epitaxial layer 26, the concentration ratio of the gas such as dichloromethane, decane, and hydrogen chloride may be (0.5 - 2.1): (1.5 - 3.3): 1 to form the first ruthenium concentration system. The first epitaxial layer 26 is between 20% and 30%. For example, in the present embodiment, a preferred concentration ratio of a gas such as dichloromethane, decane, and hydrogen chloride is 0.97:2.2:1 to form a first epitaxial layer 26 having a first concentration of 25%, but not This is limited.

It should be noted that the first epitaxial layer 26 of the preferred embodiment includes a bottom thickness t1 and a side edge thickness t2, and the bottom thickness t1 of the first epitaxial layer 26 is substantially smaller than the depth of the groove 12. H1, that is, the first epitaxial layer 26 does not completely fill the recess 12. In addition, the bottom thickness t1 of the first epitaxial layer 26 is substantially greater than or equal to the side thickness t2 of the first epitaxial layer 26, that is, the ratio of the bottom thickness t1 to the side thickness t2 is substantially greater than or equal to 1, In other words, the thickness of the first epitaxial layer 26 formed on the bottom surface of the recess 12 is substantially greater than or equal to the thickness of the first epitaxial layer 26 formed on the sidewall of the recess 12. In the present embodiment, the ratio of the bottom thickness t1 to the side thickness t2 is preferably substantially greater than or equal to 1.4.

As shown in FIG. 3, next, a second selective epitaxial growth process is performed to form a second epitaxial layer 28 on the first epitaxial layer 26. The second selective epitaxial growth process of the preferred embodiment includes an operating pressure and the operating pressure is substantially between 1 and 10 torr. For example, a gas such as methylene chloride, decane or hydrogen chloride is introduced into the same chamber used to form the first epitaxial layer 26 to form a second epitaxial layer 28 on the first epitaxial layer 26. The second epitaxial layer 28 includes a second material having a lattice constant different from the lattice constant of the semiconductor substrate 10, for example, including germanium, and a second germanium concentration of the second material of the second epitaxial layer 28. The first germanium concentration is substantially greater than the first germanium concentration of the first material of the first epitaxial layer 26, such as the second epitaxial layer 28 having a second germanium concentration of 36%. The second epitaxial layer 28 is then made available to provide stress to the channel region 29 below the gate structure 14.

In addition, as shown in FIG. 4, the second selective epitaxial growth process may also be an in-situ doped ion epitaxial growth process. Therefore, when the second epitaxial layer 28 is formed, At the same time, the second epitaxial layer 28 is doped with a desired conductivity type dopant to form a corresponding source/drain doping region 30. In this embodiment, the second selective epitaxial growth process may be a field-doping boron ion epitaxial growth process, for example, when the transistor to be formed is a PMOS transistor, when forming a second barium containing germanium In the case of the seed layer 28, the desired boron ions are simultaneously implanted in the second epitaxial layer 28 to serve as the corresponding source/drain doping region 30. Alternatively, an annealing process may be selectively performed to activate Source/drain doping region 30.

It should be noted that the first epitaxial layer 26 and the second epitaxial layer 28 preferably comprise the same kind of material, such as a germanium epitaxial layer, but have different composition ratios, such as the germanium concentration of the second epitaxial layer 28. It is substantially larger than the germanium concentration of the first epitaxial layer 26. In addition, the second epitaxial layer 28 includes a conductive dopant such as boron ions, and the first epitaxial layer 26 preferably does not include a conductive dopant, and the first epitaxial layer 26 is disposed on the second epitaxial layer 28 and the semiconductor substrate. 10, to avoid the conductive type dopant of the second epitaxial layer 28 being directly diffused to the semiconductor substrate 10 by lattice dislocation between the epitaxial layer and the semiconductor substrate 10, resulting in the subsequently formed transistor 32. Abnormal electrical performance such as leakage. In addition, the operating pressure of the first selective epitaxial growth process of the embodiment is substantially less than or equal to 10 Torr, and the operating pressure of the first selective epitaxial growth process of another embodiment is substantially equal to 50 Torr. Compared with the ear, a volume of the second epitaxial layer 28 of the embodiment is substantially larger than a volume of the second epitaxial layer 28 of the other embodiment, that is, the second epitaxial layer 28 of the present invention can be Directly providing greater stress in the channel region 29. Additionally, the second epitaxial layer 28 can be higher, equal to, or lower than the surface of the semiconductor substrate 10.

Thereafter, as shown in FIG. 5, a third selective epitaxial growth process is performed to form a third epitaxial layer 36 on the second epitaxial layer 28. The third selective epitaxial growth process of the preferred embodiment includes an operating pressure and the operating pressure is substantially between 1 and 10 torr. For example, the third selective epitaxial growth process can be performed in the same chamber used to form the first epitaxial layer 26 and the second epitaxial layer 28, and the germanium source gas such as decane is turned off to separately enter the second A source gas of chlorodecane or the like is introduced into the chamber to form a third epitaxial layer 36 on the second epitaxial layer 28.

Then, as shown in FIG. 6, after the third selective epitaxial growth process is completed, the first sidewall spacers 24 are selectively removed or partially removed, and then a second sidewall spacer 34 is formed. The second side wall sub- 34 may be a single layer or a multi-layer structure, or may include a liner or the like. The material of the second sidewall 34 may include a high temperature oxide (HTO), tantalum nitride, hafnium oxide or tantalum nitride (HCD-SiN) formed using hexachlorodisilane (Si ₂ Cl ₆ ). ), but not limited to this. In this embodiment, the second sidewall sub-layer 34 does not overlap the third epitaxial layer 36, but not limited thereto, the second sidewall sub-34 may also be disposed on the third epitaxial layer 36, that is, partially overlapped. Three epitaxial layer 36. Finally, the third epitaxial layer 36 is subjected to a self-aligned metal salicide process, and a transistor 32 is thus completed. Since the material of the third epitaxial layer 36 is epitaxial germanium, the third epitaxial layer 36 can cover the defects of the surface of the second epitaxial layer 28, ensuring a subsequent process of self-aligning the salicide. The metal telluride layer can be formed correctly on the third epitaxial layer 36.

In addition, the order of the source/drain doping process and the selective epitaxial growth process can be adjusted according to the design requirements of the transistor. For example, in a preferred embodiment, the gate structure 14 and the second sidewall 34 can be used as a mask, and the second epitaxial layer 28 and the third epitaxial layer 36 are subjected to an ion implantation process and an annealing process to form a mask. Source/drain doping region 30. In another preferred embodiment, before the recess 12 is formed, an ion implantation process is performed on the semiconductor substrate 10, and then each selective epitaxial growth process is performed to form a source/drain doping. Miscellaneous area 30.

The invention is also applicable to non-planar transistors. Please refer to Figures 7 to 9. 7 to 9 are schematic views showing a method of fabricating an epitaxial layer according to a second preferred embodiment of the present invention. As shown in FIG. 7, a semiconductor substrate 10 having at least one fin structure 38 is first provided. The semiconductor substrate 10 includes a plurality of fin structures 38 and shallow trench isolations 16. The material of the fin structure 38 includes, for example, gallium arsenide, a blanket insulating (SOI) layer, an epitaxial layer, a germanium layer, or other semiconductor material. The shallow trench isolation 16 may be filled with a dielectric material and disposed between the fin structures 38 or a bottom oxide layer of a SOI.

Then, at least one gate structure 14 is formed to partially cover the fin structure 38, and the first sidewall portion 24 is selectively formed on the sidewall of the gate structure 14, wherein the extension direction of the gate structure 14 is staggered with the extending direction of the fin structure 38. . As shown in FIG. 8, an etching process is performed by using a patterned photoresist layer (not shown) as a mask, for example, an anisotropic dry etching process to remove a portion of the fin structure to form the recess 12 In the fin structure 38 on both sides of the gate structure 14. As shown in FIG. 9, the first selective epitaxial growth process, the second selective epitaxial growth process, and the third selective epitaxial growth process are sequentially performed to form the first epitaxial layer 26 described above. The second epitaxial layer 28 and the third epitaxial layer 36 are in the recess 12, wherein the operating pressure of the first selective epitaxial growth process is substantially less than or equal to 10 Torr, and thus the first epitaxial layer 26 is formed. The bottom thickness t1 is substantially greater than or equal to its side thickness t2. In addition, the second epitaxial layer 28 can be included with the source/drain doping region 30 in conjunction with an ion implantation process.

Please refer to Figure 10. Figure 10 is a schematic view of a semiconductor device in accordance with a preferred embodiment of the present invention. As shown in FIG. 10, the semiconductor substrate 10 includes at least one iso region 42 or an open region, and at least one dense region, having different element pattern densities. 44, and a plurality of transistors 46/48 are disposed in the wide area 42 and the dense area 44, respectively. Each of the transistors 46/48 includes at least one gate structure 50/52 and at least one source/drain region 54/56, and the source/drain regions 54/56 are respectively disposed on both sides of the gate structure 50/52. In the semiconductor substrate 10. In the present embodiment, the opening width of the source/drain region 54 is substantially equal to the opening width of the source/drain region 56, but not limited thereto, the opening width of the source/drain region 54 may also be It is substantially larger or smaller than the opening width of the source/drain region 56. Furthermore, the present invention is also applicable to source/drain regions having different opening widths in regions of the same element pattern density, for example, the present invention is applicable to A plurality of source/drain regions 54 each having a different opening width in the wide region 42 are provided. Each of the gate structures 50/52 includes a gate dielectric layer 18, a gate conductive layer 20 disposed on the gate dielectric layer 18, and a cap layer 22 disposed on the gate conductive layer 20. The gate dielectric layer 18 may be formed of an insulating material such as tantalum oxide, oxynitride or a high-k dielectric layer having a dielectric constant greater than 4 formed by a process such as thermal oxidation or deposition. The gate conductive layer 20 may be composed of a conductive material such as polysilicon, metal halide or a metal material having a specific work function. The selectively formed cap layer 22 may be composed of a dielectric material such as tantalum nitride, hafnium oxide or hafnium oxynitride. The first sidewalls 24 are selectively disposed on sidewalls of the gate structures 50/52. The source/drain regions 54/56 each include a first epitaxial layer 26 formed by the first selective epitaxial growth process, the second selective epitaxial growth process, and the third selective epitaxial growth process. A second epitaxial layer 28 and a third epitaxial layer 36, and the distribution density of the source/drain regions 54 in the wide region 42 is substantially smaller than the distribution density of the source/drain regions 56 in the dense region 44.

The first selective epitaxial growth process of the preferred embodiment includes an operating pressure, and the operating pressure is substantially less than or equal to 10 torr, such that the first epitaxial region in the wide region 42 and the dense region 44 The layers 26 each have a bottom thickness t3/t5 and a side edge thickness t4/t6, and each bottom thickness t3/t5 is substantially greater than or equal to the corresponding side thickness t4/t6, that is, in each The ratio of the thickness of each bottom portion to the thickness of each side in the region, that is, t3/t4 and t5/t6, is substantially greater than or equal to 1, preferably substantially greater than or equal to 1.4. The second epitaxial layer 28 is disposed on the first epitaxial layer 26, and the first epitaxial layer 26 and the second epitaxial layer 28 respectively comprise a first material having a lattice constant different from the lattice constant of the semiconductor substrate 10. A second material, and both the first material and the second material comprise ruthenium, wherein the first ruthenium concentration of one of the first materials is substantially less than the second ruthenium concentration of one of the second materials. The third epitaxial layer 36 is disposed on the second epitaxial layer 28, and the material of the third epitaxial layer 36 includes germanium.

It should be noted that the first epitaxial layer 26 preferably does not include a conductive type dopant, and the second epitaxial layer 28 includes a conductive type dopant corresponding to the type of the transistor 46/48, including an N-type dopant or a P-type. In the dopant, for example, the second epitaxial layer 28 in the P-type transistor has boron ions, that is, a portion of the second epitaxial layer 28 can serve as a source/drain doping region. The first epitaxial layer 26 is disposed between the second epitaxial layer 28 and the semiconductor substrate 10 such that the second epitaxial layer 28 does not directly contact the semiconductor substrate 10 to prevent the conductive dopant of the second epitaxial layer 28 from being used. The lattice dislocation between the epitaxial layer and the semiconductor substrate 10 directly diffuses to the semiconductor substrate 10, causing abnormal electrical performance such as leakage of the subsequently formed transistor 46/48. Since the operating pressure of the first selective epitaxial growth process of the preferred embodiment is substantially less than or equal to 10 torr, even if the wide region 42 and the dense region 44 have different source/drain regions, respectively. The distribution density of 54/56, that is, the wide area 42 and the dense area 44 have different source/drain regions 54/56, respectively, and the bottom thickness t3/t5 of each first epitaxial layer 26 is still The thickness of the side of the first epitaxial layer is substantially smaller than the thickness t4/t6 of the first epitaxial layer 26 to overcome the problem that the thickness of the bottom of the first epitaxial layer in the widened region is smaller than the thickness of the side of the first epitaxial layer. The first epitaxial layer 26 of the present invention provides a better barrier effect that is unaffected by the micro-loading effect.

In summary, the present invention provides a selective epitaxial growth process with low operating pressure to form an epitaxial layer having a bottom thickness greater than the thickness of the side in the recess, and further performing the selective epitaxial growth process of the low operating pressure. Applying a plurality of regions having different pattern densities on a semiconductor substrate to simultaneously form an epitaxial layer having a structural feature having a bottom thickness substantially greater than or equal to the thickness of the sidewalls in the recess to avoid process variability caused by microloading effects For example, it is avoided to form an epitaxial layer having a bottom thickness substantially smaller than the thickness of the side in the groove of the wide area, which contributes to improving the reliability of the electrical performance of the semiconductor device.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Base

12. . . Groove

14. . . Gate structure

16. . . Shallow trench isolation

18. . . Gate dielectric layer

20. . . Gate conductive layer

twenty two. . . Cover

twenty four. . . First side wall

26. . . First epitaxial layer

28. . . Second epitaxial layer

29. . . Channel area

30. . . Source/drain-doped region

32. . . Transistor

34. . . Second side wall

36. . . Third epitaxial layer

38. . . Fin structure

42. . . Wide area

44. . . Dense area

46. . . Transistor

48. . . Transistor

50. . . Gate structure

52. . . Gate structure

54. . . Source/bungee area

56. . . Source/bungee area

H1. . . depth

T1, t3, t5. . . Bottom thickness

T2, t4, t6. . . Side thickness

1 to 6 are schematic views showing a method of fabricating an epitaxial layer according to a first preferred embodiment of the present invention.

7 to 9 are schematic views showing a method of fabricating an epitaxial layer according to a second preferred embodiment of the present invention.

Figure 10 is a schematic view of a semiconductor device in accordance with a preferred embodiment of the present invention.

10. . . Base

16. . . Shallow trench isolation

18. . . Gate dielectric layer

20. . . Gate conductive layer

twenty two. . . Cover

twenty four. . . First side wall

26. . . First epitaxial layer

28. . . Second epitaxial layer

29. . . Channel area

30. . . Source/drain-doped region

36. . . Third epitaxial layer

Claims (29)

A method of fabricating an epitaxial layer, comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes at least one recess; and performing a first selective epitaxial growth (SEG) process to form in the recess A first epitaxial layer, wherein the first selective epitaxial growth process comprises an operating pressure, and the operating pressure is substantially less than or equal to 10 torr. The method of fabricating an epitaxial layer according to claim 1, wherein the first epitaxial layer comprises a bottom thickness and a side edge thickness. The method of fabricating an epitaxial layer according to claim 2, wherein the bottom thickness of the first epitaxial layer is substantially smaller than a depth of the recess. The method of fabricating an epitaxial layer according to claim 2, wherein the bottom thickness is substantially greater than or equal to the thickness of the side, and the ratio of the thickness of the bottom to the thickness of the side is substantially greater than or equal to one. The method of producing an epitaxial layer according to claim 4, wherein the ratio of the thickness of the bottom portion to the thickness of the side portion is substantially greater than or equal to 1.4. The method for producing an epitaxial layer according to claim 1, wherein when the first selective epitaxial growth process is performed, a gas including dichlorosilane (DCS), decane (GeH ₄ ), and hydrogen chloride is introduced. (HCl) and the like. The method of producing an epitaxial layer according to claim 6, wherein a concentration ratio of one of the dichlorosilanes is substantially smaller than a concentration ratio of the decane. The method of producing an epitaxial layer according to claim 7, wherein a concentration ratio of the hydrogen chloride is substantially between the concentration ratio of the dichlorosilane and the concentration ratio of the decane. The method for fabricating an epitaxial layer according to claim 1, further comprising performing a second selective epitaxial growth process to form a second epitaxial layer on the first epitaxial layer. The method for producing an epitaxial layer according to claim 9, wherein the first epitaxial layer and the second epitaxial layer respectively comprise a first material and a lattice constant having a lattice constant different from a lattice constant of the semiconductor substrate Second material. The method of producing an epitaxial layer according to claim 10, wherein the first material and the second material both comprise ruthenium. The method of producing an epitaxial layer according to claim 11, wherein the first concentration of the first material is substantially less than the concentration of the second one of the second material. The method for fabricating an epitaxial layer according to claim 10, further comprising performing a third selective epitaxial growth process to form a third epitaxial layer on the second epitaxial layer. The method of producing an epitaxial layer according to claim 13, wherein the material of the third epitaxial layer comprises germanium. A semiconductor device comprising: a semiconductor substrate comprising at least one iso region and at least one dense region; and a plurality of transistors respectively disposed in the wide region and the dense region, and each The transistor includes at least one source/drain region, wherein each of the source/drain regions includes a first epitaxial layer having a bottom thickness and a side thickness, and each of the bottom thicknesses is substantially greater than Or equal to the corresponding thickness of each side. The semiconductor device of claim 15 wherein the ratio of each of the bottom thickness to the thickness of each of the sides is substantially greater than or equal to 1.4. The semiconductor device of claim 15, wherein the source/drain regions further comprise a second epitaxial layer disposed on the first epitaxial layer. The semiconductor device of claim 17, wherein the first epitaxial layer and the second epitaxial layer respectively comprise a first material and a second material having a lattice constant different from a lattice constant of the semiconductor substrate. The semiconductor device of claim 18, wherein the first material and the second material both comprise germanium. The semiconductor device of claim 19, wherein the first concentration of the first material is substantially less than the second concentration of the second material. The semiconductor device of claim 17, further comprising a third epitaxial layer disposed on the second epitaxial layer. The semiconductor device of claim 21, wherein the material of the third epitaxial layer comprises germanium. The semiconductor device of claim 15, wherein each of the transistors further comprises at least one gate structure, and the source/drain regions are respectively disposed in the semiconductor substrate on both sides of the gate structure. A method of fabricating an epitaxial layer, comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes at least one recess; and performing a first selective epitaxial growth (SEG) process to form in the recess a first epitaxial layer, wherein the first selective epitaxial growth process comprises introducing a gas comprising Dichlorosilane (DCS), decane (GeH ₄ ), hydrogen chloride (HCl), etc. Gases such as chlorodecane, decane, and hydrogen chloride have a concentration ratio (0.5-2.1): (1.5-3.3): 1. The method of fabricating an epitaxial layer of claim 24, wherein the first selective epitaxial growth process comprises an operating pressure and the operating pressure is substantially less than or equal to 10 torr. The method of fabricating an epitaxial layer according to claim 24, wherein the first epitaxial layer comprises a first material, and the first material comprises germanium. The method of producing an epitaxial layer according to claim 26, wherein the first epitaxial layer has a first germanium concentration system of between 20% and 30%. The method of fabricating an epitaxial layer according to claim 24, wherein a bottom thickness of the first epitaxial layer is substantially greater than or equal to a side thickness of the first epitaxial layer, and the bottom thickness and the side The ratio of edge thicknesses is substantially greater than or equal to one. The method of making an epitaxial layer of claim 28, wherein the ratio of the thickness of the bottom to the thickness of the side is substantially greater than or equal to 1.4.