CN108231778B - Semiconductor element and manufacturing method thereof - Google Patents
Semiconductor element and manufacturing method thereof Download PDFInfo
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- CN108231778B CN108231778B CN201611128637.4A CN201611128637A CN108231778B CN 108231778 B CN108231778 B CN 108231778B CN 201611128637 A CN201611128637 A CN 201611128637A CN 108231778 B CN108231778 B CN 108231778B
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- layer
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- gate structure
- semiconductor device
- cap layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000003860 storage Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 28
- 125000006850 spacer group Chemical group 0.000 claims abstract description 21
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 4
- 229910052757 nitrogen Inorganic materials 0.000 claims 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 2
- 238000011065 in-situ storage Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- -1 silicon carbide nitride Chemical class 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- Semiconductor Memories (AREA)
Abstract
The invention discloses a method for manufacturing a semiconductor element. Firstly, providing a substrate, wherein the substrate is provided with a storage area and a logic area, then forming a stacking structure in the storage area and a grid structure in the logic area, forming a first covering layer on the stacking structure and the grid structure, carrying out an oxidation in-situ manufacturing process to form an oxide layer on the surface of the first covering layer, and forming a second covering layer on the oxide layer. And removing part of the second cover layer, part of the oxide layer and part of the first cover layer in the logic region to form a spacer on the sidewall of the gate structure.
Description
Technical Field
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming an oxide layer on a cap layer of a memory region by an oxidation process.
Background
With the trend toward miniaturization of various electronic products, the design of Dynamic Random Access Memory (DRAM) cells must meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, it has gradually replaced a DRAM cell with a planar gate structure due to its longer carrier channel length within the same semiconductor substrate to reduce the leakage of the capacitor structure.
Generally, a DRAM cell with a recessed gate structure includes a transistor element and a charge storage device to receive voltage signals from bit lines and word lines. However, due to the limitations of the fabrication process, the conventional DRAM cell with recessed gate structure still has many drawbacks, and further improvements and improvements are needed to effectively improve the performance and reliability of the related memory device.
Disclosure of Invention
The preferred embodiment of the invention discloses a method for manufacturing a semiconductor element. Firstly, providing a substrate, wherein the substrate is provided with a storage area and a logic area, then forming a stacking structure in the storage area and a grid structure in the logic area, forming a first covering layer on the stacking structure and the grid structure, carrying out an oxidation in-situ manufacturing process to form an oxide layer on the surface of the first covering layer, and forming a second covering layer on the oxide layer. And removing part of the second cover layer, part of the oxide layer and part of the first cover layer in the logic region to form a spacer on the sidewall of the gate structure.
Another embodiment of the present invention discloses a semiconductor device, comprising: a substrate, which is provided with a storage area and a logic area; a gate structure disposed on the substrate of the logic region; and a first spacer disposed on the sidewall of the gate structure. The first spacer further includes a first cap layer, an oxide layer disposed on the first cap layer, and a second cap layer disposed on the oxide layer.
Drawings
Fig. 1 to 5 are schematic diagrams illustrating a method for fabricating a semiconductor device according to a preferred embodiment of the invention.
Description of the main elements
12 substrate 14 storage area (memory area)
16 logic region 18 gate structure
20 shallow trench isolation 22 silicon oxide layer
24 silicon nitride layer 26 silicon oxide layer
28 stack structure 30 gate structure
32 amorphous silicon layer 34 titanium metal layer
36 titanium nitride metal layer 38 tungsten silicide layer
40 tungsten metal layer 42 silicon nitride layer
44 silicon oxide layer 46 first cap layer
48 oxide layer 50 second cap layer
52 patterning photoresist 54 first spacers
56 third cap layer 58 patterned photoresist
60 second spacer
Detailed Description
Referring to fig. 1 to 5, fig. 1 to 5 are schematic diagrams illustrating a method for fabricating a semiconductor device according to a preferred embodiment of the invention. As shown in fig. 1, a substrate 12, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, is provided. The substrate 12 preferably defines at least a memory region 14 and a logic region 16, wherein the memory region 14 may be used for fabricating Dynamic Random Access Memory (DRAM) devices with recessed gates, and the logic region 16 may be used for fabricating active devices such as mos transistors.
In the present embodiment, a plurality of buried gate structures 18 may be disposed in the substrate 12 of the memory region 14, at least one Shallow Trench Isolation (STI) 20 may be disposed between the memory region 14 and the logic region 16 for isolating devices disposed in the memory region 14 and the logic region 16, and the STI 20 and the insulating material covering the surface of the substrate 12 of the memory region 14 may include a silicon oxide layer 22, a silicon nitride layer 24 and a silicon oxide layer 26 in detail.
A stacked structure 28 is then formed on the storage region 14 and at least one gate structure 30 is formed on the logic region 16, wherein the stacked structure 28 is preferably disposed on the substrate 12 of the storage region 14 and covers the plurality of embedded gate structures 18 embedded in the substrate 12, and the gate structure 30 of the logic region 16 is directly disposed on the surface of the substrate 12. In the present embodiment, the stacked structure 28 and the gate structure 30 are formed by first globally stacking a plurality of material layers (not shown) on the substrate 12 of the storage region 14 and the logic region 16, wherein the combination of the material layers may include an amorphous silicon layer 32, a titanium metal layer 34, a titanium nitride metal layer 36, a tungsten silicide layer 38, a tungsten metal layer 40, a silicon nitride layer 42, and a silicon oxide layer 44. A pattern transfer process is then performed, such as by removing portions of the material layer using a patterned photoresist (not shown) as a mask, to form a stacked structure 28 and a gate structure 30 formed by the patterned material layer in the memory region 14 and the logic region 16, respectively.
Then, a first cap layer 46 is formed on the stacked structure 28 and the gate structure 30 while covering the shallow trench isolation 20, and an oxidation process is performed to oxidize a portion of the first cap layer 46 to form an oxide layer 48 on the surface of the first cap layer 46. In the present embodiment, the first cap layer 46 preferably comprises silicon carbide nitride (SiCN), and the oxide layer 48 formed by the oxidation process comprises silicon oxycarbide nitride (SiCON).
As shown in fig. 2, a second cap layer 50 is formed on the oxide layer 48, a patterned mask, such as a patterned photoresist 52, is formed on the storage region 14, and a portion of the second cap layer 50, a portion of the oxide layer 48 and a portion of the first cap layer 46 in the logic region 16 are removed by using the patterned photoresist 52 as a mask to form a first spacer 54 on sidewalls of the gate structure 30. In the present embodiment, the first spacer 54 formed on the sidewall of the gate structure 30 preferably includes a first cap layer 46 having an L-shaped cross-section, an oxide layer 48 having an L-shaped cross-section, and a second cap layer 50 having an I-shaped or a I-shaped cross-section. In addition, the second cap layer 50 of the present embodiment preferably comprises silicon nitride, but is not limited thereto.
At least one ion implantation process may then be performed, and ions may be implanted into the substrate 12 on both sides of the first spacer 54 using the patterned photoresist 52 of the storage region 14 and the gate structure 30 and the first spacer 54 of the logic region 16 as masks to form a lightly doped drain, wherein the lightly doped drain may have N-type or P-type dopants depending on the type of transistor.
Next, as shown in fig. 3, the patterned photoresist 52 of the storage region 14 is removed, and a third cap layer 56 is formed on the stacked structure 28 and the gate structure 30, wherein the third cap layer 56 preferably comprises, but not limited to, silicon oxide. More specifically, the third cap layer 56 preferably covers the surface of the second cap layer 50 exposed by the storage region 14 and the surfaces of the gate structure 30 and the first spacer 54 in the logic region 16. Another patterned mask, such as a patterned photoresist 58, is then formed in the logic region 16 to expose the third cap layer 56 of the storage region 14.
As shown in fig. 4, an etching process is then performed using the patterned photoresist 58 as a mask, for example, a first etchant comprising diluted hydrofluoric acid may be used to remove the third cap layer 56 of the storage region 14 and expose the surface of the underlying second cap layer 50, and the remaining third cap layer 56 of the logic region 16 becomes a second spacer 60, and the second spacer 60 preferably covers the upper surface of the gate structure 30 and the sidewall of the first spacer 54.
As shown in fig. 5, another etching process is then performed using patterned photoresist 58 as a mask, for example, a second etchant consisting of hot phosphoric acid is used to remove second capping layer 50 of storage region 14, and then patterned photoresist 58 is removed. It should be noted that since the current second cap layer 50 of silicon nitride directly covers the surface of the first cap layer 46 of silicon carbonitride without the oxide layer 48 formed by the oxidation process, the etchant formed by hot phosphoric acid is likely to directly damage the underlying first cap layer 46 of silicon carbonitride when removing the second cap layer 50 or silicon nitride layer of the memory region 14. In view of the above, the present invention preferably utilizes the oxidation process to form the oxide layer 48 formed of silicon oxycarbonitride (SiCON) on the first cap layer surface 46 as a barrier layer (stop layer), so that the second cap layer 50 of the memory region 14 is removed by the second etchant formed of hot phosphoric acid and then directly stops on the oxide layer 48 without wearing down the underlying first cap layer 46.
Then, the fabrication process of the back-end memory and the mos transistor is performed according to the fabrication process requirements, for example, a plurality of dielectric layers (not shown) may be sequentially formed on the stacked structure 28 of the storage region 14 and the gate structure 30 of the logic region 16, and then contact plugs may be formed in the dielectric layers according to the product requirements to respectively connect the memory element of the storage region 14 and/or the mos transistor element of the logic region 16. Thus, a semiconductor device according to the preferred embodiment of the present invention is manufactured.
The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.
Claims (19)
1. A method of fabricating a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a storage area and a logic area;
forming a plurality of embedded gate structures in the storage region of the substrate;
forming a stacked structure in the storage region and a gate structure in the logic region, wherein the stacked structure and the gate structure comprise the same material stack;
forming a first capping layer on the stacked structure and the gate structure;
performing an oxidation process to form an oxide layer on the surface of the first covering layer;
forming a second cap layer on the oxide layer;
forming a first patterned mask on the storage region;
removing a portion of the second cap layer, a portion of the oxide layer and a portion of the first cap layer in the logic region by using the first patterned mask as a mask to form a first spacer on the sidewall of the gate structure;
forming a second patterned mask on the gate structure and covering the first spacer; and
and removing the second cover layer of the storage region by using the second patterned mask as a mask and the oxide layer as a barrier layer.
2. The method of claim 1, further comprising:
forming a third cap layer on the stacked structure and the gate structure;
forming a second patterned mask in the logic region; and
and removing the third cover layer and the second cover layer of the storage region by using the second patterned mask as a mask, wherein the third cover layer remained in the logic region is a second spacer.
3. The method of claim 2, further comprising removing the third cap layer of the storage region using a first etchant.
4. The method of claim 3, wherein the first etchant comprises dilute hydrofluoric acid.
5. The method of claim 2, further comprising removing the second cap layer of the storage region using a second etchant.
6. The method of claim 5, wherein the second etchant comprises hot phosphoric acid.
7. The method of claim 2, wherein the third capping layer comprises silicon oxide.
8. The method of claim 1, wherein the first capping layer comprises silicon carbide and nitrogen.
9. The method of claim 1, wherein the oxide layer comprises silicon oxycarbide.
10. The method of claim 1, wherein the second capping layer comprises silicon nitride.
11. A semiconductor device, comprising:
the semiconductor device comprises a substrate, a first substrate, a second substrate and a third substrate, wherein the substrate is provided with a storage area and a logic area, and the storage area of the substrate comprises a plurality of embedded gate structures;
a gate structure disposed on the substrate of the logic region;
a stack structure disposed on the substrate of the storage region, wherein the stack structure and the gate structure comprise a same material stack; and
the first covering layer is positioned on the side wall and the top surface of the stacked structure and the side wall of the grid structure;
an oxide layer on the first cap layer; and
and a second cap layer on the oxide layer on the sidewall of the gate structure, wherein the first cap layer, the oxide layer and a portion of the second cap layer on the sidewall of the gate structure form a first spacer, and the oxide layer has a barrier effect against an etchant of the second cap layer.
12. The semiconductor device as defined in claim 11, wherein the first cap layer is L-shaped.
13. The semiconductor device as defined in claim 11, wherein the oxide layer is L-shaped.
14. The semiconductor device as defined in claim 11, wherein the second cap layer is a substantially straight-line shape.
15. The semiconductor device of claim 11, wherein said first capping layer comprises silicon carbide and nitrogen.
16. The semiconductor device of claim 11, wherein said oxide layer comprises silicon oxycarbide.
17. The semiconductor device of claim 11, wherein said second capping layer comprises silicon nitride.
18. The semiconductor device as defined in claim 11, further comprising a second spacer disposed beside the first spacer and directly above the gate structure.
19. The semiconductor device of claim 18, wherein said second spacer comprises silicon oxide.
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| CN201611128637.4A CN108231778B (en) | 2016-12-09 | 2016-12-09 | Semiconductor element and manufacturing method thereof |
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| CN201611128637.4A CN108231778B (en) | 2016-12-09 | 2016-12-09 | Semiconductor element and manufacturing method thereof |
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| CN108231778B true CN108231778B (en) | 2022-07-12 |
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