CN100470800C - 用于电设备的esd保护装置 - Google Patents

用于电设备的esd保护装置 Download PDF

Info

Publication number
CN100470800C
CN100470800C CNB2005101373560A CN200510137356A CN100470800C CN 100470800 C CN100470800 C CN 100470800C CN B2005101373560 A CNB2005101373560 A CN B2005101373560A CN 200510137356 A CN200510137356 A CN 200510137356A CN 100470800 C CN100470800 C CN 100470800C
Authority
CN
China
Prior art keywords
esd protection
cavity
reference electrode
protection device
closing line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005101373560A
Other languages
English (en)
Other versions
CN1828893A (zh
Inventor
M·库茨门卡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN1828893A publication Critical patent/CN1828893A/zh
Application granted granted Critical
Publication of CN100470800C publication Critical patent/CN100470800C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0101Neon [Ne]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01054Xenon [Xe]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

一种用于电设备的ESD保护装置,该电设备包括具有内部端子的电路结构,该内部端子通过接合线来连接到电设备的外部端子,该ESD保护装置具有:填充气体的空腔,接合线设置在该空腔中;以及在空腔中的参考电极,其中该接合线的接合线端位于空腔中,以使得该接合线端与该参考电极之间的距离小于该接合线的其余部分与该参考电极之间的距离,从而当施加一个超过预定阈值的电位给外部端子时,从接合线端到参考电极发生气体放电。

Description

用于电设备的ESD保护装置
技术领域
本发明涉及一种用于电设备的ESD保护设备。
背景技术
在微电子中,越来越多的小宽度的集成电路被利用。这些小宽度结构使集成电路得到更高的时钟频率,进而在集成电路引脚处得到更高的信号的数据率。为了使得两个电设备之间进行可以抗干扰的通信,需要使传输比特的上升和下降沿尽可能地陡峭。因此,需要保持集成电路的输入和输出端的电容性负载尽可能地低。这些电容使电流曲线平滑,并且电压流过集成电路的输入和输出端。
现代集成电路中的信号的集成主要取决于输入和输出阶段的输入电容量。因此,这些现代集成电路以几千兆赫的范围内的比特速率运行。信号的输入信号转换速度和ISI以及符号间干扰分别大大地受到输入和输出级的输入电容的影响。
输入和输出端的电容量组成了片外驱动元件(off-chip driver element)的电容、芯片的输入电容、管壳电容以及ESD保护结构的电容(ESD=静电释放)。ESD结构的电容的比例上升到输入和输出级的整个电容的30%,甚至上升到仅输入引脚的输入级的70%。
集成电路必须存在于一种高达人体或者组装设备的1000V或者超过100pF电容量的连接。用于这种保护的二极管或者其它种类的保护设备必须相对较大。
为了允许存储数据、或者命令地址总线、或者其它芯片对芯片或者板对板数据传输系统的比特速率增加,用于保护过电压的二极管的电容量应当保持尽可能的低。这通常通过减少二极管的区域来完成,其中二极管用作ESD保护结构。
在芯片上的ESD保护结构和它的电容座从而增加了数据总线上信号的数据速率,其中总线连接到引脚并且分别连接到芯片的各个引脚。
图3说明了一种示例性BGA(BGA=球栅阵列)组件的截面结构。芯片11、封装基板21、迹线31、焊球41、接合线51以及芯片衬垫61被示出。
芯片11沉积在封装基板21上。迹线31沉积在相对于芯片11的封装基板21的表面上,在其上焊球41再次沉积。通过接合线51电连接到迹线31的芯片衬垫61连接到芯片11。
根据图3所示的结构,在焊球41和芯片衬垫61之间建立了导电连接。因此,焊球41导电连接到迹线31,其中迹线31通过结合线51再次导电连接到芯片衬垫61。通过图3所示的结构,来自电路板(这里未示出)并且由电路板传输给焊球41的电信号从那里传输到芯片衬垫61。因此,在芯片衬垫61和焊球41之间的连接是信号路径的一部分,例如,在芯片11和邻近芯片(这里未示出)之间的信号通路。
通常,一个ESD保护二极管或者多个ESD保护二极管连接到芯片I/O衬垫61和例如GND和VDD的内部芯片电源线之间,从而保护芯片11不会电过载。这里未示出的ESD保护二极管的电容使得提供给芯片衬垫61的二进制信号较短的上升/下降沿更好的平缓。平缓越大,ESD保护二极管的电容就越大。这对于任何种类的高频模拟信号同样适用。一些电容像用于信号的高频谐波的低通滤波器那样工作。因此,ESD保护二极管的电容增加了芯片衬垫61处的信号的数据速率。
发明内容
本发明的目的是提供一种用于具有低电容的电设备的ESD保护装置,以及一种使用本发明的ESD保护装置的电设备。
根据第一方面,本发明提供一种用于电设备的ESD保护装置,该电设备包括具有内部端子的电路结构,该内部端子通过接合线来连接到电设备的外部端子,该ESD保护装置具有:填充气体的空腔,接合线设置在该空腔中;以及在空腔中的参考电极,其中,该接合线的接合线端位于空腔中,以使得该接合线端与该参考电极之间的距离小于该接合线的其余部分与该参考电极之间的距离,从而当超出预定阈值的电位被提供给外部端子时,从接合线端到参考电极发生气体放电。
根据第二方面,本发明提供一种电设备,该电设备包括:具有内部端子的电路结构,该内部端子通过接合线来连接到电设备的外部端子;ESD保护装置;以及连接到该电路结构的ESD保护二极管,其中ESD保护装置包括:填充气体的空腔,其中接合线设置在该空腔中;以及空腔中的参考电极,其中,该接合线的接合线端位于空腔中,以使得该接合线端与该参考电极之间的距离小于该接合线的其余部分与该参考电极之间的距离,因此当超出预定阈值的电位被提供给外部端子时,从接合线端到参考电极发生气体放电。
本发明基于ESD结果电流的一部分可以通过放电气体排出的知识,因此通过ESD保护二极管的电流可以制作得更小。
根据本发明的一个实施例的一种ESD保护结构可以被设计为具有比仅ESD保护二极管更低的电容。这就允许分别减少提供给芯片衬垫的输入电容和输出电容,从而使更高频率的数据速率可以通过各个芯片衬垫被传输。
由上所述,根据本发明的一个实施例的ESD保护结构允许包含用于连接到ESD保护结构的芯片中过载电流的ESD保护二极管。这通过芯片区域的减少来实现。因此,芯片可以低成本的制造,在减少芯片区域的同时产量也在增加。
在根据本发明使用根据本发明的一个实施例的ESD保护装置的一种设备中,其中另一个ESD二极管连接到电路结构上的内部端子上,ESD保护二极管可以具有与现有技术相比明显减少的区域。从而,发生过电压的部分可以被截断并且在ESD保护装置处被限制,而仅有余下的较低部分被较小区域的ESD保护二极管容纳。因此,ESD保护二极管的区域的减小通过ESD保护二极管的电容的减少来实现。
附图说明
本发明的这些和其它目的将从以下结合附图的描述中变得更加清楚,其中:
图1是具有根据本发明的一个实施例的ESD保护结构的BGA封装结构;
图2是图1的A部分的增加说明;以及
图3是根据现有技术的BGA封装的结构的一部分。
具体实施方式
在以下的描述中,相同或者类似的元件具有相同的参考标记。
图1示出了具有根据本发明的一个实施例的ESD保护装置的BGA封装的结构。没有ESD保护装置的BGA封装的结构对应于参考图3所描述的结构,因此重复的说明被省略。
另外,在图1中,与图3比较,示出了接合线端51a,绝缘层66以及盖71。
这里,ESD保护装置由位于迹线31上的接合线端51a形成。这些接合线端在位于绝缘层66上的盖71的方向延伸。因此,稀有气体81填充在由芯片11、封装基板21、迹线31、绝缘层66和盖71形成的空腔中。
从而,空腔基本上是封闭的气体流,因此稀有气体81不会从那里泄漏。在芯片衬垫61和铜迹线31之间的接合线51延伸到填充有稀有气体81的空腔。因此,接合线51被制成为接合线端51a沿盖71的方向从迹线31延伸。这导致了在接合线51a的尖峰和盖71之间的空间相对于接合线51和盖71之间的空间要小。因此,接合线端51a与芯片衬垫61和焊球41导电连接。
绝缘层61使迹线31与金属盖71绝缘。例如通过这里未示出的接触通常连接到地或者电源电压的一个或者多个焊球的金属盖卡盘,金属盖71连接到地或者电源电压。如果通常比稀有气体81的激发电压(ignition voltage)高的高压信号被提供给焊球41,如在静电放电过程中发生的那样,则气体放电过程发生在接合线端51a的尖峰和盖71之间的稀有气体81的那部分中。因此,气体放电发生在高压下的接合线51a的尖峰和连接到地电位的金属盖71之间。这个气体放电过程伴随着通过焊球41和迹线31的高电流,并且限制芯片衬垫61上的电压。因此,保护芯片衬垫61防止电压过载。
由于ESD结果能量部分地耗散并且电压尖脉冲电平在气体放电过程中被限制,所以由于上面所示的ESD保护装置,芯片衬垫61受到电压和电流过载的低得多的电平的影响。可以减少经常在现有技术的电路结构中出现的ESD保护二极管或者其它的保护设备,像在芯片衬垫61上的可控硅元件的区域。这就导致了施加到芯片衬垫61的电容量的减小。
在根据这里所示的本发明的一个实施例中,ESD保护装置利用一些稀有气体在低压下在强电场中被电离的特性,稀有气体例如是氦、氖、氪和氙。如果接合线端51a的尖峰以针尖的形式制成,那么在针的尖峰附近的电场强度会变得很强,从而在几伏或者十几伏的电压范围内,会激发和触发气体放电。在激发放电之后,穿过放电部分的电压对于电流的关系曲线因此十分平滑。即使电流增加十倍,电压改变也大约仅为30%。这样的效果是,例如在氖灯中使用,作为稳压元件。
放电间隙在接合线端51a和金属盖71之间形成,其最好连接到芯片11的电源电压引脚或者地。因此,接合线端51a最好是尖的针形尖峰51b。这些针形尖峰可以由接合线51整体制成。
在针形尖峰51b和盖71之间的空间,针的形式和尖度,在盖下方的气体类型和压力被选择为,在几伏或者十几伏的范围内的电极之间的电压下分别触发和激发气体放电。
这样的结构明显不足够限制电压到不大于芯片的电源电压的值。用于现代高频芯片的电源电压通常不超过5伏。但是,允许减少关于芯片上ESD二极管的需求。因此,可以通过更小的芯片区域实现相同的ESD保护的功率。
在接合线之前的针51b的位置提供了一个另外的优点,就是在放电间隙之后,接合线51的电感限制电流。
接地的盖71的位置具有在印制电路板上的芯片和迹线之间的附加的EMC屏蔽的优点,其中芯片被焊接在印制电路板上。
由于针的尖峰的区域十分低,所以根据本发明的一个实施例的ESD保护装置产生的额外电容低到可以被忽略,并且与ESD保护装置相比十分低,其中仅保护二极管被用在芯片衬垫61上。因此,ESD保护装置的寄生电容的电极区域非常小。
在图2中,示出了具有根据图1所示的本发明的一个实施例的ESD保护装置的BGA封装的机构的A部分。与图1已知的元件不同的是,针的尖峰51b在这里被特别强调。
当将超过特定阈值的电位施加给焊球41时,稀有气体81的激发发生在针的尖端51b和金属盖71之间的区域中。这导致了穿过放电气体的高电流以及接合线51上的电压击穿,因此保护芯片衬垫61以免受过电压。通过针的尖端51b和针的尖端51b距金属盖71的空间,可以分别设置发生气体放电的阈值和激发电压。
在上述的实施例中,示出了根据本发明的一个实施例的具有ESD保护装置的BGA封装的结构。但是,可选的是,例如MQFP或者PQFP封装的其它组件,这些组件可以被由上述方法制成的ESD保护装置保护以免受过电压。可选的组件甚至是电设备的端子,该端子穿过填充稀有气体81的空腔延伸。对于一些受到高压EMI脉冲影响的线路接收机/发射机的芯片的应用,这种ESD保护方法可以通过单独外部设备或者以某种方式电连接到普通封装的和ESD保护的标准芯片的子封装部分来实现。
在上述的实施例中,空腔最好填充稀有气体81。但是,可选不同气体。在上述实施例中的芯片11也可以体现为任意电设备,这些电设备通过内部端子61连接到外部端子31。
接合线51也可以体现为任意的电迹线,例如位于封装基板21上的导电层。
在上述实施例中,盖71由金属材料制成。但是,替代物可以是导电的非金属材料的盖,例如高掺杂的半导体层或者位于盖71上的电极,在这种情况下,盖由绝缘材料制成,最好位于靠近针的尖峰51b。
在上述的实施例中,芯片11的保护通过根据本发明的一个实施例的ESD保护装置实现,其中位于芯片11上的ESD保护二极管连接到芯片衬垫61上。但是,可选的是,根据本发明的一个实施例的ESD保护装置也可以与外部连接到芯片衬垫61上的二极管一起实现。
虽然本发明已经被一些优选实施例描述,但是在本发明的范围内还具有其它的改变、置换和等价物。应当注意到,有许多执行本发明的方法和组合的可选的方式。因此,以下的附属权利要求可以被理解为包括落在本发明的实际精神和范围内的所有的改变、置换和等价物。
参考标记清单
11 芯片
21 封装基板
31 铜迹线
41 焊球
51a 接合线端
51b 针的尖峰
61 芯片衬垫
71 盖
81 稀有气体

Claims (8)

1、一种用于电设备的ESD保护装置,该电设备包括具有内部端子的电路结构,该内部端子通过接合线来连接到电设备的外部端子,该ESD保护装置包括:
填充气体的空腔,该接合线设置在该空腔中;以及
在空腔中的参考电极;
其中,该接合线的接合线端位于空腔中,以使得该接合线端与该参考电极之间的距离小于该接合线的其余部分与该参考电极之间的距离,从而当提供超出预定阈值的电位给外部端子时,从该接合线端到参考电极产生气体放电。
2、根据权利要求1的ESD保护装置,其中,空腔位于封装基板和盖之间,电路结构位于封装基板上,盖位于封装基板下方。
3、根据权利要求2的ESD保护装置,其中,外部端子位于封装基板上。
4、根据权利要求2或3的ESD保护装置,其中,参考电极位于盖上。
5、根据权利要求2或3的ESD保护装置,其中,盖由导电材料制成,从而盖形成参考电极。
6、根据权利要求1的ESD保护装置,其中,参考电极电连接到电路结构的接地端子或者电源电压端子。
7、根据权利要求1的ESD保护装置,其中,填充气体的空腔中的气体包括稀有气体。
8、一种电设备,包括:
具有内部端子的电路结构,该内部端子通过接合线来连接到电设备的外部端子;
ESD保护装置;以及
连接到电路结构的ESD保护二极管,
其中,该ESD保护装置包括:
填充气体的空腔,其中,接合线设置在该空腔中;以及
在空腔中的参考电极,
其中,该接合线的接合线端位于空腔中,以使得该接合线端与该参考电极之间的距离小于该接合线的其余部分与该参考电极之间的距离,从而当超出预定阈值的电位被提供给外部端子时,从该接合线端到参考电极产生气体放电。
CNB2005101373560A 2004-11-22 2005-11-22 用于电设备的esd保护装置 Expired - Fee Related CN100470800C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/994977 2004-11-22
US10/994,977 US7196406B2 (en) 2004-11-22 2004-11-22 ESD protection apparatus for an electrical device

Publications (2)

Publication Number Publication Date
CN1828893A CN1828893A (zh) 2006-09-06
CN100470800C true CN100470800C (zh) 2009-03-18

Family

ID=36371553

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005101373560A Expired - Fee Related CN100470800C (zh) 2004-11-22 2005-11-22 用于电设备的esd保护装置

Country Status (3)

Country Link
US (1) US7196406B2 (zh)
CN (1) CN100470800C (zh)
DE (1) DE102005053689A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7576414B2 (en) * 2007-11-02 2009-08-18 Stats Chippac, Ltd. Electrostatic discharge (ESD) protection structure
US8279572B2 (en) * 2008-06-23 2012-10-02 International Business Machines Corporation Structure for an on-chip high frequency electro-static discharge device
US7915158B2 (en) * 2008-06-23 2011-03-29 International Business Machines Corporation Method for forming an on-chip high frequency electro-static discharge device
US7768762B2 (en) * 2008-06-23 2010-08-03 International Business Machines Corporation Design structure for an on-chip high frequency electro-static discharge device
US7759243B2 (en) 2008-06-23 2010-07-20 International Business Machines Corporation Method for forming an on-chip high frequency electro-static discharge device
JP5590042B2 (ja) * 2009-11-02 2014-09-17 株式会社村田製作所 電子部品デバイスおよびパッケージ基板
CN102222662B (zh) * 2011-07-01 2013-11-06 中国科学院微电子研究所 一种利用尖端放电进行静电保护的封装结构
TWI517227B (zh) 2012-02-24 2016-01-11 Amazing Microelectronic Corp Planetary Discharge Microchannel Structure and Its Making Method
DE102015205700A1 (de) 2015-03-30 2016-10-06 Robert Bosch Gmbh Elektronisches Gerät
US10332871B2 (en) * 2016-03-18 2019-06-25 Intel IP Corporation Area-efficient and robust electrostatic discharge circuit

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package
US5405808A (en) * 1993-08-16 1995-04-11 Lsi Logic Corporation Fluid-filled and gas-filled semiconductor packages
US6248380B1 (en) * 1995-06-06 2001-06-19 Cryovac, Inc. Package having a dual-film lid comprising a gas-impermeable film and a delaminatable, gas-permeable film
US6962829B2 (en) * 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
US6117705A (en) * 1997-04-18 2000-09-12 Amkor Technology, Inc. Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate
US6670023B2 (en) * 1997-12-02 2003-12-30 Cryovac, Inc. Laminate for case-ready packaging including a gas-impermeable film capable of delaminating into a gas-permeable portion and a gas-impermeable portion, and a gas-permeable film bonded thereto
US6586266B1 (en) * 1999-03-01 2003-07-01 Megic Corporation High performance sub-system design and assembly
FR2796715B1 (fr) * 1999-07-19 2002-09-13 Giat Ind Sa Initiateur pyrotechnique et procede de montage d'un tel initiateur
US6606230B2 (en) * 2000-06-30 2003-08-12 Mitsubishi Materials Corporation Chip-type surge absorber and method for producing the same
US7067914B2 (en) * 2001-11-09 2006-06-27 International Business Machines Corporation Dual chip stack method for electro-static discharge protection of integrated circuits
US7073375B2 (en) * 2004-07-02 2006-07-11 Honeywell International Inc. Exhaust back pressure sensor using absolute micromachined pressure sense die

Also Published As

Publication number Publication date
DE102005053689A1 (de) 2006-06-01
CN1828893A (zh) 2006-09-06
US7196406B2 (en) 2007-03-27
US20060108637A1 (en) 2006-05-25

Similar Documents

Publication Publication Date Title
CN100470800C (zh) 用于电设备的esd保护装置
US7215531B2 (en) Wiring connection structure of laminated capacitor and decoupling capacitor, and wiring board
US5189638A (en) Portable semiconductor memory device
KR101695492B1 (ko) 전력 전자 시스템에서 간섭 방출을 감소시키기 위한 장치
EP2400607A1 (en) Ignition device for plasma jet ignition plug
Dimarino et al. A wire-bond-less 10 kV SiC MOSFET power module with reduced common-mode noise and electric field
US7019425B2 (en) Device for noise suppressing of small electric motors
CN105957712A (zh) 用于多电压的分裂式薄膜电容器
US4325097A (en) Four terminal pulse suppressor
US6753204B1 (en) Method for assembling integrated circuits with protection of the circuits against electrostatic discharge
US5245412A (en) Low capacitance silicon transient suppressor with monolithic structure
CN113257801A (zh) 半导体装置及半导体装置的制造方法
KR200230702Y1 (ko) 접지 임피던스 및 접지저항 감소형 접지장치
US20060126254A1 (en) Protection of an integrated capacitor
US20170125380A1 (en) Inter-chip connection for noise mitigation
KR100793148B1 (ko) 차동구조로 된 고주파 회로의 정전기 방지회로
US9078354B2 (en) Techniques for attenuating resonance induced impedance in integrated circuits
US7221549B2 (en) Circuitry for protecting electronic circuits against electrostatic discharges and methods of operating the same
KR100457030B1 (ko) 배선기판및그것을사용한전력변환장치
US11689170B2 (en) Transient noise reduction filtering system
JP2002198466A (ja) 半導体装置
CN201490189U (zh) 具有静电防护功能的芯片结构
JP2009088396A (ja) 配線基板
US20060108690A1 (en) Circuit board with reduced simultaneous switching noise
US6407336B1 (en) Device for carrying high currents at a low inductance, in particular for a power converter or the like

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
C56 Change in the name or address of the patentee
CP01 Change in the name or title of a patent holder

Address after: Munich, Germany

Patentee after: Infineon Technologies AG

Address before: Munich, Germany

Patentee before: INFINEON TECHNOLOGIES AG

TR01 Transfer of patent right

Effective date of registration: 20120920

Address after: Munich, Germany

Patentee after: QIMONDA AG

Address before: Munich, Germany

Patentee before: Infineon Technologies AG

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20151228

Address after: German Berg, Laura Ibiza

Patentee after: Infineon Technologies AG

Address before: Munich, Germany

Patentee before: QIMONDA AG

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090318

Termination date: 20151122

EXPY Termination of patent right or utility model