CN100470791C - 具有堆叠的半导体元件的半导体装置及其制造方法 - Google Patents

具有堆叠的半导体元件的半导体装置及其制造方法 Download PDF

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CN100470791C
CN100470791C CNB2005100959832A CN200510095983A CN100470791C CN 100470791 C CN100470791 C CN 100470791C CN B2005100959832 A CNB2005100959832 A CN B2005100959832A CN 200510095983 A CN200510095983 A CN 200510095983A CN 100470791 C CN100470791 C CN 100470791C
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rewiring
contact
semiconductor element
contact area
substrate
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CN1744312A (zh
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哈里·黑德勒
罗兰·伊尔希格勒
托尓斯藤·迈耶
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Infineon Technologies AG
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Abstract

本发明提供了一种具有堆叠的半导体元件的半导体装置。两个半导体元件(21，26)被布置，以使得它们的接触区域(28，22)彼此相对。接触连接装置(29)在两个接触区域(28，22)之间形成了短的电连接。接触区域(28，22)与装置的外部接触区域(36)通过重新布线(23)连接。

Description

具有堆叠的半导体元件的半导体装置及其制造方法
技术领域
本发明涉及一种具有堆叠的半导体元件的半导体装置。本发明还涉及根据本发明的这种半导体装置的制造方法。
背景技术
尽管本发明是参考存储元件描述的，本发明并不局限于此。
例如，存储元件通过总线系统互相连接。所提供的布线通路尤其是信号线，应该尽可能短。提供了一种用于堆叠存储元件的技术。触点之间的布线的长度以这种方式保持短的距离，所述触点中的一个位于另一个之上。图11图示了带有壳体的半导体元件5的一种已知的布置。两个带有壳体的半导体元件中的一个被放置在另一个的顶部上，并通过外部布线3与另一个电连接。图12图示了用于堆叠的另外一种布置。这个例子里，两个未封装的半导体元件2一个叠在另一个的顶部被放置在壳体(housing)内，并利用各自的内部布线1与壳体的外部布线3电连接。图13图示了另外一种变型。这个例子里，两个半导体元件2被集合在装置8中的中间层6的周围，各个单独的半导体元件又通过内部布线1连接到壳体的外部布线3上。图14图示了第四种变型，其与前面的布置的区别在于：两个半导体元件12被堆叠在壳体里面，内部线连接1和插入(interposer)衬底形成连接到外部供电线的连接，在这个例子中，外部供电线采用焊球的形式。
不利地，在所提出的所有四种已知的半导体装置中，互相连接的各个半导体元件的接触区域10之间的布线的阻抗不匹配。尤其是，没有装置(provision)用于匹配具有1mm量级的典型长度的结合(bonding)线的阻抗。使用这些结合线，具有大于1GHz的频率范围的信号元件的未来存储代不能被应用。
对于在信号线中具有分支的总线系统，产生了另一个问题。在这种情况下，没有附加的电容和电感，不能够容易地匹配所有布线部分的阻抗。因此总线系统总是具有阻抗匹配差的部分。
这导致了未来存储元件的性能被由于布线的原因引起的信号反射和干涉效应所限制的问题。
发明内容
本发明的一个目的是提供一种半导体装置，其能够堆叠半导体元件，同时，提供改进的布线。
本发明的实质在于：两个半导体元件被布置，以使它们的活动表面互相面对。这使得能够将各个半导体元件的接触区域彼此非常靠近地布置。这样，到达半导体触点的电线中的分支点(fork)位于紧靠半导体触点的位置附近。因此，分支点后的布线部分的长度(尚未匹配的长度)短得可以忽略不计。
根据本发明，传送信号的布线从接地表面离开一段距离被规定路线(route)，并通过电介质层与后者隔开。信号布线的横截面、信号布线和接地表面之间的距离以及电介质被选择，以使得对于半导体装置的典型频率实现最佳阻抗匹配。
根据本发明的装置的一个改进(development)，半导体元件被嵌入到灌注混合物或框架中。灌注混合物可包括聚合物。
根据本发明的装置的一个改进，接触连接装置具有焊料沉积物和/或导电粘接剂。
用于生产根据本发明的装置的方法通过将半导体元件嵌入到灌注混合物中并应用重新布线的事实来实现其目的，在接下来的步骤中，第二半导体元件被与第一半导体元件相对地布置，使得它们的接触区域互相相对，先前应用的重新布线位于该两个半导体元件之间。两个接触区域之间通过接触连接装置互相连接。
附图说明
下面将结合附图详细描述示例性实施例，在附图中：
图1-6图示了制造方法的一个实施例；
图7-8图示了制造方法的第二实施例，和阻抗匹配的半导体装置；
图9-10图示了制造方法的第三个实施例，和阻抗匹配的半导体装置；和
图11-14图示了根据现有技术的堆叠的半导体元件装置。
具体实施方式
在图1-6详细地图示了本发明的制造方法的一个实施例。没有详细地描述掩模和蚀刻技术，因为假设这些技术是完全已知的。
在第一步骤中(如图1所示)，第一半导体元件21被嵌入到灌注混合物或者框架20中。该灌注混合物典型地包括聚合物。第一半导体元件21具有接触区域22。该接触区域沿着半导体元件的活动(active)侧25上的中心线分布。该活动侧25没有被灌注混合物20覆盖。有利地，活动表面25与灌注混合物20的上表面24形成一个平面。在进一步的步骤中(如图2所示)，重新布线(rewiring)23叠加于第一半导体元件和灌注混合物。重新布线23与第一半导体元件21的接触连接区域22接触。在单行触点排列的情况下，重新布线23典型地沿着接触区域在左手侧和右手侧交替地实现。在接下来的步骤中(如图3所示)，粘结剂凸起27被叠加于第一半导体元件的局部区域，接触连接装置29被叠加于接触区域22中的各个触点上。接触连接装置29可以具有焊料沉积物和/或导电粘结剂。
随后，具有活动表面30的第二半导体元件26和其中的接触连接区域28被固定在粘结剂凸起27上。在这种情况下，第二半导体元件以这样一种方式确定方向，使得它的接触连接区域28与第一半导体元件的接触连接区域22互相相对。通过接触连接区域28与接触连接装置29的连接，第一半导体元件的接触连接区域22被电连接到第二半导体元件的接触连接区域28，通过固化或者重熔接触连接装置29，形成永久的连接。如果需要，例如，在这种情况下进行热处理，以使焊料液化。这导致了重新布线23连接到两个半导体元件21、26。这样，重新布线中用于两个半导体元件21和26的分支直接位于两个接触连接区域22和28之间。粗略地估计，还没有被匹配的信号传输通路必须比媒介中的信号的波长的1/10短，当接触区域彼此之间间距为100μm时，这导致了对于该实施例的200GHz的极限频率。这使得在两个通过接触连接装置连接的半导体元件之间非常快速的通讯成为可能。也保证了从该装置的外部触点到各个半导体元件之间的信号传输通路几乎具有相同的长度，这样使得信号的传播差最小化。
在接下来的步骤中(如图4所示)，第二半导体元件的承载衬底(carriersubstrate)可以是地。在这种情况下，获得50μm的厚度是可能的。这有利于获得小的半导体装置的结构高度。
为了实现半导体装置的机械稳定性，第二半导体元件被嵌入到衬底34中。该衬底可以对应于灌注混合物20。嵌入也使得填充两个半导体元件之间的空腔成为可能。重新布线边缘处的区域35没有被衬底34覆盖。这能够通过后面的衬底去除，或者通过事先叠加掩模，然后在衬底34叠加之后去除掩模而实现。有利地，没有被衬底34覆盖的区域35位于衬底20的边缘附近。这样，外部接触连接区域36相互之间隔开一段距离，所述距离使得在印刷线路板上能够实现简单的安装。图6示意了短的重新布线37，其接触连接位于衬底34的表面上的接触连接区域36，并被沉积到未被覆盖的重新布线23的区域上。为此，重新布线37被形成图案。
重新布线37可以使用薄膜和/或厚膜技术被沉积，例如，电镀和/或在等离子反应室中的沉积。
图7中，图示了本发明的第二实施例。在第一半导体元件21被嵌入到灌注混合物20中和重新布线23已经形成之后，沉积电介质层40。电介质层40被构造为：它不覆盖灌注混合物20区域中的重新布线23的外部区域。导电层41被沉积到电介质层上。然后导电层41形成等电势表面或者接地表面。在给定电介质40的电常数和半导体元件的典型频率的情况下，根据已知的技术或者电气力学知识，以最佳方式匹配阻抗的方式选择电介质层40的厚度和布线23的宽度。
在接下来的步骤中，如在第一示例性实施例中所述，第二半导体元件通过位于第二半导体元件上或者电介质层上的粘结剂凸起被固定。两个接触连接区域22和28被使用接触连接装置29依次电连接。然后，叠加衬底34以封装第二半导体元件。通常包含金属的导电层42被沉积到衬底34上，所述的层构成了等电势或者接地表面。电介质层43被沉积到导电的接地表面42上。在最后的步骤中，重新布线48被实现，所述的重新布线将重新布线23连接到位于电介质层43的最上层表面上的外部接触连接区域。第二重新布线48的阻抗通过第二接地表面42和位于其中的电介质层43被匹配。这个实施例的优点在于：阻抗匹配从外部接触连接36到紧靠接触连接区域22和28附近的重新布线23中的分支点基本上被保证。
图9和图10示意了本发明的第三个实施例。该实施例与第二实施例的区别在于：在第一步骤中，等电势或者接地表面45被叠加至第一嵌入半导体元件21。该接地表面45不接触接触连接区域22。电介质层40被沉积到接地表面45上。然后形成重新布线44。该重新布线接触连接至接触连接区域22。该重新布线的阻抗通过接地表面45和电介质层40被匹配。制造本发明的第三个实施例的接下来的步骤对应T第二实施例的步骤。
尽管参考优选的示例性实施例描述了本发明，本发明并不限于它们。尤其，为了把第二半导体元件固定到第一半导体元件上，各种技术是已知的。而且，用于重新布线的材料并不限制于金属，而是同样可以包括掺杂半导体材料。
附图标记说明：
1：内部布线
2：未封装的半导体元件
3：外部接触连接区域
4：壳体
5：半导体元件
6：承载衬底
7，8：具有堆叠的半导体元件的半导体装置
10： 2的接触区域
11：覆盖层
12：半导体元件
13：具有内部布线的插入体
14：间距
15：绝缘
16：外部触点
17：接触连接区域
20：第一衬底或灌注混合物
21：第一半导体元件
22：   21的第一接触区域
23，44：第一重新布线
24：  20的表面
25： 21的第一活动侧
26：第二半导体元件
27：粘接剂凸起
28：26的第二接触区域
29：接触连接装置
30：26的第二活动侧
31：26的第二非活动侧
33：空腔
34：第二衬底
35：接触连接开口
36：外部触点
37，48，49：第二重新布线
40，43：电介质层
41，42，45，50：地表面

Claims (6)

1.一种具有堆叠的半导体元件的半导体装置，其中，具有第一接触区域(22)的第一半导体元件(21)和具有第二接触区域(28)的第二半导体元件(26)被布置为使第一接触区域(22)和第二接触区域(28)互相相对，接触连接装置(29)电连接第一接触区域(22)和第二接触区域(28)，该接触连接装置(29)通过重新布线(23，37，48，49)电连接到外部接触连接区域(36)，提供平行于重新布线(23，37，48，49)延伸的至少一个接地表面(41，42，45，50)，电介质层(40，43)被引入重新布线(23，37，48，49)和接地表面(41，42，45，50)之间，以匹配重新布线的阻抗。
2.根据权利要求1中所述的半导体装置，其中，第一半导体元件(21)和第二半导体元件(26)被嵌入衬底(20，34)中，所述衬底为灌注混合物或者框架。
3.根据权利要求2中所述的半导体装置，其中，衬底(20，34)包含聚合物。
4.根据权利要求1中所述的半导体装置，其中，接触连接装置(29)具有导电的粘结剂和/或焊料沉积物。
5.用于制造权利要求1中所述半导体装置的方法，所述的方法具有步骤：
a)提供第一半导体元件(21)；
b)在第一衬底(20)中嵌入第一半导体元件(21)，第一半导体元件的第一接触区域(22)没有被覆盖，其中所述第一衬底(20)为灌注混合物；
c)将接触连接装置(29)叠加于第一接触区域(22)；
d)形成第一重新布线(23，44)，以接触连接所述接触连接装置(29)，第一重新布线(23，44)延伸得与第一衬底(20)一样远；
e)布置具有第二接触区域(28)的第二半导体元件(26)，使得第二接触区域(28)面向第一接触区域(22)，并且，接触连接装置(29)将第二接触区域(28)电连接到第一接触区域(22)；
f)在第二衬底(34)中嵌入第二半导体元件；和
g)将外部触点(36)叠加到第二衬底(34)上，并形成第二重新布线(37，48，49)，以将外部触点(36)连接到第一重新布线(23，44)。
6.根据权利要求5中所述的制造方法，其中，在第一重新布线(23，44)和第二重新布线(37，48，49)形成之后或之前，用于形成接地表面(41，42，45，50)的导电层和电介质层(40，43)紧接着被沉积并形成图案，沉积的顺序被选择，使得电介质层(40，43)以使第一重新布线(23，44)和第二重新布线(37，48，49)的阻抗被匹配的方式布置在第一重新布线(23，44)和第二重新布线(37，48，49)和接地表面(41，42，45，50)之间。
7.根据权利要求6中所述的制造方法，其中，在第二半导体元件被叠加之后将第二半导体元件薄化，以降低装置的结构高度。
CNB2005100959832A 2004-08-30 2005-08-30 具有堆叠的半导体元件的半导体装置及其制造方法 Expired - Fee Related CN100470791C (zh)

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