CN100468776C - 具有介质应力产生区的晶体管及其制造方法 - Google Patents

具有介质应力产生区的晶体管及其制造方法 Download PDF

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CN100468776C
CN100468776C CNB2006101538017A CN200610153801A CN100468776C CN 100468776 C CN100468776 C CN 100468776C CN B2006101538017 A CNB2006101538017 A CN B2006101538017A CN 200610153801 A CN200610153801 A CN 200610153801A CN 100468776 C CN100468776 C CN 100468776C
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D·奇丹巴拉奥
B·J·格林
K·里姆
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

通过包括分离介质应力产生区的结构给PFET的沟道区施加压缩应力，所述介质应力产生区完全位于其中设置PFET的源极、漏极和沟道区的有源半导体区的底表面下面。具体地，所述介质应力产生区包括与所述有源半导体区的所述底表面完全接触的收缩氧化物区，以使它具有与所述底表面区共同延伸的区域。所述介质应力产生区边缘处的鸟嘴状氧化物区在所述介质应力产生区的边缘处施加向上的力，以给所述PFET的所述沟道区施加压缩应力。

Description

具有介质应力产生区的晶体管及其制造方法
技术领域
本发明涉及半导体器件和工艺。更具体地说，本发明涉及具有介质应力产生区的半导体器件及其制造方法。
背景技术
可以给某些类型的晶体管施加压缩应力或拉伸应力，以提升它们的性能。具体地，当给p型场效应晶体管(“PFET”)的沟道区施加纵向(在电流的方向上)压缩应力时，可以提升其性能。另一方面，当给n型场效应晶体管(“NFET”)的沟道区施加纵向拉伸应力时，可以提升其性能。
已经提出了多种用于给此晶体管施加压缩或拉伸应力的结构。在一些情况下，提出了在NFET或PFET附近提供一个或多个应力产生区，用于给晶体管施加有用应力。例如，共同转让的美国专利公开No.2004/0113174描述了一种在其中包括NFET或PFET的有源半导体区的外边缘处的隔离区中掩埋介质应力产生区的方法。在此情况下，合并了介质应力产生区和隔离区。尽管此方法能够起效，但是这些隔离-应力产生区需要一个设计点，此点可以同时满足对应力施加功能、隔离功能和制造它们所需工艺的潜在矛盾需求。
由此，根据公知的技术，用于给NFET或PFET施加应力的介质应力产生区限制于隔离区所处的位置。为了突破此限制，很清楚需要进一步改进的结构和工艺。
发明内容
根据本发明的一方面，通过包括完全位于设置PFET的源极、漏极和沟道区的有源半导体区的底表面下面的分离介质应力产生区的结构给PFET的沟道区施加压缩应力。具体地，所述介质应力产生区包括完全接触所述有源半导体区的所述底表面的收缩(collapsed)氧化物区，以使它具有与所述底表面区共同延伸的区域。所述介质应力产生区边缘处的鸟嘴状氧化物区在所述介质应力产生区的边缘处施加向上的力，以给所述PFET的所述沟道区施加压缩应力。
根据本发明的一个特殊方面，优选提供的芯片中，有源半导体区具有在半导体衬底的主表面处的顶表面和在所述主表面下第一深度处的底表面。提供了p型场效应晶体管(“PFET”)，所述PFET包括全部置于所述有源半导体区内的沟道区、源极区和漏极区。通过完全位于有源半导体区的底表面下面的分离介质应力产生区给PFET的沟道区施加压缩应力。具体地，所述介质应力产生区包括完全接触所述有源半导体区的所述底表面的收缩氧化物区，以使它具有与所述底表面区共同延伸的区域。
附图说明
图1为截面图，在纵向上示出了根据本发明的实施例的PFET。
图2为图1所示PFET的相应的上到下的平面图。
图3为图1所示PFET的相应的在横向上的截面图。
图4为截面图，示出了制造图1-3所示PFET的方法中的阶段。
图5为截面图，示出了制造图1-3所示PFET的方法中的后面的阶段。
图6和7为截面图，示出了制造图1-3所示PFET的方法中的更后面的阶段。
具体实施方式
根据在此描述的本发明的实施例，提供了一种芯片，即，一种半导体芯片，其中有源半导体区具有在半导体衬底主表面处的顶表面和在主表面下第一深度处的底表面。提供了一种p型场效应晶体管(“PFET”)，其包括全都置于有源半导体区内的沟道区、源极区和漏极区。通过完全位于有源半导体区底表面下面的分离介质应力产生区给PFET的沟道区施加压缩应力。具体地，介质应力产生区包括完全接触有源半导体区底表面的收缩氧化物区，以使它具有与底表面区共同延伸的区域。
图1为截面图，示出了根据本发明的实施例的PFET10。图2提供了PFFT10的相应的平面图，而图1的视图是沿图2的线1-1在纵向上获得的。图3提供了通过图2的线3-3的PFET10在横向上的另一截面图。如这些图所示，PFET具有源极区12、漏极区16和源极与漏极区之间的沟道区14。也可以分别在源极区和漏极区到达沟道区的地方提供可选延伸和/或晕圈区26、28。栅极导体36位于沟道区14上面，并通过栅极介质37与沟道区14隔开。栅极导体通常包括掺杂半导体、金属或金属的导电化合物。栅极介质优选包括氧化物和/或氮化物或氧化物和氮化物的组合。当半导体衬底基本上由硅组成时，优选栅极介质包括二氧化硅。在具体的实施例中，栅极介质包括任何或若干高介电常数的材料，例如铁电介质、钙钛矿材料、锆钛酸铅等。优选设置介质隔离物38与栅极导体36的侧壁39接触，此隔离物源自用于限定源极、漏极和沟道区位置的注入工艺。
源极、漏极和沟道区置于半导体衬底的有源半导体区18中。具体参考图1，有源半导体区18在半导体衬底15的主表面20处具有顶表面。底表面22置于顶表面下面由有源半导体区的厚度24限定的深度处。最好如图2中所看到的，有源半导体区18以沟槽隔离区30为界。
再参考图1，沟槽隔离区30优选为“浅沟槽隔离”(“STI”)型，此术语通常用于指通过在此淀积之前形成的沟槽中淀积介质材料提供的隔离区，此沟槽通常具有从半导体衬底的主表面多达约0.5微米的深度。不考虑深度，术语“浅沟槽隔离”区也可以指这样的介质结构，此结构具有足以将衬底的有源半导体区与设置在STI远侧上的衬底的一个或多个其它区隔离的深度。
STI区30具有在半导体衬底15的优选至少基本上垂直方向27上上升的侧壁。然而，作为选择，侧壁可以以与垂直方向成一定角度地上升。在PFET的纵向25上隔开的有源半导体区的边缘32、34由沟槽隔离区的侧壁的位置限定，所述纵向为晶体管的源极和漏极区之间的电流的方向。如图1所示，优选在沟槽隔离区的侧壁内，在有源半导体区的边缘32、34处提供介质隔离物35。隔离物优选包括硅的氧化物以外的介质材料。当沟槽隔离区30基本上由二氧化硅组成时，更加优选隔离物35基本上由硅的氮化物组成。
还如图1中所示，分离介质应力产生区40完全位于有源半导体区18的底表面22之下并与其接触。换句话说，有源半导体区的整个底表面优选与介质应力产生区40接触。结果，介质应力产生区40的顶表面42具有与有源半导体区的底表面22共同延伸的区域。介质应力产生区40包括“收缩氧化物”区，此区优选包括在有源半导体区中包括的半导体的氧化物。使用术语“收缩”是因为此区优选占据比最初形成此区的半导体材料的体积略小的体积。与有源半导体区类似，介质应力产生区40以STI区30的侧壁为界，侧壁限定在晶体管的纵向25上隔开的介质应力产生区的边缘44、46。另外，介质应力产生区40在其顶表面42和与衬底的体半导体区15接触的底表面45之间具有有限的厚度43。
优选隔离物35从半导体衬底的主表面20仅略微地延伸到介质应力产生区的顶表面42下面。在具体优选的实例中，有源半导体区从其底表面到主表面的厚度24优选在约50和200纳米(nm)之间，介质应力产生区40的厚度43优选在约50和500纳米(nm)之间，并更加优选在约50和200nm之间。
还如沿纵向的截面图(图1)中和沿横向的截面图(图3)中所示，鸟嘴状氧化物区50从STI区30的侧壁横向向内地在收缩氧化物应力产生区40下面向位于PFET沟道区14下面的应力产生区40的中心部分延伸。鸟嘴状氧化物区从介质应力产生区40的边缘向内延伸，它们从边缘44、46延伸越远就变得越薄，通常直到它们在介质应力产生区下面的位置到达末端。优选从介质应力产生区的边缘44延伸的鸟嘴状氧化物区的尖端不接触从相反边缘46延伸的鸟嘴状氧化物区的尖端。以此方式，鸟嘴状氧化物区在边缘44、46处具有有限的厚度，而且在超过尖端的有源半导体区下面不存在。然而，并非特别需求尖端不接触。
鸟嘴状氧化物区50产生的一个效果是收缩氧化物应力产生区40的底表面趋于在其边缘处相对于STI区较高，而底表面趋于在离边缘44、46更远的点上下陷地较低。具体地说，应力产生区40的在边缘44、46处的底表面在沿STI区侧壁的高于其中底表面45直接接触半导体衬底的体区15的区域中的底表面的点处到达STI区。由此，鸟嘴状氧化物50的效果是只会在其边缘44、46处支撑收缩氧化物区40的底表面。反过来，收缩氧化物区的顶表面42间接通过鸟嘴状区域支撑，在边缘32、34处在有源半导体区18上施加向上的力。
通过鸟嘴状氧化物区施加的向上的力在有源半导体区的边缘32、34处存在。然而此力在有源半导体区的中心处或充分远离边缘的其它位置处不存在。结果，边缘32、34处方向向上的力的净效果是会在边缘32、34处向上“弯曲”或包裹有源半导体区的顶表面。此微分的向上的弯曲给PFET的沟道区14施加压缩应力。
现在参考图4到图7，将描述制造FET10(图1-3)的方法。此方法利用与Choe等人的共同转让的美国专利公开No.2005/0067294中所述的工艺类似的工艺。在Choe等人的工艺中，注入和处理硅衬底区，以形成绝缘体上硅(“SOI”)衬底的掩埋氧化物层。通过p型掺杂剂(例如，Ga、Al、B和BF2)的离子注入和后面的阳极化形成多孔硅区。然后氧化多孔硅区，以形成掩埋氧化物层。
在本方法中，使用与Choe等人所述的方法类似的工艺，但不是用于形成SOI衬底的掩埋氧化物层。而是通过本方法，形成在沟槽隔离区30的侧壁之间延伸的分离的掩埋介质应力产生区40(图1)，而且其中上述鸟嘴状氧化物区50会产生将要施加给晶体管沟道区的压缩应力。
在此方法中，如图4中所示，构图例如光致抗蚀剂的掩模层200，并用p型掺杂剂注入位于衬底15的主表面207下面的掩埋区202以形成隐埋(pocket)p掺杂区。掺杂剂浓度可以在约1×1019cm-3到约5×1020cm-3或更高的范围内。然而，在任何情况下，获得的硼浓度必须明显高于，即，以一个或更高数量级地高于单晶硅中的正常(p-)p型掺杂剂浓度。掺杂剂优选主要由硼(B)或氟化硼(BF2)构成，但是镓(Ga)和铝(Al)可以代替使用。离子注入半导体衬底的深度确定介质应力产生区的厚度以及主表面207下面的它的深度。反过来，根据实施注入的能量选择注入的深度。当通过光刻构图掩模层实施此注入时，光刻工艺限定了注入区边缘203的位置，这些边缘203在远离注入区的水平取向上表面201的方向上延伸。
此后，剥离掩模层200，而且半导体衬底要经过阳极化工艺以将隐埋p掺杂区转化为掩埋多孔半导体区。隐埋区变为多孔半导体区是阳极化工艺的结果。
如下进行阳极化工艺。优选主要由硅构成并且具有掩埋p型注入隐埋区的半导体衬底215置于或优选浸没于包括氟化氢(HF)溶液以及铂电极的容器中。将半导体衬底215连接到电流源的正极端，而将铂电极连接到与连接到正极端的电流源电导通的电流源的负极端。电流源给半导体衬底和控制阳极化工艺的HF溶液提供了阳极化电流。在阳极化电流存在时，HF溶液很容易通过单晶硅半导体(硅)扩散进更高p型掺杂剂浓度的隐埋区。
在更高掺杂剂浓度的隐埋区中，HF溶液与高掺杂的p型硅反应，以形成如图5中所示的多孔硅隐埋区205。将如下面所述，在形成附加掩模层208之前实施此步骤。阳极化电流的范围从1mA/cm2到100mA/cm2，这取决于此工艺产生的多孔硅区205的孔隙度或密度。硅中硼或其它p型掺杂剂的浓度和阳极化电流的量都可用于控制孔隙度。也就是说，这些参数控制掩埋隐埋区的密度，例如通过硅的质量测量由其体积分离的各掩埋隐埋区中的剩余量。例如，低孔隙度区，即，具有相对高密度的区域，为具有大于初始硅衬底密度的约44％的密度的区域。另一方面，高孔隙度区，即，具有相对低密度的区域，为具有小于初始硅衬底密度的约44％的密度的区域。在此情况下，掩埋多孔硅区205需要具有高孔隙度，以使在后面的氧化后，它的体积将缩小而且它将变为如上所述(图1)的收缩氧化物应力产生区40。
阳极化之后，接着氢烘焙衬底，由此除去大多数留在硅中的注入的硼。有必要在此阶段从硅衬底中除去高浓度的硼，以避免此高浓度影响用于后面限定晶体管的不同掺杂区，即，沟道区、源极和漏极区、晕圈和/或延伸区的工艺。在范围从约800到约1000摄氏度(“℃”)的温度下进行氢烘焙范围从约30秒到30分钟的时间段。
阳极化和后烘焙工艺之后，多孔硅区保持在至少通常与之前的隐埋区共同延伸的位置上。多孔硅区是包括多个孔隙的区域。如用电子显微镜看到的，多孔硅区具有与海绵或泡沫材料类似的形貌，具有大量的通过剩下的硅材料的连接结构支撑在一起的孔隙。
接下来，如图5中所示，在衬底主表面207上淀积并构图例如衬垫氮化硅的构图的硬掩模材料的另一掩模层208以形成开口209。实施构图掩模的工艺以使半导体衬底215的区域通过与掩埋多孔半导体区205重叠的开口暴露。换句话说，向下延伸进入衬底215的硬掩模层208的边缘220与掩埋多孔半导体区205重叠，如位置222处所示。重叠这些边缘的重要性在于保证掩埋多孔半导体区在后面的工艺中被氧化。
如图6中所示，接着使用此掩模层208，优选通过例如反应离子蚀刻(“RIE”)的各向异性垂直蚀刻工艺构图衬底215。此蚀刻工艺的结果是形成向下延伸进入衬底的外周沟槽210。当沟槽210达到稍低于掩埋多孔半导体区205的顶表面242的深度时，中断此蚀刻工艺。此后，形成沿沟槽210的垂直侧壁延伸的介质隔离物35，这些隔离物包括例如氮化硅或其它氮化物的可以相对于二氧化硅(或其它氧化物)优先蚀刻的材料，反之亦然。
接着，一旦介质隔离物35就位，继续进行垂直蚀刻工艺，直到沟槽210的底部255到达掩埋多孔半导体区205的底表面245以下的深度。然后暴露的多孔硅区205要经过氧化工艺。氧化工艺优选为例如通常称作“热”或“局部”氧化，其中将可以为分子形式、原子形式或甚至为例如水蒸气的化合物形式的氧源提供给在沟槽内暴露的半导体材料。在升高的温度下在室中保持此条件，直到取得预期的氧化量。氧化在从掩埋多孔半导体区205的边缘244、246横向向内的方向248、249上进行。氧化工艺的结果是形成掩埋介质应力产生区40(图1和3)。另外，在此氧化工艺期间，在底表面245和掩埋多孔半导体区的边缘244、246之间的界面处形成鸟嘴状氧化物区50。在此氧化工艺期间，前面形成的介质隔离物35会阻止有源半导体区18的侧壁32、34被氧化。
再次参考图1，用例如硅的氧化物(例如，二氧化硅)的介质材料填充沟槽210，以形成STI区30。通过高密度等离子体(“HDP”)技术和/或其它化学气相淀积(“CVD”)技术包括低压CVD(“LPCVD”)、等离子体增强CVD(“PECVD”)等淀积介质填充物，它可以通过例如原硅酸四乙酯(“TEOS”)前体淀积。
此后，通过本领域内技术人员公知的工艺形成栅极导体36、介质隔离物38、和源极和漏极区12、16，包括可选延伸区和/或晕圈区26、28，完成PFET10(图1到3)。
在上述实施例的一个变化中，鸟嘴状氧化物区50不只是结构中包括的此鸟嘴状氧化物区。参考图1和3，在此变化中，与其中所示区域50类似的上鸟嘴状氧化物区(未示出)置于介质应力产生区的顶表面42和有源半导体区18的底表面22之间。这些第二(上)鸟嘴状氧化物区与第一鸟嘴状氧化物区50结合在一起在有源半导体区的边缘处给有源半导体区施加向上的力。
第二鸟嘴状氧化物区具有与第一鸟嘴状氧化物50类似的形状和范围。与第一鸟嘴状氧化物区50类似，第二鸟嘴状氧化物区从介质应力产生区40的边缘向内延伸，它们从边缘44、46延伸越远就变得越薄，通常直到在有源半导体区下面的位置处到达末端。优选从介质应力产生区的一个边缘44延伸的鸟嘴状氧化物区的尖端不接触从相反边缘46延伸的鸟嘴状氧化物区的尖端。以此方式，鸟嘴状氧化物区在边缘44、46处具有有限的厚度，而且在超过尖端的有源半导体区下面不存在。然而，并非特别需求尖端不接触。
为了制造同时具有第一和第二鸟嘴状氧化物区的PFET，上述工艺将以如下方式变化。参考图6，当蚀刻沟槽210时，在沟槽到达恰好在掩埋多孔硅区205的顶表面242之上的深度时停止蚀刻工艺。然后在沟槽的内侧壁上形成隔离物。在此情况下，与上述实施例不一样，这些隔离物没有覆盖边缘244、246(图7)和掩埋多孔硅区的顶表面242之间的交叉部分。然而，隔离物在更接近有源半导体区的顶表面的位置处覆盖有源半导体区的边缘。
此后，利用沿沟槽侧壁的隔离物，使用例如RIE的工艺实施垂直方向的蚀刻，直到沟槽到达它们的最终深度，即，优选在掩埋多孔硅区(图7)的底表面245下面。当实施氧化时，同时形成了下鸟嘴状氧化物区50，以及在此所述的上鸟嘴状氧化物区。与前面一样，在上鸟嘴状氧化物区的位置以上，隔离物保护在边缘32、34(图1)处的有源半导体区在氧化步骤期间不被氧化。
尽管根据本发明的某些优选实施例描述了本发明，但是本领域内的技术人员应该理解，可以在不脱离本发明的真实范围和精神的情况下对其进行许多修改和改进，这些修改和改进只受下面所附权利要求的限制。

Claims (20)

1.一种芯片，包括:
有源半导体区，具有在半导体衬底的主表面处的顶表面和在所述主表面下面的第一深度处的底表面；
p型场效应晶体管，具有全部置于所述有源半导体区内的沟道区、源极区和漏极区；以及
分离介质应力产生区，包括与所述有源半导体区的所述底表面完全接触的收缩氧化物区，所述收缩氧化物区的顶表面具有与所述底表面区共同延伸的区域，以给所述p型场效应晶体管的所述沟道区施加压缩应力。
2.根据权利要求1的芯片，还包括包围所述有源半导体区的沟槽隔离区。
3.根据权利要求2的芯片，还包括沿所述沟槽隔离区的壁加衬的第一介质材料的介质隔离物，所述介质隔离物具有与所述有源半导体区的边缘接触的第一边缘，并具有与所述沟槽隔离区内包括的第二介质材料接触的第二边缘。
4.根据权利要求2的芯片，其中所述沟槽隔离区具有与所述介质应力产生区接触的多个内壁。
5.根据权利要求4的芯片，其中所述多个内壁与所述介质应力产生区的多个边缘横向相邻。
6.根据权利要求5的芯片，还包括在所述多个边缘处在所述介质应力产生区的底表面下面延伸的鸟嘴状氧化物区。
7.根据权利要求6的芯片，其中所述鸟嘴状氧化物区在所述有源半导体区的所述多个边缘处给所述有源半导体区施加向上的力。
8.根据权利要求6的芯片，其中所述鸟嘴状氧化物区为第一鸟嘴状氧化物区，所述芯片还包括置于所述有源半导体区的底表面和所述介质应力产生区的顶表面之间的第二鸟嘴状氧化物区。
9.根据权利要求8的芯片，其中所述第一和第二鸟嘴状氧化物区在所述有源半导体区的所述多个边缘处给所述有源半导体区施加向上的力。
10.根据权利要求1的芯片，其中所述有源半导体区的所述底表面在所述沟道区长度方向上的纵向上具有第一边缘和与所述第一边缘相对的第二边缘，并在所述沟道区宽度方向上的横向上具有第三边缘和与所述第三边缘相对的第四边缘，其中所述介质应力产生区在所述有源半导体区的所述第一、第二、第三和第四边缘之间连续延伸。
11.根据权利要求1的芯片，其中所述介质应力产生区包括掩埋区，所述掩埋区包括半导体氧化物，所述半导体氧化物具有与所述有源半导体区中包括的半导体相同的成分。
12.根据权利要求1的芯片，其中通过光刻限定所述介质应力产生区的多个边缘。
13.根据权利要求1的芯片，其中所述收缩氧化物区包括阳极化的多孔硅区。
14.一种制造场效应晶体管器件的方法，包括以下步骤:
在衬底的有源半导体区的底表面下面形成分离多孔半导体区，所述底表面与所述多孔半导体区完全接触；
氧化所述多孔半导体区，以形成包括收缩氧化物区的介质应力产生区；
形成p型场效应晶体管，具有全部置于所述有源半导体区内的沟道区、源极区和漏极区，
其中所述介质应力产生区给所述p型场效应晶体管的所述沟道区施加压缩应力。
15.根据权利要求14的制造场效应晶体管器件的方法，其中所述形成所述多孔半导体区的步骤包括通过掩模中的开口在所述衬底的硅区内注入p型掺杂剂，在存在氟化氢时给所述衬底提供阳极化电流以形成多孔硅区，并在存在氢时烘焙所述衬底。
16.根据权利要求15的制造场效应晶体管器件的方法，其中在所述硅区暴露于所述衬底的主表面时实施所述注入所述掺杂剂的步骤，而且所述方法还包括在所述存在氟化氢时给所述衬底提供阳极化电流以形成所述多孔硅区的步骤之前，生长所述半导体的外延层以覆盖所述注入区，所述有源半导体区置于所述外延层中。
17.根据权利要求15的制造场效应晶体管器件的方法，其中在实施所述注入所述硅区的步骤时，所述半导体衬底的所述硅区位于所述有源半导体区的所述底表面下面。
18.根据权利要求17的制造场效应晶体管器件的方法，其中所述介质应力产生区的边界根据所述掩模中的所述开口由光刻确定。
19.根据权利要求14的制造场效应晶体管器件的方法，还包括在所述介质应力产生区的多个边缘处形成在所述介质应力产生区的底表面下面延伸的鸟嘴状氧化物区，所述鸟嘴状氧化物区在所述有源半导体区的所述多个边缘处给所述有源半导体区施加向上的力。
20.根据权利要求19的制造场效应晶体管器件的方法，其中所述鸟嘴状氧化物区为第一鸟嘴状氧化物区，所述方法还包括在所述多个边缘处形成在所述有源半导体区的底表面和所述介质应力产生区的顶表面之间的第二鸟嘴状氧化物区，所述第一和第二鸟嘴状氧化物区在所述有源半导体区的所述多个边缘处给所述有源半导体区施加向上的力。
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