CN100461302C

CN100461302C - Shift register and liquid crystal driver

Info

Publication number: CN100461302C
Application number: CNB2005101161815A
Authority: CN
Inventors: 岩崎千里
Original assignee: Alps Electric Co Ltd
Current assignee: European and southern European Refco Group Ltd
Priority date: 2004-10-28
Filing date: 2005-10-25
Publication date: 2009-02-11
Anticipated expiration: 2025-10-25
Also published as: KR20060052255A; JP2006127630A; TW200614128A; TWI308312B; KR100745111B1; CN1783346A

Abstract

To provide a shift register whose operating speed can be increased, and to provide a liquid crystal driver employing the shift register. The shift register includes a plurality of stages connected in cascade, each stage shifts input data by using a plurality of clocks with different phases, outputs a clock inputted to a drain of an output transistor when receiving the input data from the source of the output transistor as a phase shift clock so as to shift an output signal, phase shift clocks at the (n-2) and (n-1)th stages are inputted to an n-th stage, and a gate voltage of the output transistor is sequentially increased by the phase shift clocks of the (n-2) and (n-1)th stages.

Description

Shift register and liquid crystal driver

Technical field

The present invention relates to for example be arranged on the liquid crystal display drive circuit that provides the shift register (Shift Resister) of scanning drive signal in the liquid crystal indicators such as LCD and used this shift register.

Background technology

For example, active array type LCD at display device that is used for computing machine and televisor, be provided with signal of video signal line (alignment) and scanning drive signal line (line) rectangularly, be provided with the on-off elements such as thin film transistor (TFT) of the liquid crystal that drives each pixel at the intersection point of these lines.

And, provide and to scan these signal wires successively, make all on-off elements on the scanning drive signal line temporarily to be in the scanning drive signal of conducting state to many scanning drive signal lines, and provide signal of video signal to the signal of video signal line with the scanning drive signal line locking.

At this, what a plurality of scan signal lines were supplied with action successively is shift register.

As shown in Figure 5, constituted following active matrix circuit in the display part: matrix is provided with many lines and alignment, cross part at this line and alignment has disposed liquid crystal cell, and this liquid crystal cell comprises that control is to the on-off element (transistor) of liquid crystal applied voltages and controlled liquid crystal portion.

Gate drivers (shift register) applies predetermined voltage on time series makes line (sweep trace) be in the ON state, the driver of alignment and this timing apply predetermined voltage (being applied by signal wire) to source electrode synchronously, thus, the optical states of change liquid crystal drives liquid crystal indicator.

And, in order to drive liquid crystal cell, in Fig. 5, with film crystal pipe manufacturer gate drivers (for example, with reference to patent documentation 1).

At this moment, must make the gate drivers high speed motion that applies voltage to line, and need provide enough magnitudes of current to line.

Wherein, as shown in Figure 6, gate drivers is made of the shift register of the hop count with a plurality of SR (shift register) level.

And, each SR level becomes structure as shown in Figure 7, and as shown in Figure 6, this SR level is cascaded, each SR level applies voltage as driving pulse to alignment successively, has the function that applies the gate drivers of predetermined voltage as the grid to the thin film transistor (TFT) of liquid crystal cell.

Here, shift register is designed to: in the oscillogram of the expression drive waveforms of Fig. 8, apply grid voltage Vgs (gate source voltage) to the node P1 of Fig. 7, this grid voltage makes output transistor 16 fully become conducting state (the low-down state of conducting resistance) in the front and back of output driving pulse (phase shifted clock).

Patent documentation 1: Japanese kokai publication hei 08-87897 communique

As judging according to Fig. 7, at node P1, the bootstrapping effect that rises and to produce by the voltage of following the node 13 that causes by clock C1, become than the high voltage of input voltage (actual be value), can make the HIGH voltage of the output voltage of output OUTn rise to the HIGH voltage of clock C1 divided by transistorized threshold value.

But, in patent documentation 1 described shift register, driven object by gate drivers is object apparatus roughly determines the expectation that produces in output OUTn a HIGH voltage, therefore, the input voltage of shift register is fixed, even because bootstrapping effect and the booster voltage that in node P1, produces, also roughly by voltage decision as the output OUT of input voltage.

As mentioned above, as liquid crystal indicator high-accuracyization of development in recent years of one of object apparatus of gate drivers and the high speed of corresponding animation, the high speed motion of above-mentioned gate drivers becomes one of problem.

As also according to the judgement of Fig. 9, among this Fig. 9 with output transistor 16 (FET, field effect transistor) grid voltage Vgs, leakage current as parametric measurement output transistor 16, if can improve transistorized grid voltage, then current driving ability increases, and can make the action high speed of shift register.

But the structure of the shift register of patent documentation 1 can not realize making the booster voltage height of the grid voltage of output transistor than above-mentioned bootstrapping generation.

Summary of the invention

The present invention makes in light of this situation, and purpose is, a kind of liquid crystal driver that can increase the shift register of responsiveness and use this shift register is provided.

Shift register of the present invention has a plurality of levels of cascade, to import data according to the different a plurality of clocks of phase place is shifted, when these input data of input, the clock that is input to the drain electrode of output transistor is exported from source electrode as phase shifted clock, carry out the shift motion of output signal; To the phase shifted clock of n-2 section of the level input of n section and n-1 section, by the phase shifted clock of n-2 section and n-1 section, the grid voltage to above-mentioned output transistor boosts successively; In above-mentioned a plurality of levels, first capacitor and second capacitors in series are connected between the grid and source electrode of above-mentioned output transistor; Have first input circuit, make above-mentioned n-2 section phase shifted clock be input to the connecting portion of the above-mentioned grid and first capacitor; And second input circuit, make above-mentioned n-1 section phase shifted clock be input to the connecting portion of above-mentioned first and second capacitor; And, adjust the capacity ratio of above-mentioned first capacitor and second capacitor, control is input to ratio above-mentioned grid, boost in voltage.

Thus, shift register of the present invention, making the grid voltage of above-mentioned output transistor by phase shifted clock is the voltage of the multiple of clock, voltage by clock boosts it again, making gate source voltage is about 3 times of clock, therefore reduce the conducting resistance of output transistor thus significantly, can carry out turn-on action at high speed, can export clock voltage almost constant, the precipitous phase shifted clock in upper edge and lower edge.

Thus, shift register of the present invention with the phase shifted clock of n-2 section output, makes the charging of first capacitor; Use the phase shifted clock of n-1 section output then, make the charging of second capacitor and the current potential of the capacitor of winning is risen; Then the current potential of first capacitor is risen with clock; Therefore, the conducting resistance of output transistor is reduced significantly, and carry out turn-on action at high speed, can export the voltage of clock almost constant, upper edge, the precipitous phase shifted clock in lower edge.

Thus, shift register of the present invention can be adjusted the grid voltage of the grid that is input to output transistor, can avoid applying the unwanted grid voltage of action, can improve the reliability of output transistor.

Shift register of the present invention, above-mentioned first and second input circuits are diode.

Thus, shift register of the present invention can prevent to be stored in the discharge that the electric charge adverse current on first capacitor and second capacitor produces, up to finish with n-2 section, n-1 section phase shifted clock and clock a series of boost handle till, can make the voltage that on each capacitor, charges keep required voltage.

Liquid crystal display drive circuit of the present invention is characterized in that, the described shift register of above any one party case is applied in and is used to generate sweep trace and signal wire and intersects the scanning drive signal of the active matrix circuit that constitutes.

Thus, liquid crystal driver of the present invention uses, and can export the shift register of clock voltage phase shifted clock almost constant, that upper edge, lower edge are precipitous, therefore, can high-speed driving liquid crystal cell, the after image in the time of can preventing the view data variation or contrast decline.

The invention effect

As described above, according to shift register of the present invention, the conducting resistance of output transistor is reduced significantly, therefore can carry out turn-on action at high speed by increasing drive current, can export clock voltage almost constant, upper edge, the precipitous phase shifted clock in lower edge, therefore can access the effect of the responsiveness that can improve liquid crystal cell.

Description of drawings

Fig. 1 is the block diagram of structure example of the shift register of expression first and second embodiments of the present invention;

Fig. 2 is the concept map of the circuit structure example of the level 3 in the presentation graphs 1;

Fig. 3 is the oscillogram of action example of the shift register of expression first embodiment;

Fig. 4 is the oscillogram of action example of the shift register of expression second embodiment;

Fig. 5 is the concept map of the structure of expression liquid-crystal apparatus;

Fig. 6 is the block diagram of structure of the shift register of expression conventional example;

Fig. 7 is the concept map of expression as the level circuit structure at different levels of Fig. 6;

Fig. 8 is the oscillogram of action example of the shift register of presentation graphs 6;

Fig. 9 is the Vgs (grid-source voltage) of expression FET and the curve map of the corresponding relation of Ids (leakage current).

Embodiment

The present invention relates to following technology, on the substrate of liquid crystal indicator by register cells at different levels that form, such as a-Si as shift register in, the scanning drive signal that makes output drive liquid crystal cell is that the grid voltage of the output transistor of phase shifted clock Gout boosts to than conventional example height.

Promptly, the structure at different levels of shift register of the present invention is: the voltage of the phase shifted clock Gout (n-2) that will export from n-2 section grade (n-2) is as the voltage on the grid of the output transistor (M1) of the level n that is applied to the n section, raise by voltage, obtain thus than the grid voltage of high phase shifted clock size in the past from the phase shifted clock Gout (n-1) of n-1 section level (n-1) output.

(first embodiment)

Shift register first embodiment of the present invention, that be used as the gate drivers (liquid crystal display drive circuit) of Fig. 5 is described with reference to the accompanying drawings.Fig. 1 is the block diagram of the structure example of the shift register of above-mentioned first embodiment of expression.

In the figure, shift register 100 for cascade a plurality of level (register cells) 1,2,3,4 ... structure, with from a plurality of phases of the clock generator of outside input, for example the clock (CK1, CK2, CK3) by 3 phases makes the input data shift, by the level of having imported data make be input to this grade in clock synchronization mutually, from different levels respectively to terminal Mout1, Mout2, Mout3, Mout4 ... the output phase shift clock.

Wherein, when the input data that press the phase sequence input at arbitrary clock of 3 phase clocks, are shifted successively arrived self, output data (phase shifted clock) was exported on clock synchronization ground at different levels and that import.

Level 1 output phase shift clock Gout1, level 2 output phase shift clock Gout2, level 3 output phase shift clock Gout3, level 4 output phase shift clock Gout4.

Promptly, in shift register 100, make successively from the input data shift of commencing signal ST1 and ST2 input according to above-mentioned 3 grades of clocks, imported the level of data and the clock synchronization that is input to this grade, the terminal Moutn by connection to liquid crystal cell output phase shift clock as drive signal.

To level 1 input clock CK1, to level 2 input clock CK2, to level 3 input clock CK3, to level 4 input clock CK1 ..., to level n input clock CKm.(m is the remainder of n divided by " 3 ", and m is 3 under the situation about eliminating.)

Below, with reference to the structure of the level 3 of the shift register of Fig. 2 key diagram 1.Fig. 2 is the concept map (though the signal difference of other level input, structure is identical with this level 3) of the circuit structure of expression level 3.

Wherein, Moutn is Mout3, and n-2 section level n-2 is that the level n-1 of 1, the n-1 section of level is a level 2, and clock CKm is clock CK3.

The grid of output transistor M1 is connected with the drain electrode of transistor M2, and to drain electrode input clock CK3, source electrode is connected with terminal Mout3.

The source ground of transistor M2, drain electrode is connected with the grid of above-mentioned output transistor M1, to grid input control signal S2.

Diode D1 is an input circuit, and anode is connected on the terminal I1, and negative electrode is connected (connecting by tie point A) with the grid of output transistor M1.

This diode D1 also can be made of transistor by image pattern 2 like that, uses this moment the terminal that has connected grid and drain electrode as anode, uses source electrode as negative electrode.

Capacitor C1 one end is connected with the negative electrode of diode D1, and the other end is connected with the negative electrode of diode D2, that is, be inserted between the negative electrode of the negative electrode of diode D1 and diode D2.

Capacitor C2 one end is connected with the other end of capacitor C1, and the other end is connected with the source electrode of output transistor M1, that is, be inserted between the source electrode of the other end of capacitor C1 and output transistor M1.

Diode D2 is an input circuit, and anode is connected with terminal I2, and negative electrode is connected with the tie point B of the end of capacitor C2 with the other end of capacitor C1.

This diode D2 is the same with diode D1, can be made of transistor as shown in Figure 2, and as anode, use source electrode as negative electrode with the terminal that has connected grid and drain electrode this moment.

Transistor M2 source ground, drain electrode is connected with the grid of above-mentioned output transistor M1, and control signal S2 is input to grid.

Transistor M3 source ground, drain electrode is connected with above-mentioned tie point B, to grid input control signal S3.

Transistor M4 source ground, drain electrode is connected with the source electrode of above-mentioned output transistor M1, to grid input control signal S4.

Transistor M5 source ground, drain electrode is connected with the source electrode of above-mentioned output transistor M1, to grid input control signal S5.

Transistor M1～M5 all is a n channel fet (field effect transistor).

Below, be benchmark, the action of the shift register of an embodiment of the invention is described with Fig. 3 with level 3.Fig. 3 is the oscillogram of the action of the level 3 in the shift register of an embodiment of expression.

In level 3, the anode of diode D1 is connected with terminal Mout1, and the anode of diode D2 is connected with terminal Mout2.

At moment t1, because control signal S3 is " H " level, therefore, transistor M3 is the ON state; Because control signal S2, S4 and S5 are " L " level, so transistor M2, M4, M5 and output transistor M1 are OFF (disconnection) state.

At this moment, level 1 is transfused to the clock CK1 of predetermined pulse width, with the phase shifted clock Gout1 of this clock CK1 output synchronously with clock CK1 same widths.

Thus, in level 3, be input to the end of capacitor C1 by diode D1 phase shifted clock Gout1, be tie point A side, stored charge in capacitor 1 makes voltage become the voltage Vout-Vth that deducts the threshold voltage vt h of diode D1 from the voltage Vout of phase shifted clock Gout1.

Wherein, the other end of capacitor C1, be that tie point B side is owing to transistor M3 is that the ON state becomes earthing potential.

Then, at moment t2, control signal S3 becomes " L " level, and transistor M3 is in the OFF state, and control signal S4 becomes " H " level, and transistor M4 is the ON state, because control signal S2, S5 be " L " level, so transistor M2 and M5 are the OFF state.

At this moment, level 2 is transfused to the clock CK2 of predetermined pulse width, with the phase shifted clock Gout2 of this clock CK2 output synchronously with clock CK2 same widths.

Thus, in level 3, by diode D2 phase shifted clock Gout2 be input to capacitor 1 the other end, be tie point B side, stored charge on capacitor 2 makes voltage become the voltage Vout-Vth that deducts the threshold voltage vt h of diode D2 from the voltage Vout of phase shifted clock Gout2.

Here, the other end of capacitor C2, be that terminal Mout3 side becomes earthing potential owing to transistor M4 is in the ON state.

And by phase shift clock Gout2, the voltage of tie point B side becomes voltage Vout-Vth, so the voltage of the tie point A side of capacitor C1, rises to voltage (Vout-Vth) * 2 (bootstrapping effect) from voltage Vout-Vth.

Then, at moment t3, control signal S4 becomes " L " level, and transistor M4 is the OFF state, because control signal S2, S3, S5 are " L " level, so transistor M2, M3 and M5 are the OFF state.

At this moment, in level 3, become grid at output transistor M1 and applied voltage (state (as Vgs) of Vout-Vth) * 2, transistor M1 becomes the ON state.Because the source electrode of output transistor M3 is ground voltage (Vss), so voltage Vgs becomes above-mentioned voltage (Vout-Vth) * 2 between grid-source.

And, the clock CK3 of input predetermined pulse width in the drain electrode of output transistor M1, from the source electrode of output transistor M1 and this clock CK3 synchronously, export the phase shifted clock Gout3 of width and clock CK3 same widths.

And, phase shifted clock Gout (Gout1, Gout2, Gout3, Gout4 ...) as the back explanation, the voltage of " H " level is Vout, is following pulse: voltage and pulse width and the clock CK1～CK3 that exports from clock signal generator and identical from commencing signal ST1, the ST2 of control circuit, output circuit output.

Thus, when phase shifted clock Gout3 outputs to terminal Mout3, because with the other end of capacitor C2, be that the terminal Mout3 (source electrode of output transistor M3) of the opposition side that is connected of the tie point B of capacitor C2 is voltage Vout, therefore, the terminal of the tie point B side of capacitor C2 rises to voltage (Vout-Vth)+Vout from voltage Vout-Vth.

And, since the tie point B side of capacitor C1 from voltage Vout-Vth to (Vout-Vth)+Vout rising Vout, thus, be applied to capacitor C1 tie point A side, be that voltage on the grid of output transistor M1 is from voltage (Vout-Vth) * 2 rise to [(Vout-Vth) * 2+Vout].

The Vgs (gate source voltage) of output transistor M3 of this moment is (Vout-Vth) * 2.

Its result, the conducting resistance of output transistor M1 reduces significantly, provide enough electric currents to terminal Mout3, therefore can be to a plurality of liquid crystal cells that are connected on the back segment, provide enough electric currents to the transistorized grid (load of grid capacitance) that constitutes this liquid crystal cell, can make the pulse fast rise of phase shifted clock Gout3.

At this moment, owing on the grid of output transistor M1, applied voltage (Vout-Vth) * 2+Vout, so phase shifted clock Gout3 is as the signal of " H " level of the voltage Vout identical with clock CK3 roughly, promptly with the waveform output identical with clock CK3.

Therefore, when clock CK3 descended, phase shifted clock Gout3 is same to descend fast, becomes " L " level.

Then, at moment t4, control signal S2, S3 and S5 become " H " level, transistor M2, M3 and M5 become the ON state, terminal Mout3 becomes " L " level, and the electric charge that is stored among capacitor C1 and the C2 is released, and tie point A, B all become earthing potential (Vss current potential).

At this, though adopt during a plurality of pulse widths, make structure transistor M5, control signal S2, S3 and S5 conducting of the transistor M2 of clamper shown in Figure 2 (clamping) usefulness and M3 and conducting drop-down (pull down) usefulness, but also can adopt the transistor that a plurality of conductings are regularly different to connect side by side respectively, only make structure in the timing conducting of a pulse width.

And, to the anode of diode D1 import n-2 section the level (n-2) output phase shifted clock Gout (n-2), to the anode of diode D2 import n-1 section the level (n-1) output phase shifted clock Gout (n-1).

And, because

level

1 and 2 does not exist leading portion, the level of leading portion or leading portion again, the processing that the input data that will be shifted after therefore needing are imported separately.

That is, the timing of not shown control circuit and clock CK2 is synchronously to the anode input commencing signal ST1 of the diode D1 of level 1, with clock CK3 synchronously to the anode input commencing signal ST2 of diode D2.

Equally, the timing of above-mentioned control circuit and clock CK3 is synchronous, and to the anode input commencing signal ST2 of the diode D1 that gives level 2, level 1 is imported phase shifted clock Gout1 in the timing of clock CK1 to the anode of diode D2.

Thus, whole levels in the shift register are by different clock CK1, CK2 and the CK3 of phase place, the input data that are input to level 1 are shifted successively, have imported the level n and the synchronous output phase shift clock of the clock CKm Goutn that is transfused to of data.

As mentioned above, the action of the shift register of first embodiment, with existing shift register that the output of the level of leading portion is different as the input data, with 2 outputs (phase shifted clock Gout) of leading portion and leading portion again input data as displacement, the voltage of these 2 phase shifted clock Gout multiplies each other, and the level of accumulation becomes the level of having imported data.

Simply, confirm that the action of shift register of the present invention is as follows:

In moment t (-3), in level 1, import control signal S2, S3, S4, the S5 of " H " level respectively to the transistor M2～M5 of the level of all sections of shift register synchronously with clock CK2, carry out the initialization of shift register.

In moment t (-2), in level 1, import commencing signal ST1 (voltage Vout) to the anode of diode D1 synchronously with clock CK2.

At this moment, only transistor M3 is the ON state, and other transistor M2, M4, M5 are the OFF state.

Therefore, the pulse of the preset width by commencing signal ST1, (the corresponding electric charge of Vout-Vth) of storage and the voltage that deducts the threshold value Vth of diode D1 from voltage Vout on capacitor C1.

In moment t (-1), in level 1, import commencing signal ST2 (voltage Vout) to the anode of diode D2 synchronously with clock CK3.

At this moment, transistor M3 becomes the OFF state, and transistor M4 is in the ON state, and other transistor M2, M5 is the OFF state.

Therefore, the pulse of the preset width by commencing signal ST2, (the corresponding electric charge of Vout-Vth), the boost in voltage of connecting portion A is to voltage (Vout-Vth) * 2 for storage and the voltage that deducts the threshold value Vth of diode D2 from voltage Vout on capacitor C2.

And this moment, CK3 was synchronous with clock in level 2, to the anode input commencing signal ST2 (voltage Vout) of diode D1.

At this moment, only transistor M3 is in the ON state, and other transistor M2, M4, M5 are the OFF state.

Therefore, the pulse of the preset width by commencing signal ST2, (the corresponding electric charge of Vout-Vth) of storage and the voltage that deducts the threshold value Vth of diode D1 from voltage Vout on capacitor C1.

At moment t1, in level 1,, grid voltage (state of Vout-Vth) * 2, so output transistor M3 output phase shift clock Gout1 have been applied to the drain electrode input clock CK1 of output transistor M1.

At this moment, transistor M4 is in the OFF state, and other transistor M2, M3, M5 are the OFF state.

And in level 2, CK1 is synchronous with clock, from the anode input phase shifted clock Gout1 (voltage Vout) of leading portion to diode D2.

At this moment, transistor M3 becomes the OFF state, and transistor M4 becomes the ON state, and other transistor M2, M5 is the OFF state.

Therefore, the pulse of the preset width by phase shifted clock Gout1, (the corresponding electric charge of Vout-Vth), the voltage of connecting portion A rise to (Vout-Vth) * 2 for storage and the voltage that deducts the threshold value Vth of diode D2 from voltage Vout in capacitor C2.

At this moment, the input data are displaced to level 2 from level 1.

And in level 3, CK1 is synchronous with clock, from the anode input phase shifted clock Gout1 (voltage Vout) of leading portion to diode D2.

Thus, the pulse of the preset width by phase shifted clock Gout1, (the corresponding electric charge of Vout-Vth) of storage and the voltage that deducts the threshold value Vth of diode D1 from voltage Vout in capacitor C1.

At moment t2, in level 2, clock CK2 is input to the drain electrode of output transistor M1, is in to be applied in voltage (state of Vout-Vth) * 2, so output transistor M3 output phase shift clock Gout2 on the grid.

At this moment, transistor M4 is the OFF state, and other transistor M2, M3, M5 are the OFF state.

And, exporting above-mentioned phase shifted clock Gout2, transistor M2, M3, the M5 of level 1 become the ON state thus, and the output state of the output transistor M1 of level 1 is reset.

And in level 3, CK2 is synchronous with clock, from the anode input phase shifted clock Gout2 (voltage Vout) of leading portion to diode D2.

Therefore, the pulse of the preset width by phase shifted clock Gout2, (the corresponding electric charge of Vout-Vth), the voltage of connecting portion A rise to (Vout-Vth) * 2 for storage and the voltage that deducts the threshold value Vth of diode D2 from voltage Vout in capacitor C2.

At this moment, the input data are displaced to level 3 from level 2.

And, in level 4, with clock CK2 synchronously, from leading portion to the anode of diode D2 input phase shifted clock Gout2 (voltage Vout).

Thus, the pulse of the preset width by phase shifted clock Gout2, (the corresponding electric charge of Vout-Vth) of storage and the voltage that deducts the threshold value Vth of diode D1 from voltage Vout in capacitor C1.

Repeat above-mentioned processing, in shift register, the input data are shifted successively, as the phase shifted clock Gout of output data successively by the order of cascade from outputs at different levels.

(second embodiment)

Then, will be generated as under the more high-tension situation, and for example, can make clock be increased to 4 phases mutually, and make the input data of boosting be divided into 3 kinds by 3 at the voltage that applies on the grid of output transistor M1.

As mentioned above, if increase the number of phases of clock, the parts number that then constitutes the transistor etc. of shift register increases, and the wiring between the element increases too, and the area that forms shift register increases, and has the shortcoming of the size that influences liquid crystal indicator.

On the other hand, the grid voltage of output transistor boosts to more than or equal under the driving of the liquid crystal cell situation of required (comparing the voltage height of expecting), in order to improve the reliability of output transistor, can tie point A or tie point B decompression device is set so that be adjusted into suitable grid voltage.

And, as the voltage method that is controlled to be expectation, in level n, when importing n-2 section phase shifted clock Gout (n-2), the not conducting of transistor M3 that clamper is used makes the transistor M4 of drop-down usefulness or any conducting among the M5, makes capacitor C1 and capacitor C2 serial connection charge.

Fig. 4 represents the oscillogram of the action of level in 3 of Fig. 2 of this moment.

Action when moment t1, makes control signal S3, S4 still for " L " level as mentioned above, and to make transistor M3, M4 be the OFF state, and on the other hand, making control signal S5 is " H " level, and making transistor M5 is the ON state.

And phase shifted clock Gout1 is input to the anode of diode D1 from level 1 with predetermined pulse width.

Thus, if capacitor C1 is equated with the capacitance of capacitor C2, (Vout-Vth) in the same manner by dividing potential drop is recharged (charge storage) (voltage of Vout-Vth)/2 at the two ends separately of capacitor C1 and capacitor C2 to deduct the voltage of the threshold voltage vt h of diode D1 from the voltage Vout of phase shifted clock Gout1.

At this moment, the voltage of tie point A becomes voltage (Vout-Vth).

Then, at moment t2, make control signal S3 still be " L " level, and making transistor M3 is the OFF state, and on the other hand, making control signal S4 is " H " level, making transistor M4 is the ON state, and making control signal S5 is " L " level, and making transistor M5 is the OFF state.

And phase shifted clock Gout2 is input to the anode of diode D2 from level 2 with predetermined pulse width.

Thus, deduct the voltage (Vout-Vth) be recharged of the threshold value Vth of diode D1 at the two ends of capacitor C2 from the voltage Vout of phase shifted clock Gout1.

And, the voltage that is recharged at the two ends of capacitor C2, be that the voltage of tie point B becomes voltage (Vout-Vth) therefore, the two ends of capacitor C1, is that the voltage of tie point A is elevated to voltage (Vout-Vth) * (3/2).

Then,, make control signal S3, S5 still for " L " level, and make transistor M3, M5 be in the OFF state, and to make control signal S4 be " L " level that making transistor M4 is the OFF state at moment t3.

And the clock CK3 of predetermined pulse width is input to the drain electrode of output transistor M1 from clock signal generator, and terminal Mout3 (source electrode of output transistor M1) voltage becomes Vout.

Thus, because the voltage of tie point B is voltage [(Vout-Vth)+Vout], so the two ends of capacitor C1, be that the boost in voltage of tie point A is to [(Vout-Vth) * (3/2)+Vout].

The Vgs (gate source voltage) of output transistor M3 of this moment is (Vout-Vth) * (3/2).

As mentioned above, by adjusting the capacity ratio of capacitor C1 and C2, (resulting voltage in Vout-the Vth)+Vout and first embodiment can be finely tuned between [(Vout-Vth) * 2+Vout] in the past bootstrap voltage mode.Other action is identical with first embodiment.

Therefore, as long as the capacity ratio of capacitor C1 and C2 is designed to: make output transistor M1 that the magnitude of current with the speed action of needs can be provided to the load of the transistorized grid of liquid crystal cell, and make that grid voltage (voltage of tie point A) is the conducting resistance that can access output transistor M1.

And the circuit structure of the shift register of above-mentioned first and second embodiments not only can be applied to a-Si (amorphous silicon) TFT (thin film transistor (TFT)), and can be applied to the gate drivers of multi-crystal TFT or the driver IC of monocrystalline silicon (integrated circuit).

Claims

1. a shift register has a plurality of levels that cascade connects, and will import data shift with the different a plurality of clocks of phase place, when these input data of input, the clock that is input to the drain electrode of output transistor is exported from source electrode as phase shifted clock, carry out the shift motion of output signal, it is characterized in that

To the phase shifted clock of n-2 section of the level input of n section and n-1 section, by the phase shifted clock of n-2 section and n-1 section, the grid voltage to above-mentioned output transistor boosts successively;

In above-mentioned a plurality of levels, first capacitor and second capacitors in series are connected between the grid and source electrode of above-mentioned output transistor;

This shift register has:

First input circuit makes above-mentioned n-2 section phase shifted clock be input to the connecting portion of the above-mentioned grid and first capacitor; And

Second input circuit makes above-mentioned n-1 section phase shifted clock be input to the connecting portion of above-mentioned first capacitor and second capacitor;

Adjust the capacity ratio of above-mentioned first capacitor and second capacitor, control is input to the ratio of the boost in voltage of above-mentioned grid.

2. shift register as claimed in claim 1 is characterized in that, above-mentioned first input circuit and second input circuit are diode.

3. a liquid crystal display drive circuit is characterized in that, the described shift register of each in the claim 1 to 2 is used to generate sweep trace and signal wire and intersects the scanning drive signal of the active matrix circuit that constitutes.