TWI416874B - Shift register apparatus and active array substrate - Google Patents

Abstract

A shift register apparatus and an active array substrate are provided. The shift register apparatus includes a plurality of shift registers, wherein each of the shift registers coupled to each other in series and includes a start transistor, an output transistor and a capacitor. The start transistor has a first gate coupling to a last shift register, a first source coupling to a start signal and a first drain. The output transistor has a second gate coupling to the first drain, a second source outputting a scanning signal and a second drain coupling to a first clock signal. Moreover, a capacitance between the second gate and the second source is greater than a capacitance between the second gate and the second drain. The capacitor is coupled between the second source and the second gate.

Description

Shift register device and active array substrate

The present invention relates to a shift register device and a substrate, and more particularly to a shift register device disposed on a substrate and an active array substrate.

In recent years, with the rapid development of semiconductor technology, portable electronic products and flat panel display products have also emerged. Among the many types of flat panel displays, liquid crystal displays (LCDs) have become the mainstream of display products based on their low voltage operation, no radiation scattering, light weight and small size. Because of this, all of them are driving the development technology of liquid crystal displays to miniaturization and low production costs.

In order to reduce the manufacturing cost of the liquid crystal display, some manufacturers have made a multi-stage amorphous shift register (a-Si shift register) directly on the glass substrate of the panel through the amorphous germanium process. The gate driver is conventionally used to achieve the purpose of reducing the manufacturing cost of the liquid crystal display.

In general, an output transistor is provided in each shift register that is turned on when the shift register is turned on. At this time, the clock signal received by the drain of the output transistor is outputted by its source as a scan signal to increase the voltage level of the scan signal by outputting a clock signal. However, when the output transistor is not conducting, the drain of the output transistor still receives the clock signal. At this time, the output transistor is equivalent to two capacitors connected in series, that is, the equivalent capacitor between the gate and the drain of the transistor and the equivalent capacitor between the gate and the source of the transistor, so that the source of the output transistor The output will be rippled, and if the ripple is too large, it may affect the operation of the circuit. Therefore, in order to reduce the size of the chopping, a capacitor of a large capacitance value is generally connected in parallel between the gate and the source of the output transistor. Since this capacitor must have a large capacitance value, it will occupy a certain layout area, thereby affecting the flexibility of the internal circuit layout of the shift register.

The invention provides a shift temporary storage device which can increase the capacitance value between the gate and the source of the output transistor to reduce the capacitance value of the capacitor connected in parallel.

The invention also provides an active array substrate, which can reduce the area of the capacitor of the output transistor in parallel with the source to reduce the area of the shift register.

The invention provides a shift register device comprising a plurality of shift registers connected in series with each other. Each shift register includes a start transistor, an output transistor, a capacitor, a first pull down circuit, and a second pull down circuit. The starting transistor has a first gate, a first source and a first drain, wherein the first gate is coupled to the previous stage shift register, and the first source is coupled to the start Signal. The output transistor has a second gate, a second source and a second drain, wherein the second gate is coupled to the first drain, the second source outputs a scan signal, and the second drain is coupled Connected to a first clock signal, and the capacitance value (Cgs) between the second gate and the second source is greater than the capacitance value (Cgd) between the second gate and the second drain. The capacitor is coupled between the second source and the second gate. The first pull-down circuit is coupled to the second gate. The second pull-down circuit is coupled to the second source.

In an embodiment of the invention, the ratio of the capacitance value (Cgs) between the second gate and the second source to the capacitance value (C) of the capacitor is between 1:100 and 37:100.

In an embodiment of the invention, the output transistor is a bottom gate transistor.

In an embodiment of the invention, the output transistor is a top gate transistor.

In an embodiment of the invention, the second source includes a plurality of source branches connected to each other, and the second drain includes a plurality of drain branches connected to each other, and the source branches and the drain branches are mutually connected Electrically insulated, and the number of these source branches is greater than the number of these bungee branches.

In an embodiment of the invention, the overlapping area of the source branches and the second gates is greater than the overlapping area of the drain branches and the second gates.

In an embodiment of the invention, the output transistor has a semiconductor layer, and the ratio of the area of the semiconductor layer to the gate is about 0.001 to 0.9.

In an embodiment of the invention, the second gate is a rectangular gate and the semiconductor layer is a rectangular semiconductor layer.

In one embodiment of the invention, the rectangular gate is a square gate and the semiconductor layer is a square semiconductor layer.

In an embodiment of the invention, the rectangular gate is a rectangular gate and the semiconductor layer is a rectangular semiconductor layer.

In an embodiment of the invention, the source branches and the extension directions of the dipole branches are parallel to the two short sides of the rectangular gate, and the source branches and the dipole branches are respectively from the rectangular gate The long side extends onto the semiconductor layer.

In an embodiment of the invention, the shortest distance between at least one side of the rectangular gate and one side of the rectangular semiconductor layer is greater than 3 microns.

In an embodiment of the invention, the source branches and the extension directions of the drain branches are parallel to each other.

In an embodiment of the invention, the semiconductor layer comprises a plurality of semiconductor patterns independent of each other, and a gap is maintained between any two adjacent semiconductor patterns.

In one embodiment of the invention, the gap described above is between about 3 microns and 100 microns.

The invention also provides an active array substrate comprising a substrate, a driving circuit and an active array. The substrate has an active area and a peripheral circuit area. The driving circuit is located on the substrate and located in the peripheral circuit region, and the driving circuit includes the shift register device as described above. The active array is located on the substrate and located in the active area, and is electrically connected to the driving circuit.

Based on the above, the shift register device and the active array substrate of the present invention increase the capacitance between the gate and the source of the output transistor by increasing the overlap area between the source and the gate of the output transistor. Thereby, the capacitance value of the capacitor coupled to the output transistor can be reduced to reduce the area of the capacitor.

The above described features and advantages of the present invention will be more apparent from the following description.

FIG. 1 is a top plan view of an active array substrate according to an embodiment of the invention. Referring to FIG. 1, the active array substrate 100 includes a substrate 102, a driving circuit 104, and an active array. The substrate 100 has an active region 106 and a peripheral circuit region 108. The material of the substrate 110 is, for example, glass, plastic or other suitable material. The active array is located on the substrate 100 and located in the active area 106, and is electrically connected to the driving circuit 104. The active array includes a plurality of pixel structures 110, a plurality of data lines 114 electrically connected to the pixel structure 110, and a plurality of scan lines 112. The material of the data line 114 and the scan line 112 is, for example, a metal. Each pixel structure 110 is electrically connected to a data line 114 and a scan line 112 for driving by the data line 114 and the scan line 112. Each of the pixel structures 110 mainly has a thin film transistor 110a and a pixel electrode 110b.

The drive circuit 104 is located on the substrate 100 and is located within the peripheral circuit region 110. The drive circuit 104 includes a source driver 116 and a shift register 118. The shift register 118 sequentially supplies the scan signal SC to the scan line 112. Source driver 116 provides display data to data line 114. In this embodiment, the shift register 118 includes a plurality of shift registers SR connected in series with each other, and the shift registers SR are based on the vertical start signal VST, the clock signal CK and the XCK. The scan signal SC is turned on and the scan signal SC is output, wherein the clock signal CK can be 180 degrees out of phase with the XCK, and the instant pulse signal CK can be the inverted signal of the clock signal XCK. However, other embodiments are not limited thereto.

FIG. 2 is a circuit diagram of a shift register according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, in the embodiment, the shift register SR includes a start transistor MS, an output transistor MO, a capacitor C1, and transistors M1 and M2, wherein the transistor MS and the output power are started. The crystal MO, the transistors M1 and M2 may be a bottom gate transistor or a top gate transistor. The gate and the source of the start transistor MS can be coupled to the previous stage shift register RS to receive the start signal SS, wherein the start signal SS is the scan signal SC of the previous stage shift register RS. However, if the shift register SR is the first one, the gate and the source of the start transistor MS are coupled to a vertical start signal VST.

The gate of the output transistor MO is coupled to the drain of the start transistor MS, and the source of the output transistor MO outputs a corresponding scan signal SC(n). When the shift register is an odd shift register, the drain of the output transistor MO is coupled to the clock signal CK; otherwise, the drain of the output transistor MO is coupled to the clock signal XCK. The capacitance value of the equivalent capacitor Cgs between the gate and the source of the output transistor MO is greater than the capacitance of the equivalent capacitor Cgd between the gate and the drain of the output transistor MO. The capacitor C1 is coupled between the gate and the source of the output transistor MO, and the ratio of the capacitance of the equivalent capacitor Cgs to the capacitance of the capacitor C1 is between 1:100 and 37:100.

The gate of the transistor M1 is coupled to the gate of the output transistor MO, the source of the transistor M1 is coupled to the reference voltage VSS, and the gate of the transistor M1 is coupled to the scan signal of the shift register RS of the subsequent stage. SC(n+1), in which the transistor M1 can be regarded as a pull-down circuit, and the voltage level of the gate of the output transistor MO is pulled down. The drain of the transistor M2 is coupled to the source of the output transistor MO, and the source of the transistor M2 is coupled to the reference voltage VSS. When the shift register is an odd shift register, the gate of the transistor M2 is coupled to the clock signal XCK; otherwise, the gate of the transistor M2 is coupled to the clock signal CK. The transistor M2 can also be regarded as a pull-down circuit, and the voltage level of the scan signal SC(n) is pulled down.

FIG. 3 is a timing diagram showing the operation of the shift register SR according to an embodiment of the invention. Referring to FIG. 1 to FIG. 3, the first shift register is taken as an example. In the period T1, the start transistor MS receives the start signal SS (ie, the vertical start signal VST), and starts the power. The crystal MS is turned on to transfer the start signal SS to the gate of the output transistor MO. At this time, the start signal SS charges the capacitor C1, so that the voltage level of the node A rises, and when the voltage level of the node A is greater than the threshold voltage of the output transistor MO, the output transistor MO is turned on.

In the period T2, the output transistor MO receives the clock signal CK and outputs the clock signal CK as the scan signal SC(n). As shown in FIG. 2, the capacitor C1 and the output transistor MO form a bootstrap configuration. Therefore, when the clock signal CK outputs the clock signal CK, the voltage level of the node A suddenly rises. In other words, when the output transistor MO outputs the pulse signal CK, the voltage level of the source of the output transistor MO is equal to the clock signal CK, and the potential difference stored by the capacitor C1 is still present, so that the voltage level of the node A will be Was raised.

In the period T3, the transistor M2 receives the clock signal XCK and is turned on, whereby the voltage level of the pull-down scan signal SC(n) is the reference voltage VSS. Moreover, the transistor M1 receives the scan signal SC(n+1) and is turned on, whereby the voltage level of the pull-down node A is the reference voltage VSS. In the period T4 and after, although the output transistor MO is in a non-conducting state, the output transistor MO will be similar to the two capacitors in series, so when the rising edge and the falling edge of the clock signal CK, the node A and the scanning The signal SC(n) will still generate ripples. Since node A is inside the circuit, it can be ignored. However, the chopping of the scanning signal SC(n) may cause the erroneous action of the thin film transistor 110a, so the smaller the chopping of the scanning signal SC(n), the better.

According to the above, the sum of the capacitance value of the capacitor C1 of the present invention and the capacitance value of the equivalent capacitor Cgs is larger than the capacitance value of the equivalent capacitor Cgd, thereby suppressing the magnitude of the chopping of the scanning signal SC(n). Moreover, the present invention can improve the capacitance value of the equivalent capacitor Cgs by modifying the mask of the output transistor MO process (which will be described later). After the capacitance value of the equivalent capacitor Cgs is increased, the capacitance value of the capacitor C1 can be correspondingly reduced, thereby reducing the area in which the capacitor C1 is formed.

In addition, the operation of the other shift register SR can be referred to the above description, the difference is in the operation timing difference, and A' in FIG. 3 is the operation timing of the node A of the second shift register. It is generally understood by those skilled in the art and will not be described in detail.

FIG. 4A is a top view of an output transistor MO according to an embodiment of the invention. Referring to FIG. 4A, the output transistor MO includes a gate 400, a gate insulating layer (not shown for convenience of explanation), a semiconductor layer 402, a plurality of source branches 406, a source connection line 410, and a plurality of drain branches 404. Connect with the drain line 408. The material of the gate 400 is, for example, a metal. The gate 400 is, for example, a rectangular gate. The gate insulating layer is disposed on the gate 400, and the material of the gate insulating layer is, for example, tantalum oxide, tantalum nitride or other suitable dielectric material.

The semiconductor layer 402 is disposed on the gate insulating layer and above the gate 400 for use as a channel layer, and the material of the semiconductor layer 402 is, for example, amorphous germanium. The semiconductor layer 402 is, for example, a rectangular semiconductor layer. The area ratio of the semiconductor layer 402 to the gate 400 is about 0.001 to 0.9. The source branches 406 are electrically connected to each other through the source connection line 410 to form a source, and the drain branches 404 are electrically connected to each other through the gate connection line 408 to form a drain, and the source branch 406 and the drain branch 404 are mutually connected to each other. Electrical insulation. The material of the source branch 406, the source connection line 410, the drain leg 404, and the drain connection line 408 is, for example, a metal. In addition, the source branch 406 and the drain branch 404 extend in parallel with each other, and the source branch 406 and the drain branch 404 extend from the opposite sides of the gate 400 to the semiconductor layer 402, respectively, and are alternately arranged on the semiconductor layer. 402. As shown in FIG. 4A, the number of source branches 406 is greater than the number of the drain branches 404, so that the overlapping area of the source branches 406 and the gates 400 is larger than the overlapping area of the drain branches 404 and the gates 400, thereby improving The capacitance value of the equivalent capacitor Cgs between the gate and the source of the output transistor MO.

In detail, in the present embodiment, the gate 400 is, for example, a square gate, and the semiconductor layer 402 is, for example, a square conductor layer. Further, the area of the gate 400 is increased such that the ratio of the area of the semiconductor layer 402 to the gate 400 is about 0.001 to 0.9. The manner in which the area of the gate 400 is increased is, for example, such that the shortest distance between one side of the gate 400 and one side of the semiconductor layer 402 is greater than 3 μm.

In particular, in the present embodiment, the shortest distance between one side of the gate 400 and one side of the semiconductor layer 402 is greater than 3 microns, such that the ratio of the area of the semiconductor layer 402 to the gate 400 may be about 0.001 to 0.9. In another embodiment, the shortest distance between the four sides of the gate and the four sides of the semiconductor layer may be greater than 3 micrometers (as shown in FIG. 4B) to further increase the gate area (reducing the semiconductor layer and the gate). Area ratio). Further, in Fig. 4B, the shortest distance between each side of the gate 400' and each side of the semiconductor layer 402 may be the same or different from each other. In other embodiments, the shortest distance between the two sides of the gate and the two sides of the semiconductor layer is greater than 3 micrometers, or the shortest distance between the three sides of the gate and the three sides of the semiconductor layer is greater than 3 micrometers. And these shortest distances can be the same or different.

Moreover, in the present embodiment, the gate 400 can extend below the illustration to increase the area of the gate 400 overlapping the source branch 406, even overlapping the source connection line 410 (as shown in FIG. 4C). In FIG. 4C, the gate 400" extends below the figure such that the source connection line 410 is located on the gate 400", thereby increasing the equivalent capacitor Cgs between the gate and the source of the output transistor MO. Capacitance value. In this embodiment, the source connection line 410 and the gate 400" partially overlap, but in other embodiments, the source connection line 410 and the gate 400" may be completely overlapped, and the source connection line 410 and The proportion of the gate 400" overlap can be adjusted by itself.

FIG. 4D is a top view of an output transistor MO according to another embodiment of the invention. Referring to FIG. 4D, in the output transistor MO, the semiconductor layer 202' is a plurality of semiconductor patterns (not labeled) that are independent of each other, and a gap S is maintained between any two adjacent semiconductor patterns, so that the semiconductor layer 402' The ratio of the area to the gate 400 is about 0.001 to 0.9. The gap S is, for example, about 3 micrometers to 100 micrometers, and these gaps S may be the same or different. Moreover, on each semiconductor pattern, the number of source branches 406 is greater than the number of drain branches 404, so that the overlap area of the source branches 406 and the gates 400 is much larger than the overlap area of the drain branches 404 and the gates 400. Thereby, the capacitance value of the equivalent capacitor Cgs between the gate and the source of the output transistor MO can be greatly improved. It should be noted that in each of the above embodiments, the gates are all square, but in other embodiments, the gate and the semiconductor layer may also be rectangular.

4E is a top plan view of a bottom gate thin film transistor according to another embodiment of the invention. Referring to FIG. 4E, in the embodiment, the gate 400"" and the semiconductor layer 402" are both rectangular. The source branch 406 and the drain branch 404 extend in parallel, for example, to the gate 400"". The short side, and the source branch 404 and the drain branch 406 extend from the two long sides of the gate 400"" to the semiconductor layer 402", respectively. In addition, in FIG. 4E, the arrangement relationship between the remaining components is the same as that of the components in FIG. 4B, that is, the shortest distance between the four sides of the gate 400''' and the four sides of the semiconductor layer 402" is greater than 3 micrometers. And these shortest distances can be the same or different.

Of course, in the case where the gate 400''' and the semiconductor layer 402" are both rectangular, one side (two or three sides) of the gate 400"' and one side of the semiconductor layer 402" (two sides or The shortest distance of the three sides is greater than 3 microns; or the semiconductor layer 402" is a plurality of mutually independent semiconductor patterns, and a gap is maintained between any two adjacent semiconductor patterns; or the gate 400"' The shortest distance between one side (two sides or three sides) and one side (two sides or three sides) of the semiconductor layer 402" is greater than 3 micrometers, and the semiconductor layer 402" is a plurality of semiconductor patterns independent of each other, and any two adjacent A gap is maintained between the semiconductor patterns.

FIG. 5 is a circuit diagram of a shift register according to another embodiment of the invention. Referring to FIG. 2 and FIG. 5, the difference is that the shift register SR of the present embodiment further includes transistors M3, M4, M5 and a capacitor C2, and the same operation as the element of FIG. 2 is performed here. No longer. The gate of the transistor M3 is coupled to the drain of the start transistor MS, and the source of the transistor M3 is coupled to the reference voltage VSS. The capacitor C2 is coupled between the clock signal CK (or XCK) and the drain of the transistor M3. The gate of the transistor M4 is coupled to the drain of the start transistor MS, the gate of the transistor M4 is coupled to the drain of the transistor M3, and the source of the transistor M4 is coupled to the reference voltage VSS2. The gate of the transistor M5 is coupled to the source of the output transistor MO, the gate of the transistor M5 is coupled to the drain of the transistor M3, and the source of the transistor M5 is coupled to the reference voltage VSS.

FIG. 6 is a timing diagram showing the operation of the shift register SR according to another embodiment of the present invention. Referring to FIG. 5 and FIG. 6 , the first shift register SR is taken as an example. In the period T1 , the transistor M3 receives the start signal SS and is turned on, and the transistors M4 and M5 are non-conductive. The capacitor C2 is coupled to the reference voltage VSS via the turned-on transistor M3. In the period T2, the turned-on transistor M3 couples the capacitor C2 between the clock signal CK and the reference voltage VSS, and the clock signal CK charges the capacitor C2, so the node B rises at the clock signal CK. There was a surge. During the period T3, the transistors M1 and M2 are turned on to pull down the voltage levels of the node A and the scanning signal SC(n), respectively, so that the transistor M3 is not turned on.

In the period T4, since the transistor M3 is not turned on, the clock signal CK can pull the voltage level of the node B through the capacitor C2, so that the transistors M4 and M5 are turned on, and the turned-on transistor M4 pulls down the node. The voltage level of A is to the reference voltage VSS2, and the turned-on transistor M5 pulls down the voltage level of the scan signal SC(n) to the reference voltage VSS. It is worth mentioning that in other embodiments, the source of the transistor M4 can also be coupled to the reference voltage VSS, which can be changed according to the design requirements.

In summary, the shift register device and the active array substrate of the present invention increase the overlap area of the source branch and the gate, and even overlap the source connection line and the gate to increase the output gate of the transistor. The value of the capacitance between the sources. Thereby, the capacitance value of the capacitor coupled to the output transistor can be reduced to reduce the area of the capacitor. Moreover, by making the ratio of the area of the semiconductor layer and the gate of the output transistor to about 0.001 to 0.9, when the output transistor generates high self-heating, the heat dissipation rate can be effectively improved to avoid the component due to self-heating. Reliability is reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Active array substrate

102. . . Substrate

104. . . Drive circuit

106. . . Active zone

108. . . Peripheral circuit area

110. . . Pixel structure

110a. . . Thin film transistor

110b. . . Pixel electrode

112. . . Scanning line

114‧‧‧Information line

116‧‧‧Source Driver

118‧‧‧Shift register

400, 400', 400", 400'''‧‧‧ gate

402, 402', 402" ‧‧ ‧ semiconductor layer

404‧‧‧Bungan branch

406‧‧‧Source branch

408‧‧‧汲 connection cable

410‧‧‧Source cable

A, B‧‧‧ nodes

C1, C2‧‧‧ capacitor

Cgs, Cgd‧‧‧ equivalent capacitor

CK, XCK‧‧‧ clock signal

L‧‧‧ length

MS, MO, M1~M5‧‧‧O crystal

S‧‧‧ gap

SC, SC(n), SC(n+1)‧‧‧ scan signals

SR‧‧‧Shift register

SS‧‧‧ start signal

During the period of T1~T4‧‧

VSS, VSS2‧‧‧ reference voltage

VST‧‧‧ vertical start signal

W‧‧‧Width

FIG. 1 is a top plan view of an active array substrate according to an embodiment of the invention.

FIG. 2 is a circuit diagram of a shift register according to an embodiment of the invention.

FIG. 3 is a timing diagram showing the operation of the shift register SR according to an embodiment of the invention.

FIG. 4A is a top view of an output transistor MO according to an embodiment of the invention.

FIG. 4B is a top view of an output transistor MO according to another embodiment of the invention.

FIG. 4C is a top view of an output transistor MO according to another embodiment of the invention.

FIG. 4D is a top view of an output transistor MO according to another embodiment of the invention.

4E is a top view of an output transistor MO according to another embodiment of the invention.

FIG. 5 is a circuit diagram of a shift register according to another embodiment of the invention.

FIG. 6 is a timing diagram showing the operation of the shift register SR according to another embodiment of the present invention.

400. . . Gate

402. . . Semiconductor layer

404. . . Bungee branch

406. . . Source branch

408. . . Bungee connection line

410. . . Source connection line

L. . . length

W. . . width

Claims (17)

A shift register device includes: a plurality of shift registers connected in series with each other, each of the shift registers comprising: a start transistor having a first gate, a first source, and a a first gate, the first gate is coupled to the previous stage shift register, and the first source is coupled to a start signal; and an output transistor has a second gate and a second a source and a second drain, the second gate is coupled to the first drain, the second source outputs a scan signal, and the second drain is coupled to a first clock signal, wherein the second drain a capacitance value (Cgs) between the second gate and the second source is greater than a capacitance value (Cgd) between the second gate and the second drain; a capacitor coupled to the second source Between the pole and the second gate, wherein a ratio of a capacitance value (Cgs) between the second gate and the second source to a capacitance value (C) of the capacitor is between 1:100 and 37:100 a first pull-down circuit coupled to the second gate; and a second pull-down circuit coupled to the second source. The shift register device of claim 1, wherein the output transistor is a bottom gate transistor. The shift register device of claim 2, wherein the second source comprises a plurality of source branches connected to each other, and the second drain comprises a plurality of drain branches connected to each other, The source branches and the drain branches are electrically insulated from each other, and the number of the source branches is greater than the number of the drain branches. The shift register device of claim 2, wherein an overlap area of the source branches and the second gates is larger than an overlap area of the drain branches and the second gates. The shift register device of claim 1, wherein the output transistor is a top gate transistor. The shift register device of claim 5, wherein the second source comprises a plurality of source branches connected to each other, and the second drain comprises a plurality of drain branches connected to each other, The source branches and the drain branches are electrically insulated from each other, and the number of the source branches is greater than the number of the drain branches. The shift register device of claim 5, wherein an overlap area of the source branches and the second gates is larger than an overlap area of the drain branches and the second gates. The shift register device of claim 1, wherein the output transistor has a semiconductor layer, and an area ratio of the semiconductor layer to the gate is about 0.001 to 0.9. The shift register device of claim 1, wherein the second gate is a rectangular gate and the semiconductor layer is a rectangular semiconductor layer. The shift register device of claim 9, wherein the rectangular gate is a square gate and the semiconductor layer is a square semiconductor layer. The shift register device of claim 9, wherein the rectangular gate is a rectangular gate and the semiconductor layer is a rectangular semiconductor layer. A shift register device according to claim 11 of the patent application, The source branches and the extension directions of the drain branches are parallel to the two short sides of the rectangular gate, and the source branches and the drain branches respectively extend from the two long sides of the rectangular gate to On the semiconductor layer. The shift register device of claim 9, wherein a shortest distance between at least one side of the rectangular gate and one side of the rectangular semiconductor layer is greater than 3 micrometers. The shift register device of claim 1, wherein the source branches and the extension directions of the drain branches are parallel to each other. The shift register device of claim 1, wherein the semiconductor layer comprises a plurality of semiconductor patterns independent of each other, and a gap is maintained between any two adjacent semiconductor patterns. The shift register device of claim 15, wherein the gap is about 3 microns to 100 microns. An active array substrate comprises: a substrate having an active region and a peripheral circuit region; a driving circuit located on the substrate and located in the peripheral circuit region, the driving circuit comprising the first to the 17th as claimed in the patent scope The shift register device of any one of the preceding claims; and an active array on the substrate and located in the active region, electrically connected to the driving circuit.