CN100459154C - 具有感测结构的半导体器件 - Google Patents

具有感测结构的半导体器件 Download PDF

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CN100459154C
CN100459154C CNB038228998A CN03822899A CN100459154C CN 100459154 C CN100459154 C CN 100459154C CN B038228998 A CNB038228998 A CN B038228998A CN 03822899 A CN03822899 A CN 03822899A CN 100459154 C CN100459154 C CN 100459154C
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circuit
sensing
sensing cell
group
output
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CN1685519A (zh
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R·路易斯
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Yasuyo Co Ltd
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Koninklijke Philips Electronics NV
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Abstract

本发明描述了一种具有多个单元的功率半导体器件，这些单元分为功率单元(14)和感测单元(16)。提供了多组(30、32)感测单元(16)。该器件允许对各组感测单元(16)边缘引起的效应进行补偿。

Description

具有感测结构的半导体器件
技术领域
本发明涉及一种具有感测结构的半导体器件，特别地涉及具有感测端子的功率半导体器件，本发明还涉及包括该功率半导体器件的系统。
背景技术
现有技术的功率半导体器件的一个已知实例为感测金属氧化物半导体场效应晶体管(MOSFET)结构，传统上将其简称为Sens eMOS。SenseMOS具有传统MOS的源极、栅极、与漏极以及另外的感测端子，该感测端子提供的感测电流应与负载电流成比例。在理想的Sens eMOS结构中，感测电流应在所有工作条件下都与负载电流成比例。
例如，可以使用感测端子上的电流输出来制作电流保护开关。可将感测电流与一个预定电流进行比较，当感测电流变得太大时，降低施加在Sens eMOS结构的栅极上的电压以减小输出电流。
Philips Electronics NV公司的专利WO 96/12346描述了Sens eMOS结构的一个例子及其在电流保护开关中的使用。该器件具有多个MOSFET单元，这些单元中的几个连接到感测端子以提供感测电流，其余部分连接到主输出端子以提供用于驱动负载的主输出电流。
技术人员将会了解到，在这些应用中，感测电流应在各种不同条件下能够精确地跟踪主电流是很重要的，此外还非常希望的是，主单元中的电流与感测单元中的电流之比应等于单元数目之比。这意味着，工作时每个单元内的条件应尽可能相同，特别地，数量少的感测单元中的条件应该与主单元中的条件匹配。然而，这种精确匹配并非总是可能的，特别是在没有使用昂贵的加工技术、采用小的单元尺寸(例如小于约5至6微米)的情况下。
发明内容
本发明目的在于解决这个困难，并允许对主电流进行更加精确的跟踪。
根据本发明，提供了一种功率半导体器件，包括：第一主端子与第二主端子，至少其中之一用于耦合负载；控制端子；以及半导体主体，该半导体主体具有相对的的第一和第二主要表面和在半导体主体的第一主要表面上排列成网格(lattice)的多个半导体单元，这些半导体单元分为主单元和感测单元，每个半导体单元具有与控制端子连接的栅极或基极；其中每个主单元并联地连接在第一和第二主端子之间，以在控制端子的控制之下耦合第一和第二主端子；该功率半导体器件还包括第一和第二感测端子；这些感测单元划分为多组感测单元，每组感测单元在网格上排列成一个图形，每组感测单元并联地连接在各个感测端子与第一主端子之间；并且第一组感测单元在网格上排列成一个图形，该图形的边缘单元与内部单元之比不同于第二组感测单元，其中内部感测单元被该组的其它感测单元包围，且边缘感测单元则排列在该组感测单元的边缘上。
本发明人已经意识到现有技术器件中的一个问题为边缘效应。换而言之，位于主单元和感测单元之间边界处的单元中的电学条件经常不同于单元的体内的电学条件。当主单元和感测单元之间存在既没有连接到主电极也没有连接到感测电极的空单元(dummy cell)时，该问题尤其严重。这些未连接的空单元影响边缘单元内的电流，这将在下文中进行更详细的解释。
主单元中，位于主单元组边缘的单元数目相对于单元的总数而言很少，这种边缘效应通常非常小。然而，感测单元的数目通常要少得很多，感测单元内的边缘效应会变得非常显著。在现有技术的器件中，这意味着感测单元并未精确地跟踪主单元内的电流。
根据本发明的半导体器件通过提供两个不同的感测单元组以及各自的感测端子来补偿这种边缘效应，感测单元组在单元网格内排列成各种图形，使得这两组感测单元具有不同的边缘单元与内部单元之比。于是这两个输出电流提供充分的信息以对内部单元内的电流的度量以及用作对边缘单元内的电流的度量。
优选地，第一组感测单元内边缘单元的数目基本上与第二组中的相匹配。这使得对边缘效应的校正尤为容易。
在一个特别方便的配置中，第一组感测单元排列成至少含有40％、优选50％、更优选80％的边缘单元的图形，例如，这可以通过采用一行单元作为感测单元来实现。该第一组感测单元的输出于是提供了边缘单元内电流的度量。第二组感测单元排列成具有更多数目的内部单元，尽管它不可避免地也会含有边缘单元。于是，可以使用第一组的电流输出来对第二组感测单元的电流输出进行边缘效应的校正。这个校正后、或补偿后的信号随后代表主单元内电流的更加精确的度量。
本发明特别适用于功率MOSFET，其中的半导体单元为具有栅极、源极和漏极的MOS单元。主单元的源极和漏极连接到第一和第二主端子，一组感测单元的源极和漏极连接在第一主端子和该组的各自感测端子之间。
在实施例中，MOSFET可以为沟道MOSFET。本领域技术人员将会意识到本发明并不局限于沟道MOSFET，本领域技术人员将会熟悉许多其它有用的单元结构，例如包括垂直和侧向MOSFET结构甚至是绝缘栅双极器件的阵列。
半导体单元可以为任何容易实现的形状，例如，六边形、方形、或条形。
功率半导体器件可以封装成分立的功率半导体器件。
本发明还涉及包括该半导体器件的半导体装置，且该半导体配置还包括一个补偿电路以及一个输出连接到控制端子用于驱动控制端子的驱动电路。
优选地，补偿电路具有分别直接或间接地连接到第一和第二感测端子的第一和第二感测输入，以及连接到驱动电路以控制驱动电路的输出，其中补偿电路把从第一和第二感测输入上的电流中获得的内部感测单元内电流的度量输出到驱动电路。
补偿电路可能包括参考子电路，该参考子电路具有连接到第一感测端子的输入和提供参考电压的输出，其中来自第一感测端子的电流施加在一个电阻器上，使参考电压随着来自第一组感测单元的电流而线性增加。
补偿电路可能还包括一个感测子电路，该感测子电路具有连接到与第二组感测单元相连的第二感测端子的输入，并且补偿输入连接到参考子电路的输出；该感测子电路还具有一个输出，把补偿后的感测电流信号提供至驱动电路输入，用于控制驱动电路以限制该功率半导体器件的电流输出。可以把来自第二组感测单元的电流施加在与参考子电路中电阻器相同的电阻器上，该相同电阻器上产生的电压与来自参考子电路的输入进行比较以产生输出。
按照这个方式，当第一、二组感测单元内边缘单元的数目相同时，边缘单元的影响得到补偿。
在一个特定实施例中，单元为具有栅极、源极和漏极的预定第一导电类型的MOS单元，主单元和感测单元的漏极共同地连接到第一端子，主单元的源极连接到依次与源极电压干线(rail)(Vss)相连的第二端子。
驱动电路可包括第一导电类型的FET，该FET的源极连接到源极电压干线，漏极连接到功率半导体器件的控制端子以及栅驱动电路。
参考子电路可包括第一导电类型的FET，该FET的源极通过电阻连接到源极电压干线，漏极通过电阻连接到逻辑源，栅极连接到漏极并连接到参考子电路的输出，且其中参考子电路的输入连接到参考子电路FET的源极，以把第一感测端子上的电流输出提供给参考子电路。
感测子电路可能包括第一导电类型的FET，该FET的源极通过电阻连接到源极电压干线，漏极通过电阻连接到逻辑源，栅极连接到参考子电路的输出，且其中感测子电路的输入连接到源极，以把第二感测端子上的电流输出提供给感测子电路，用于将该电流与参考子电路设定的值进行比较并输出一个信号至驱动电路。
参考子电路及感测子电路的各个FET与源极电压干线之间的电阻优选为匹配的感测电阻器。
该半导体装置可以提供成包括补偿电路的集成封装。
注意，所描述的特定的补偿电路不是唯一的可能，本领域技术人员将可以以许多其它的方式来实现该相同的功能。例如，可以使用运算放大器。
附图说明
为更好地理解本发明，现在将仅通过举例的方式，参考附图对实施例进行描述，其中：
图1示出了根据本发明的一个Sens eMOS的截面侧视图；
图2示出了根据本发明的一个装置中一组感测单元的第一种配置；
图3示出了根据本发明的一个装置中一组感测单元的第二种配置；
图4示意性示出了根据本发明的一个Sens eMOS的各个端子；
图5示出了根据本发明的一个电路；以及
图6示出了根据本发明的已封装的半导体器件。
应该注意到，示意图不是按比例绘制。此外要注意，相同的部件在不同的图中用相同的参考数字表示。
具体实施方式
参考图1，示出了一个沟道MOS结构的截面图。n+衬底2在其第一主要表面114上形成n-外延层4，在其第二主要表面116上形成漏极接触20。n+衬底2构成了连接到漏极接触20的漏极。
在第一主要表面上延伸的外延层上形成多个单元12，这些单元由填充了多晶硅栅8的绝缘沟道6定义。在每个单元12的沟道6之间形成源区10与p-主体区11。
大部分单元为主单元14，这些单元的源区10和p-主体区11并联地连接到主金属化区22。图1还示出了一组感测单元16--感测单元的源区10和p-主体区11并联地连接到感测金属化区24。
当使用小的单元间距(pitch)时，光刻容差(tolerance)无法留出足够的空间采可靠地接触所有单元的源区10和p-主体区11。因此，在感测单元16与主单元14之间使用了空单元18，这些空单元18没有连接，因此并不像正常单元那样工作。与这些空单元18相邻的单元将称为边缘单元28。
图1示意性示出了该图中器件的电流路径26。空单元18内没有源电流流过，因此相邻的边缘单元28内沿栅8流动的电流更少。这减小了这些单元内的电流集聚效应，并提供了一个阻抗更小的路径。净效应是界面处的边缘单元28所传导的电流与阵列中间的单元传导的电流大不相同，这对感测电流的影响非常显著。如果主单元与感测单元之比很大，该效应将尽其可能地加剧。
图2与图3示出了本发明的实施例中使用的感测单元群的顶视图。图2示出了边缘单元28占50％以上的第一感测单元群30，图3示出了包括边缘单元28和内部感测单元34的第二感测单元群32。
注意，两个感测单元群30、32中的边缘单元的数目相同。
第一实施例的功率半导体器件被封装，如图4示意性示出的封装51示意性所示。在所示的配置中，功率半导体器件具有第一、第二感测单元组30、32，分别并联地连接到相应的第一、第二感测端子40、42。共用的漏极接触20连接到第一主端子44，且第二主端子46连接到主单元16。控制端子48共用地连接到栅极。
图5以实例的方式示出了使用本装置的电路。
第一主端子44连接到负载52。第二主端子46连接到源极电压干线53。
该电路包括参考子电路54，参考子电路54具有连接到第一感测端子40的输入56，并且具有参考输出58。该子电路54依次连接到感测子电路60，感测子电路60的输入62连接到第二感测端子42，控制输入64连接到参考输出58。感测子电路具有输出66。注意，输出和输入仅仅是半导体衬底上的轨道(track)而已。
参考子电路和感测子电路都连接在逻辑源干线68和源极电压干线53之间。
参考子电路54包括n型MOSFET 80，其源极直接连接到输入56，并通过电阻器82连接到源极电压干线53。漏极通过电阻器84连接到逻辑源干线68，并且还连接到随后与输出58相连的栅极。
感测子电路60包括一个n型MOSFET 90，其源极直接连接到输入62，并通过电阻器92连接到源极电压干线53。漏极通过电阻器94连接到逻辑源干线68。栅极连接到输入64，并且因此连接到参考子电路54的输出58。从漏极获得感测子电路的输出66。
电路的其它部分为具有另一个n-MOSFET 96的驱动电路70，该n-MOSFET 96的栅极连接到驱动输入74，因此该栅极依次连接到感测子电路的输出66。漏极通过电阻器98连接到栅极驱动(未示出)。源极连接到源极电压干线53。从漏极获得驱动电路的输出76，且输出76连接到功率晶体管50的输入48。
在工作时，该电路将参考子电路54内n-MOSFET 80的电压与感测子电路60内n-MOSFET 90栅极处的电压进行比较。如果后者过高，则降低驱动电路70的MOSFET 96的栅极电压并因此降低了功率MOSFET 50上的电压，直到建立平衡，因此，该电路作为电流限制电路进行工作。
该电路通过把来自感测端子40的电流注入到参考子电路54内MOSFET 80的源极来补偿边缘效应。这提高了参考子电路54的输出58上的栅极电压，电压的提高量与边缘单元内的电流有关。来自感测端子42的感测电流注入到感测子电路内MOSFET 90的源极，这利用普通单元及边缘单元的贡献升高了其电压。由于第一和第二组的边缘单元数目相同且电阻器82与92相匹配，所以来自边缘单元的电压贡献将抵消。施加到驱动电路上的结果校正信号将只包括内部单元的贡献。
负载电流与感测电流之比不应该随温度大幅变化，因为边缘单元的性能变化将与其它单元的性能变化相同。电阻器82与92由温度系数很低的多晶硅制成。
备选地，本领域技术人员将会了解到，Sens eMOS 50可用作由具有虚接地的运算放大器控制的分立器件。
由于边缘效应得到补偿，在需要使用空单元的Sens eMOS结构中使用更小的单元间距成为可能。这些更小的单元间距反过来产生如下益处：开态(on-state)的比漏源电阻(Rds(on))更低，同时仍可获得精确的负载—感测电流比。
在第二实施例中，图5所示的总体电路除了负载以外均并入到如图5所示封装100的单个器件封装中。
本发明可以用于如图6示意性示出的分立器件。半导体芯片102安装在引线框104上并容纳在封装101中。所示的例子为七引脚封装，其中端子40、42、44、46、48、110、及112通过导线106电学地连接到芯片。在所示器件中，所提供的主单元和感测单元Kelvin端子110、112位于芯片上，并分别连接到主单元14及感测单元16的源极10。这允许对源极10的电压进行更加精确地测量。主端子46上的大量电流输出导致电压降低，因此测得的端子46上的电压并非源极电压的精确度量。使用Kelvin端子110、112测量电压而不提取大量电流减轻了这个问题。
本发明的应用包括要求在大的负载电流、温度、及电源电压范围内非常精确地保持负载和感测电流的应用。
通过阅读本说明书，本发明的其它变型和改变对于本领域技术人员是明显的。这些变型和改变可能涉及在本发明器件的设计、制作、及使用中已知的等效特征或其它特征，而且可以附加使用这些特征或者用这些特征替换这里所公开的特征。尽管在本专利申请中已经明确地表达了这些特征的特定组合，但是应该理解，本公开的范围还包括本说明书所明确或含蓄地公开的任何新特征以及任何特征的新组合或它们的任意概括，无论这些新特征或新组合是否像本发明这样减轻了任何或所有相同的技术难题。因此本申请人预先通告的是，在本专利申请或任何由其衍生的专利申请的执行过程中，可能会对任何这些特征和/或这些特征的组合提出新的权利要求。
特别地，本发明可以用于具有各种形状和配置的沟道单元。本发明并不限于沟道MOSFET，本领域技术人员将会容易地意识到如何以可供选择的基于单元的结构来实现本发明，例如包括侧向MOSFET、其它类型的垂直MOSFET、以及甚至其它结构，
此外，尽管所描述的实施例使用了两组感测单元，而且通常不期望使用太多组的感测单元，但是如果需要时本发明可能包括更多组的感测单元。

Claims (10)

1.一种功率半导体器件，包括：
第一主端子(44)与第二主端子(46)，至少其中之一用于耦合负载(52)；
控制端子(48)；以及
半导体主体(2)，该半导体主体具有相对的第一和第二主要表面(114、116)以及在半导体主体的第一主要表面(114)上排列成网格的多个半导体单元(12)，所述半导体单元(12)分为主单元(14)和感测单元(16)，每个半导体单元具有与控制端子(48)连接的栅极或基极，
其中每个主单元(14)并联地连接在第一和第二主端子(44、46)之间，以在控制端子(48)的控制之下耦合第一和第二主端子(44、46)；
该功率半导体器件还包括第一和第二感测端子(40、42)；
该感测单元分为多组感测单元(30、32)，每组感测单元在网格上排列成一个图形，每组感测单元并联地连接在各个感测端子(40、42)与第一主端子(44)之间；以及
第一组感测单元(30)在网格上排列成一个图形，该图形的边缘单元与内部单元之比不同于第二组感测单元(32)，内部感测单元(34)被该组的其它感测单元包围，且边缘感测单元(28)则排列在该组感测单元的边缘。
2.根据权利要求1的半导体器件，其中第一和第二组感测单元(30、32)内的边缘感测单元(28)数目相同。
3.根据权利要求1的半导体器件，其中半导体单元为MOS单元，所述MOS单元包括源极(10)、漏极(2)、及连接到控制端子的栅极(8)，主单元的源极(10)和漏极(2)连接到第一和第二主端子(44、46)，且一组感测单元(30、32)的源极和漏极(10、2)连接在第二主端子与所述一组感测单元的各自的感测端子(40、42)之间。
4.根据权利要求3的半导体器件，其中半导体单元(12)为沟道MOSFET单元。
5.根据权利要求1至4中任一项的半导体器件，还包括连接到主单元的源极的Kelvin端子。
6.一种半导体装置，包括：
根据权利要求1的半导体器件；
具有输入(74)和输出(76)的驱动电路(70)，输出(76)连接到控制端子(48)用于驱动控制端子；以及
补偿电路，包括参考子电路(54)和感测子电路(60)，所述参考子电路(54)具有直接或间接地连接到第一感测端子(40)的输入(56)，所述感测子电路(60)具有直接或间接地连接到第二感测端子(42)的输入(62)，且补偿电路的输出(66)连接到驱动电路(70)用于控制驱动电路，其中补偿电路基于从第一和第二感测端子(40、42)上的电流获得的内部感测单元(34)中的电流，向驱动电路输入(74)输出一个信号。
7.根据权利要求6的半导体装置，其中：
所述参考子电路(54)的输入(56)连接到与第一组感测单元相连的第一感测端子(40)，并且所述参考子电路(54)提供参考电压的输出(58)，其中来自第一感测端子(40)的电流施加在电阻(82)上，以使参考电压随来自第一组感测单元的电流线性增加；
所述感测子电路(60)的输入(62)连接到与第二组感测单元(32)相连的第二感测端子(42)，其中来自第二组感测单元(32)的电流施加在与参考子电路中的电阻相同的电阻(92)上以产生一个电压；而且
该感测子电路具有一个连接到参考子电路的输出(58)的补偿输入(64)，
该感测子电路可操作地将补偿输入(64)上的电压输入与在所述相同电阻器(92)上产生的电压进行比较以产生输出，该输出提供补偿后的感测电流信号至驱动电路输入(74)，用于控制驱动电路(70)来限制功率半导体器件的电流输出。
8.根据权利要求7的半导体装置，其中：
功率半导体器件含有具有栅极(8)、源极(10)、和漏极(2)的预定第一导电类型的MOS单元，所述MOS单元的栅极(8)并联地连接到控制端子(48)，主单元和感测单元的漏极(2)共同地连接到第一主端子(44)，主单元(14)和感测单元(16)的源极分别连接到第二主端子(46)和感测端子(40、42)；
其中第二主端子(46)连接到源极电压干线(53)(Vss)；
驱动电路(70)包括第一导电类型的FET(96)，驱动电路的FET(96)的源极连接到源极电压干线(53)，其漏极连接到功率半导体器件的控制端子(48)以及栅驱动电路(98)；
参考子电路(54)包括第一导电类型的FET(80)，参考子电路的FET(80)的源极通过电阻(82)连接到源极电压干线(53)，其漏极通过电阻(84)连接到逻辑源(68)，其栅极连接到漏极并连接到参考子电路的输出(58)，且其中参考子电路的输入(56)连接到参考子电路的FET(80)的源极，以把第一感测端子(40)上的电流输出提供给参考子电路(54)；以及
感测子电路(60)包括第一导电类型的FET(90)，感测子电路的FET(90)的源极通过电阻(92)连接到源极电压干线(53)，其漏极通过电阻(94)连接到逻辑源(68)，其栅极连接到参考子电路的输出(58)，且其中感测子电路的输入(62)连接到第二感测端子(42)，以把第二感测端子上的电流输出与参考子电路设定的值进行比较并输出一个信号至驱动电路。
9.一种放置在单独封装(100)内的根据权利要求6至8中任一项的半导体装置。
10.根据权利要求6至8中任一项的半导体装置，其中第一主端子(44)连接到负载(52)。
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