CN100447978C - 在铜晶种沉积后的植入方法 - Google Patents

在铜晶种沉积后的植入方法 Download PDF

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Publication number
CN100447978C
CN100447978C CNB028234413A CN02823441A CN100447978C CN 100447978 C CN100447978 C CN 100447978C CN B028234413 A CNB028234413 A CN B028234413A CN 02823441 A CN02823441 A CN 02823441A CN 100447978 C CN100447978 C CN 100447978C
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layer
barrier
implant
forming
seed
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Expired - Fee Related
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CNB028234413A
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English (en)
Chinese (zh)
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CN1592964A (zh
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S·洛帕京
P·R·贝瑟
M·S·比伊诺斯基
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
CNB028234413A 2001-11-26 2002-10-11 在铜晶种沉积后的植入方法 Expired - Fee Related CN100447978C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/994,358 2001-11-26
US09/994,358 US6703307B2 (en) 2001-11-26 2001-11-26 Method of implantation after copper seed deposition

Publications (2)

Publication Number Publication Date
CN1592964A CN1592964A (zh) 2005-03-09
CN100447978C true CN100447978C (zh) 2008-12-31

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CNB028234413A Expired - Fee Related CN100447978C (zh) 2001-11-26 2002-10-11 在铜晶种沉积后的植入方法

Country Status (7)

Country Link
US (1) US6703307B2 (enExample)
EP (1) EP1449248A2 (enExample)
JP (1) JP4685352B2 (enExample)
KR (1) KR20040064288A (enExample)
CN (1) CN100447978C (enExample)
AU (1) AU2002340177A1 (enExample)
WO (1) WO2003046978A2 (enExample)

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TWI584441B (zh) * 2013-02-26 2017-05-21 旺宏電子股份有限公司 內連線結構及其形成方法

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CN105899003B (zh) 2015-11-06 2019-11-26 武汉光谷创元电子有限公司 单层电路板、多层电路板以及它们的制造方法
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Publication number Publication date
CN1592964A (zh) 2005-03-09
AU2002340177A1 (en) 2003-06-10
JP2005510874A (ja) 2005-04-21
JP4685352B2 (ja) 2011-05-18
US20040023486A1 (en) 2004-02-05
KR20040064288A (ko) 2004-07-16
US6703307B2 (en) 2004-03-09
WO2003046978A2 (en) 2003-06-05
EP1449248A2 (en) 2004-08-25
WO2003046978A3 (en) 2003-10-30

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Address before: American California

Patentee before: Advanced Micro Devices Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20081231

Termination date: 20161011