CN100447748C - Interrupt system realizing method - Google Patents
Interrupt system realizing method Download PDFInfo
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- CN100447748C CN100447748C CNB2005100292833A CN200510029283A CN100447748C CN 100447748 C CN100447748 C CN 100447748C CN B2005100292833 A CNB2005100292833 A CN B2005100292833A CN 200510029283 A CN200510029283 A CN 200510029283A CN 100447748 C CN100447748 C CN 100447748C
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Abstract
The present invention relates to an interruption system realizing method which comprises following steps that after an interruption module accepts an interruption request, the present invention judges whether the request simultaneously satisfies interruption permission and interruption effective permission or not; if the request simultaneously satisfies the interruption permission and the interruption effective permission, the interruption request is converted to interruption response; the system is interrupted, or the interruption response is not generated. Through the method of the present invention, the judgment of an interruption source is clearer, and by using a software method, interruption priority is processed, so written program is simpler and more understandable. A part of interruption response can activate a microcontroller in an idle mode and enters a normal working mode.
Description
Technical field
The invention belongs to the integrated circuit (IC) design technical field, be specifically related to a kind of interrupt system implementation method of microcontroller.
Background technology
Along with the continuous progress of deep-submicron CMOS integrated circuit production technology, can be integrated in the microcontroller of complexity (MCU) kernel on the chip piece at present, leave enough silicon area simultaneously and be used to realize complicated storer and peripheral hardware logic.The method for designing and the framework that are used for high-end 32 and 64 bit CPUs in the past can effectively be used for 8 8-digit microcontroller systems at a low price now.Utilize these powerful and cheap microcontrollers to make the integrated level of system improve constantly, also strengthened the ability that microprocessor data is handled and flow process is controlled simultaneously greatly.In the process of microprocessor system handling procedure flow process control, interrupt system is being played the part of more and more important role.Interrupt system be microprocessor in the normal process of operating software, insert other processing subroutine, it has than higher priority in program circuit control.
In recent years, the design of the interrupt system of microcontroller has obtained to popularize widely.Though realize that now the method for interrupt system is a lot, shield the design that the method for designing of interrupting forbids shielding interruption such as adopting, adopting the method for designing of an interrupt address still is method for designing of a plurality of interrupt vectors or the like.
A lot of companies are all at the microcontroller of producing the band interrupt system, as Microchip, Motorola, Toshiba, NEC, Hitachi, Atmel, Holtek etc.Though the part microcontroller products of these companies all possesses interrupt system, but interrupt type, the Interrupt Process mode of most of products are more single in the middle of these products, interrupting the source judges unclear, causing interrupt response not handled well optimizes, making does not have well to bring into play the resource of interrupt system aspect Industry Control, grasp these interrupt systems to the CLP AD simultaneously and bring difficulty.
Summary of the invention
The object of the present invention is to provide a kind of interrupt system implementation method, make that the judgement of interrupting the source is more clear.
Another object of the present invention is to select interrupt vector number and interrupt vector table flexibly, realize the processing of interrupt priority level by the method for software by interrupt system implementation method provided by the present invention.
Further purpose of the present invention is and the microcontroller that is in idle pulley can be activated, enters normal mode of operation.
The present invention is achieved in that interrupt system implementation method provided by the invention comprises the steps:
Described interrupt module accepts to judge after the interrupt request whether this request is satisfied simultaneously interrupts allowing and interrupt effectively allowing, if, converting interrupt request to interrupt response, system enters interruption, otherwise, do not produce interrupt response;
Wherein, described interruption allows to interrupt the related register realization by being provided with, and it is that corresponding interruption permission and interrupt request is effectively that described interruption effectively allows.
Described interrupt request comprises internal interrupt request, external interrupt request and soft interrupt request.
When described interrupt request was the external interrupt request, described interruption allowed to be meant that the peripheral interruption of interrupting permission and this external interrupt request correspondence allows.
The interruption of described this external interrupt request correspondence allows to comprise that external timer interrupts allowing, and seizure/comparison/width modulation is interrupted allowing, and communication port interrupts allowing, and mould/number conversion is interrupted allowing.
When described interrupt request was the internal interrupt request, the interruption that described interruption allows to be meant this internal interrupt request correspondence allowed.
The interruption of described this internal interrupt request correspondence allows to comprise that port changes interruption and allows, and port interrupts allowing along triggering, and the timer internal interruption allows.
When described interrupt request was soft interrupt request, described interruption allowed to be meant that software interruption allows.
Described external interrupt request comprises that external timer interrupt request, seizure/comparison/width modulation interrupt request, communication port interrupt or mould/number conversion interrupt request.
Described internal interrupt request comprises that the port level changes interrupt request, port along triggering interrupt request or timer internal interrupt request.
Set in advance interrupt vector number and interrupt vector table, interrupt type is classified according to interrupt vector table.
After described interrupt module is accepted interrupt request, judge its realization priority of interrupt according to the type of this interrupt request earlier, and carry out the processing of interrupt priority level.
Under the pattern of a plurality of interrupt vectors, soft interrupt priority level is the highest.
The processing of described interrupt priority level realizes by software approach.
The present invention utilizes to satisfy interrupts the microcontroller activation that condition for validity will be operated in idle pulley.
System carries out the IDLE instruction and enters idle pulley, when the interruption module receives interrupt request, judges whether this request is satisfied the interruption of its correspondence simultaneously and allowed, if, activate idle pulley, enter normal mode; Judge then and interrupt effectively whether allowing, in this way, then enter interruption subroutine, continue to carry out otherwise return master routine.
Have no progeny during system enters protecting breakpoint automatically, carry out the PC pop down, withdraw from when interrupting, will recover on-the-spot, carry out PC automatically and pop.
As can be seen, comprise in the implementation method of interrupt system of the present invention and interrupt permission, interrupt request, interruption effectively and four kinds of operations of interrupt response, make that the judgement of interrupting the source is more clear.Part interrupts effectively the microcontroller that is in idle pulley to be activated, and enters normal mode of operation.And interrupt system of the present invention is based on and designs on each functional module of microcontroller, and three kinds of different interrupt types are arranged: internal interrupt, external interrupt and software interruption make that the resource of interrupting is abundanter.Can select interrupt vector number and interrupt vector table by being provided with of microcontroller register in the present invention, the method by software realizes the processing of interrupt priority level, makes coding be easily understood more.Interrupt source of the present invention, interrupt vector number and interrupt vector table number can be expanded, and possess good extensibility.The present invention adopts the method for designing of software-hardware synergism, at hardware aspect, in conjunction with the functional module of microcontroller, reasonably divides interrupt type, arranges interrupt vector cleverly, fast the interrupt response judgment processing; Aspect software, the method handling interrupt priority by software realizes the high performance interrupt system of relative high-level efficiency.
Description of drawings
Fig. 1 is an interrupt resources type synoptic diagram of the present invention;
Fig. 2 is that timer internal of the present invention interrupts the embodiment schematic flow sheet;
Fig. 3 is that external timer of the present invention interrupts the embodiment schematic flow sheet;
Fig. 4 is a soft interruption embodiment schematic flow sheet of the present invention;
Fig. 5 is an interrupt enable idle pulley embodiment schematic flow sheet of the present invention.
Embodiment
Method of the present invention, its core concept is to comprise the steps: that described interrupt module accepts to judge after the interrupt request whether this request is satisfied simultaneously interrupts allowing and interrupt effectively allowing, if, convert interrupt request to interrupt response, system enters interruption, otherwise, do not produce interrupt response.
Now in conjunction with the accompanying drawings, the specific embodiment of the present invention is described in further detail.
As shown in Figure 1, interrupt resources type of the present invention comprises internal interrupt, external interrupt and software interruption.Described internal interrupt is meant the functional module interruption that the central processing unit CPU of microcontroller inside is interior, external interrupt is that the CPU functional module in addition of microcontroller is interrupted, software interruption is the software interruption that the CPU internal register is set, it need not the special triggered time of hardware circuit, and only needs to realize interrupting by software control.Wherein, internal interrupt can comprise that the port level changes interruption, port interrupts and the timer internal interruption along triggering; External interrupt can comprise external timer interruption, seizure/comparison/width modulation interruption, communication port interrupts and mould/number conversion is interrupted; Described soft interruption is to enable to realize by soft interruption is set.The dissimilar Interrupt Process of forming by internal interrupt, peripheral interruption and software interruption can be formed among the present invention, interrupt vector number and interrupt vector table and type can be selected to be provided with.Can select to be provided with one or more interrupt vectors in the present invention, when selecting an interrupt vector, only there is a kind of interrupt vector table to select, when selecting a plurality of interrupt vector is set, just can there be a plurality of interrupt vector tables to select, interrupt type be classified by interrupt vector table.When receiving an interrupt request, judge the priority of this interrupt request according to the type of interrupt request, under a plurality of interrupt vector patterns, soft priority of interrupt is the highest.
Interrupt system implementation method of the present invention comprises interruption permission, interrupt request, interruption is effective and four kinds of interrupt operations of interrupt response; Wherein, interrupt related register realization interruption permission, by corresponding interrupt identification related register takes place or interrupts the realization interrupt request is set by being provided with.Interrupt realizing effectively being meant that corresponding interruption permission and interrupt request are effectively, for example for external interrupt, external interrupt allows also to need to enable, and can realize interrupting effectively.When interrupting effectively allowing and interrupt under effective situation about satisfying simultaneously, system just can enter interrupt response.
Timer internal as shown in Figure 2 interrupts synoptic diagram, and its interrupt type belongs to internal interrupt, further belongs to the situation that timer internal interrupts.At first, inner timer work is set, timer internal begins counting, and when the numerical value of counting during to maximal value, timer will change to zero from maximal value, and this moment, timer was to a counting of interrupt module output overflow indicator position, i.e. an interrupt request singal.Interrupt module judges whether that interruption effectively allows to enable and timer internal interrupts allowing to enable, if interrupt module converts this interrupt request to effective interrupt response and enters interruption; Otherwise, do not produce interrupt response.Other internal interrupt types are the sign differences that produces interrupt request with the difference of present embodiment, whether is to have the sign of rising edge or negative edge to ask to trigger by detection port as port along triggering interruption, the port level interrupt be detection port whether vicissitudinous sign triggers, and whether the timer down trigger in the present embodiment is to overflow and trigger by detecting timer.Internal interrupt all needs to cooperate each self-corresponding interruption to allow to enable and interrupts effectively allowing to enable, and its interrupt request could be converted to effective interrupt response, otherwise will not produce interrupt response.Such as, port needs effective port of its correspondence of cooperation to interrupt permission along triggering along triggering interruption, and the port level changes interruption needs to cooperate effective port level variation of its correspondence to interrupt permission.
If external interrupt is effective, then peripheral interruption allows also to be necessary for effectively, otherwise it is effective not to be regarded as external interrupt.As shown in Figure 3, be example with the external timer interruption, this external timer is assumed to be 16.At first need 16 inner bit timing device work are set, and begin counting; When counting up to FFFH, timer will change from FFFFH to 0000H, and timer module will be sent a counting overflow indicator position this moment, and it is exactly interrupt request singal that this zone bit enters interrupt module.Interrupt module judges whether that interruption effectively allows to enable, peripheral interruption allows to enable and external definition is interrupted allowing to enable, if interrupt module converts this interrupt request to effective interrupt response and enters interruption; Otherwise, do not produce interrupt response.Other external interrupt types are the sign differences that produces interrupt request with the difference of present embodiment, as communication port down trigger or other triggering modes.All types of external interrupt requests all needs to cooperate separately interruption to allow to enable, external interrupt allows to enable and interrupt effectively allowing to enable its interrupt request to be converted to effective interrupt response, otherwise, do not produce interrupt response.For example, interrupt needing to cooperate that seizures/comparison/width modulation interruption allows to enable, external interrupt allows to enable and interrupt effectively allowing to enable corresponding to seizure/comparison/width modulation.
As Fig. 4 is soft interruption synoptic diagram of the present invention.At first, soft down trigger condition is set, promptly soft interruption enables; Soft interrupt request mode then is set.When soft down trigger condition was set up, the soft interrupt request that transmission sets in advance was to interrupt module.Whether interrupt module judges to interrupt effectively allowing whether to enable, reach software interruption and allow to enable, if enable, then produces interrupt response, enters interruption; Otherwise, do not produce interrupt response.
Corresponding above-mentioned each interruption all has an interrupt service routine, and the entry address of this interrupt service routine is called interrupt vector.The present invention can be provided with an interrupt vector, also a plurality of interrupt vectors can be set.When an interrupt vector is set, only there is a kind of interrupt vector table to select; When selecting a plurality of interrupt vector is set, there are a plurality of interrupt vector tables to select, can classify to interrupt type by interrupt vector table.The user can select best a kind of interruption implementation according to different application.Can also select to be provided with interrupt vector number and interrupt vector table and type in the present invention, realize the processing of interrupt priority level by software approach.When interrupting after module receives interrupt request, decide the processing of interrupt priority level by the type of judging interrupt request, under the pattern of a plurality of interrupt vectors, soft priority of interrupt can be set to the highest.
In the above-described embodiments, when system enters interruption, will protect breakpoint automatically, promptly enter the PC pop down automatically, and withdraw from interruption and will recover on-the-spot, and promptly carry out PC automatically and pop.
According to method of the present invention, part interrupt response can activate the microcontroller that is in idle pulley, enter normal mode of operation, be that described part interrupts activating the microcontroller that is operated in idle pulley, promptly enter the pattern that stops the major clock low-power consumption, make microcontroller enter normal mode of operation.Be illustrated in figure 5 as the port level and change interrupt enable idle pulley embodiment schematic flow sheet.At first set in advance, the variation of port level is set earlier interrupts allowing to enable.Whether select then to be provided with to interrupt effectively allowing to enable: if need to enter interruption subroutine after activating, be provided with interruption and effectively allow to enable this moment; Continue to carry out if need to return master routine after activating, be provided with interruption and effectively allow not enable this moment.System carries out idle mode instruction IDLE, makes calling program enter idle pulley, and waits for that port changes.When detecting port when changing, this port is changed as effective interrupt request once, and because having set in advance the port level changes and interrupt allowing to enable, so satisfy the effective condition of interruption, the activation idle pulley enters normal mode of operation.After entering normal mode of operation, interrupt system will judge to interrupt effectively allowing whether to enable, if enable, program enters interruption subroutine, promptly from corresponding interruption inlet beginning executive routine, if do not enable, program enters master routine, continues to carry out the following program of IDLE.The above-mentioned interrupt request that can activate idle pulley can also be that port is along triggering interruption or communication port interruption etc.
Claims (16)
1, a kind of interrupt system implementation method is characterized in that, comprises the steps:
Interrupt module accepts to judge after the interrupt request whether this request is satisfied simultaneously interrupts allowing and interrupt effectively allowing, if, converting interrupt request to interrupt response, system enters interruption, otherwise, do not produce interrupt response;
Wherein, described interruption allows to interrupt the related register realization by being provided with, and it is that corresponding interruption permission and interrupt request is effectively that described interruption effectively allows.
2, the method for claim 1 is characterized in that: described interrupt request comprises internal interrupt request, external interrupt request and soft interrupt request.
3, method as claimed in claim 2 is characterized in that: when described interrupt request was the external interrupt request, described interruption allowed to be meant that the peripheral interruption of interrupting permission and this external interrupt request correspondence allows.
4, method as claimed in claim 3 is characterized in that: the interruption of described this external interrupt request correspondence allows to comprise that external timer interrupts allowing, and seizure/comparison/width modulation is interrupted allowing, and communication port interrupts allowing, and mould/number conversion is interrupted allowing.
5, method as claimed in claim 2 is characterized in that, when described interrupt request was the internal interrupt request, the interruption that described interruption allows to be meant this internal interrupt request correspondence allowed.
6, method as claimed in claim 5 is characterized in that: the interruption of described this internal interrupt request correspondence allows to comprise that port changes interruption and allows, and port interrupts allowing along triggering, and the timer internal interruption allows.
7, method as claimed in claim 2 is characterized in that, when described interrupt request was soft interrupt request, described interruption allowed to be meant that software interruption allows.
8, method as claimed in claim 3 is characterized in that, described external interrupt request comprises that external timer interrupt request, seizure/comparison/width modulation interrupt request, communication port interrupt or mould/number conversion interrupt request.
9, method as claimed in claim 3 is characterized in that, described internal interrupt request comprises that the port level changes interrupt request, port along triggering interrupt request or timer internal interrupt request.
10, the method for claim 1 is characterized in that, sets in advance interrupt vector number and interrupt vector table, according to interrupt vector table interrupt type is classified.
11, method as claimed in claim 8 is characterized in that, judges its realization priority of interrupt according to the type of this interrupt request earlier after described interrupt module is accepted interrupt request, and carries out the processing of interrupt priority level.
12, method as claimed in claim 8 is characterized in that, under the pattern of a plurality of interrupt vectors, soft interrupt priority level is the highest.
13, method as claimed in claim 9 is characterized in that, the processing of described interrupt priority level realizes by software approach.
14, the method for claim 1 is characterized in that, utilizes to satisfy to interrupt the microcontroller activation that condition for validity will be operated in idle pulley.
15, method as claimed in claim 12 is characterized in that, system carries out the IDLE instruction and enters idle pulley, when the interruption module receives interrupt request, judge whether this request is satisfied the interruption of its correspondence simultaneously and allowed, if, activate idle pulley, enter normal mode; Judge whether to interrupt effective permission then, if, then enter interruption subroutine, continue to carry out otherwise return master routine.
16, the method for claim 1 is characterized in that, has no progeny during system enters protecting breakpoint automatically, carries out the PC pop down, withdraws from when interrupting, and will recover on-the-spot, carries out PC automatically and pops.
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| CNB2005100292833A CN100447748C (en) | 2005-08-31 | 2005-08-31 | Interrupt system realizing method |
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| CNB2005100292833A CN100447748C (en) | 2005-08-31 | 2005-08-31 | Interrupt system realizing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| GB2454885B (en) * | 2007-11-21 | 2012-06-06 | Advanced Risc Mach Ltd | Interrupt jitter suppression |
| CN101373443B (en) * | 2008-09-23 | 2012-11-28 | 北京中星微电子有限公司 | Method for responding and stopping response of host computer and processing peripheral interrupt |
| CN102547178A (en) * | 2010-12-08 | 2012-07-04 | 中国科学院声学研究所 | Dynamic adjusting method of kernel module driven by application |
| CN104123179A (en) * | 2013-04-29 | 2014-10-29 | 敦南科技股份有限公司 | Method of interrupt control and electronic system using the same |
| CN110554979A (en) * | 2018-05-31 | 2019-12-10 | 瑞昱半导体股份有限公司 | time-piece device and method for operating same |
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| CN1294707A (en) * | 1998-01-21 | 2001-05-09 | 英特尔公司 | Method and appts. for handling multiple level-triggered and edge-triggered interrupts |
| US20010032286A1 (en) * | 1997-12-23 | 2001-10-18 | Pawlowski Stephen S. | Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals |
| US6704863B1 (en) * | 2000-06-14 | 2004-03-09 | Cypress Semiconductor Corp. | Low-latency DMA handling in pipelined processors |
| CN1484158A (en) * | 2002-09-16 | 2004-03-24 | 华为技术有限公司 | Method for realizing interrupt request preprocessing |
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2005
- 2005-08-31 CN CNB2005100292833A patent/CN100447748C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20010032286A1 (en) * | 1997-12-23 | 2001-10-18 | Pawlowski Stephen S. | Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals |
| CN1294707A (en) * | 1998-01-21 | 2001-05-09 | 英特尔公司 | Method and appts. for handling multiple level-triggered and edge-triggered interrupts |
| US6704863B1 (en) * | 2000-06-14 | 2004-03-09 | Cypress Semiconductor Corp. | Low-latency DMA handling in pipelined processors |
| CN1484158A (en) * | 2002-09-16 | 2004-03-24 | 华为技术有限公司 | Method for realizing interrupt request preprocessing |
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