CN100442261C - Interrupt signal control system and control method - Google Patents
Interrupt signal control system and control method Download PDFInfo
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- CN100442261C CN100442261C CNB2003101180959A CN200310118095A CN100442261C CN 100442261 C CN100442261 C CN 100442261C CN B2003101180959 A CNB2003101180959 A CN B2003101180959A CN 200310118095 A CN200310118095 A CN 200310118095A CN 100442261 C CN100442261 C CN 100442261C
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Abstract
The present invention relates to an interrupt signal control system and a control method, which is set and used in a computer system. The computer system has a central processing unit, a north bridge chip, a south bridge chip, a first peripheral device and a second peripheral device; the interrupt signal control system comprises a first output-input interrupt control device, a second output-input interrupt control device and an interrupt state indication route. In the interrupt signal control method, according to the triggering of a first interrupt signal sent by the first peripheral device which is electrically connected with the south bridge chip, a wake up signal is generated to the south bridge chip; accordingly, the south bridge chip releases the electricity saving state of the central processing unit; according to the triggering of a second interrupt signal sent by the second peripheral device which is electrically connected to the north bridge chip, interrupt state indication information is generated; through the interrupt state indication route, the interrupt state indication information is transmitted to the south bridge chip; accordingly, the south bridge chip releases the electricity saving state of the central processing unit.
Description
Technical field
The present invention relates to a kind of look-at-me control system and control method, especially be provided with and be applied to look-at-me control system and control method in the computer system.
Background technology
Electricity-saving mechanism is quite extensive in the utilization of computer system, be applied to battery saving mode on the central processing unit (CPU) and then be divided into considerable level and kind (advanced configuration and electricity interface (Advanced Configuration and Power Interface for example, abbreviation ACPI) defined C 1, C2 and C3 isotype in the specification), but its purpose is nothing more than being in order to the minimizing energy resource consumption and providing lower temperature stable circuit operation environment.And under general structure, (see also conventional computer system architecture synoptic diagram shown in Figure 1), the central processing unit of computer system (CPU) 1 is by 2 management of the South Bridge chip in the chipset (South Bridge is called for short SB) by the mechanism that returns to normal operation in the battery saving mode.Following steps are to illustrate simply how central processing unit (CPU) 1 in the computer system enters C2 or C3 battery saving mode and recover the step of operate as normal again by C2 or C3 battery saving mode as follows:
1. the operating system (Operating System is called for short OS) of working as computer system is in the time of will entering battery saving mode, and central processing unit 1 is just issued a power-saving mode instruction (Sleep Command) to South Bridge chip 2.
2. when stopping clock control module (STPCLK control module) 20 and receive this power-saving mode instruction in the South Bridge chip 2, produce (assert) immediately and stop clock signal (STPCLK#) and stop clock signal pin 21 passing to central processing unit 1 by one.
3. when this stops clock signal (STPCLK#) generation, central processing unit 1 just transmits a suspension of licence special instruction (STPGNT) to South Bridge chip 2 by the data bus of 2 of central processing unit 1, north bridge chips (North Bridge is called for short NB) 3 and South Bridge chips.
4. when South Bridge chip 2 received this suspension of licence special instruction (STPGNT), central processing unit 1 will all enter into battery saving mode together with whole computer system.
5. when first peripheral unit 4 sends look-at-me (interrupt) to South Bridge chip 2 by a look-at-me pin 40, it is to be received by the interrupt control device in the South Bridge chip 2 22, sends a wake-up signal by interrupt control device 22 again and stops clock control module (STPCLK control module) 20 and stop clock signal (STPCLK#) with what remove that (de-assert) produced to trigger this.
6. work as this clock signal (STPCLK#) that stops that stopping on the clock signal pin 21 and be disengaged, central processing unit 1 just can return to normal mode of operation from battery saving mode together with whole computer system.
But for continuous increase and elevator system overall efficiency according to the peripheral unit number, the design of Computer Systems Organization constantly produces change.See also shown in Figure 2, it has a plurality of outputs and imports advanced programmable interrupt controller (Input Output Advanced Programmable Interrupt Controller, abbreviation IOAPIC) future generation computer system structural representation, it more sets up the bridge-set that links bus bridge device (PCI to PCIBridge) 5 as the computing machine periphery with different being in of general Computer Systems Organization commonly used on north bridge chips 3, use to connect newly-increased peripheral unit (second peripheral unit 6 as shown in FIG.) and improve system effectiveness.And wherein advanced programmable interrupt controller (IOAPIC) the 25th is imported in first output, is arranged in South Bridge chip 2, and the computing machine periphery that is arranged at as shown in the figure as for the advanced programmable interrupt controller of the second output input (IOAPIC) 50 links in the bridge-set of bus bridge device (PCI to PCIBridge) 5.
Therefore, when central processing unit 1 is in the battery saving mode of C2 or C3 and first peripheral unit 4 when sending look-at-me (interrupt) to South Bridge chip 2 by a look-at-me pin 40, the advanced programmable interrupt controller of in the South Bridge chip 2 first output input (IO APIC) 25 just receives this look-at-me and sends a wake-up signal and stops clock control module (STPCLK control module) 20 and stop clock signal (STPCLK#) with what remove that (de-assert) produced to trigger this, this first output advanced programmable interrupt controller of input (IO APIC) 25 is also sent information signal interruption (message signaled interrupt simultaneously, be called for short MSI), and writing the interrupting information (interrupt message) that instruction (memory write cycle) kenel exists with internal memory, this interrupting information is again by South Bridge chip 2, the data bus that north bridge chips 3 and central processing unit are 1 is sent to central processing unit 1.
But, when central processing unit 1 is in the battery saving mode of C2 or C3 and second peripheral unit 6 when sending a look-at-me (interrupt) and link bus bridge device (PCI to PCI Bridge) 5 to the computing machine periphery by a look-at-me pin 60, the second output advanced programmable interrupt controller of input (IO APIC) 50 in the computing machine periphery binding bus bridge device (PCI to PCI Bridge) 5 also can be sent information signal interruption (message signaled interrupt after receiving this look-at-me, be called for short MSI), and write the interrupting information (interrupt message) that instruction (memory write cycle) kenel exists with internal memory, but because the destination of this interrupting information is all central processing unit 1, therefore this this interrupting information only just is sent to central processing unit 1 by the data bus of 1 of north bridge chips 3 and central processing unit, triggers this and stops clock control module (STPCLK control module) 20 and stop clock signal (STPCLK#) with what remove that (de-assert) produced and can't be passed to South Bridge chip 2.Therefore under this system state of new generation, be connected the computing machine periphery and link second peripheral unit 6 on the bus bridge device (PCI to PCI Bridge) 5 and can't effectively computer system be waken up by battery saving mode and return to normal mode of operation.And how effectively solve the problem of above conventional means, be fundamental purpose of the present invention.
Summary of the invention
The present invention relates to a kind of look-at-me control system, be arranged in the computer system, this computer system has a central processing unit, one north bridge chips, one South Bridge chip, one first peripheral unit and one second peripheral unit, and this look-at-me control system comprises: one first output input interrupt control device, be electrically connected on this first peripheral unit and this South Bridge chip, its triggering according to one first look-at-me that this first peripheral unit is sent produces a wake-up signal to this South Bridge chip, and then makes this South Bridge chip remove the power down mode of this central processing unit; One second output input interrupt control device is electrically connected on this second peripheral unit and this north bridge chips, and its triggering according to one second look-at-me that this second peripheral unit is sent produces an interruption status indication information; An and interruption status indication path, signal is connected between this second output input interrupt control device and this South Bridge chip, it is in order to this interruption status indication information is sent to this South Bridge chip, and then makes this South Bridge chip can remove the power down mode of this central processing unit.
According to above-mentioned conception, look-at-me control system of the present invention, wherein this first output input interrupt control device is to be integrated in this South Bridge chip.
According to above-mentioned conception, look-at-me control system of the present invention, wherein have one in this South Bridge chip and stop clock control module, this stops clock control module and stops the clock signal pin by one and be electrically connected to this central processing unit, and then utilizes this to stop one on the clock signal pin to stop Generation of Clock Signal or remove and carry out the switching of this central processing unit power down mode.
According to above-mentioned conception, look-at-me control system of the present invention, wherein this interruption status indication path is an interruption status indication pin, be electrically connected on this second output input interrupt control device and this stops between the clock control module, it stops clock control module in order to this interruption status indication information is sent to this, and then can remove this and stop on the clock signal pin this and stop clock signal.
According to above-mentioned conception, look-at-me control system of the present invention, wherein this second output input interrupt control device is to be integrated in the bus bridge device, this bus bridge device is to be electrically connected between this second peripheral unit and this north bridge chips.
According to above-mentioned conception, look-at-me control system of the present invention, wherein this interruption status indication path is made of one first data bus between this bus bridge device and this north bridge chips and one second data bus between this north bridge chips and this South Bridge chip, it stops clock control module in order to this interruption status indication information is sent to this, and then can remove this and stop on the clock signal pin this and stop clock signal.
According to above-mentioned conception, look-at-me control system of the present invention, wherein this bus bridge device is that computing machine periphery links the bus bridge device.
According to above-mentioned conception, look-at-me control system of the present invention, wherein these output input interrupt control devices are to finish with the advanced programmable interrupt controller of output input.
Another aspect of the invention is a kind of look-at-me control method, be applied in the computer system, this computer system has a central processing unit, a north bridge chips, a South Bridge chip, one first peripheral unit and one second peripheral unit, and this look-at-me control method comprises the following step: the triggering of one first look-at-me of being sent according to this first peripheral unit that is electrically connected on this South Bridge chip produces a wake-up signal to this South Bridge chip, and then makes this South Bridge chip remove the power down mode of this central processing unit; The triggering of one second look-at-me of being sent according to this second peripheral unit that is electrically connected on this north bridge chips produces an interruption status indication information; And, this interruption status indication information is sent to this South Bridge chip, and then makes this South Bridge chip can remove the power down mode of this central processing unit by interruption status indication path.
According to above-mentioned conception, look-at-me control method of the present invention, wherein this wake-up signal is produced according to this first look-at-me by the one first output input interrupt control device that comprises on this South Bridge chip.
According to above-mentioned conception, look-at-me control method of the present invention, wherein this interruption status indication information is produced according to this second look-at-me by the one second output input interrupt control device that comprises in this computer system.
According to above-mentioned conception, look-at-me control method of the present invention, wherein these look-at-mes be an information signal interrupt (message signaled interrupt, MSI).
The present invention is able to more deep understanding by following accompanying drawing and detailed description:
Description of drawings
Fig. 1: be common computer system architecture synoptic diagram.
Fig. 2: be to have the Computer Systems Organization synoptic diagram that advanced programmable interrupt controller is imported in a plurality of outputs.
Fig. 3: be that the present invention is the preferred embodiment function block diagram that the public defective of improvement develops out.
Fig. 4: be that the present invention is the preferred embodiment function block diagram that the public defective of improvement develops out.
Wherein, description of reference numerals is as follows:
1 central processing unit (CPU), 2 South Bridge chips
20 stop clock control module 21 stops the clock signal pin
3 north bridge chips, 22 interrupt control devices
4 first peripheral units, 40 look-at-me pins
5 computer externals link bus bridge device 6 second peripheral units
25 first output input advanced programmable interrupt controller (IO APIC)
50 second output input advanced programmable interrupt controller (IO APIC)
501 interruption statuss indication pin, 30 first data buss
31 second data buss
Embodiment
See also Fig. 3, be that the present invention is the preferred embodiment function block diagram that improvement defective commonly used is put forward, the present invention is mainly a kind of look-at-me control system, it can be arranged in the computer system, and this computer system has central processing unit 1 as shown in FIG., north bridge chips 3, South Bridge chip 2, one first peripheral unit 4 and one second peripheral unit 6, and look-at-me control system of the present invention consists predominantly of the first output advanced programmable interrupt controller of input (IO APIC) 25, the second output input advanced programmable interrupt controller (IO APIC), 50 and one interruption status indication pin 501.
Thus, when central processing unit 1 is in the battery saving mode of C2 or C3 and second peripheral unit 6 when sending this look-at-me (interrupt) and link bus bridge device (PCI to PCI Bridge) 5 to the computing machine periphery by this look-at-me pin 60, after the second output advanced programmable interrupt controller of input (IO APIC) 50 in the computing machine periphery binding bus bridge device (PCI to PCIBridge) 5 receives this look-at-me, interrupt (message signaled interrupt except sending information signal equally, be called for short MSI), be sent to central processing unit 1 and write the interrupting information (interruptmessage) that instruction (memory write cycle) kenel exists with internal memory, this interruption status indication pin 501 that also can utilize the present invention to set up sends state indication, in order to notifying in this South Bridge chip 2 this to stop clock control module (STPCLKcontrol module) 20, so trigger that this stops that clock control module (STPCLK control module) 20 removes that (de-assert) produced stop clock signal (STPCLK#).Therefore, in preferred embodiment of the present invention, even be connected second peripheral unit 6 on the computing machine periphery binding bus bridge device (PCI to PCI Bridge) 5, still can be effectively central processing unit and computer system be waken up by battery saving mode and return to normal mode of operation, and then can solve the problem of conventional means effectively, reach fundamental purpose of the present invention.Interruption status indication information as for this interruption status indication pin 501 can represent by following example that look-at-me is not received in low-voltage accurate position representative, and look-at-me is received in the accurate position of high voltage then representative.
And for avoiding increasing pin, the present invention also can use one second data bus 31 that this computer external links 2 of one first data bus 30 of bus bridge device 5 and 3 of this north bridge chips and this north bridge chips 3 and this South Bridge chips instead and constitute this interruption status and indicate path (another preferred embodiment function block diagram as shown in Figure 4), it is to be sent to this in the mode of an information by bus in order to this interruption status indication that the advanced programmable interrupt controller of the second output input (IOAPIC) 50 is produced to stop clock control module 20, so remove (de-assert) this stop that clock control module 20 produced stop clock signal (STPCLK#).
In sum, the present invention is under this system state of new generation, still can effectively utilize and be connected computing machine periphery and link second peripheral unit 6 on the bus bridge device 5 and computer system is waken up by battery saving mode returned to normal mode of operation, successfully solve the problem of above conventional means, reach fundamental purpose of the present invention.The present invention does not break away from equivalence change or the modification of finishing under the disclosed spirit by being familiar with this technician, all should be included in the claim.
Claims (10)
1. a look-at-me control system is arranged in the computer system, and this computer system has a central processing unit, a north bridge chips, a South Bridge chip, one first peripheral unit and one second peripheral unit, and wherein this look-at-me control system comprises:
One first output input interrupt control device, be electrically connected on this first peripheral unit and this South Bridge chip, its triggering according to one first look-at-me that this first peripheral unit is sent produces a wake-up signal to this South Bridge chip, and then makes this South Bridge chip remove the power down mode of this central processing unit;
One second output input interrupt control device is electrically connected on this second peripheral unit and this north bridge chips, and its triggering according to one second look-at-me that this second peripheral unit is sent produces an interruption status indication information; And
One interruption status indication path, signal is connected between this second output input interrupt control device and this South Bridge chip, it is in order to this interruption status indication information is sent to this South Bridge chip, and then makes this South Bridge chip can remove the power down mode of this central processing unit.
2. look-at-me control system as claimed in claim 1, wherein this first output input interrupt control device is to be integrated in this South Bridge chip.
3. look-at-me control system as claimed in claim 1, wherein be to have one to stop clock control module in this South Bridge chip, this stops clock control module and stops the clock signal pin by one and be electrically connected to this central processing unit, and then utilize this to stop one on the clock signal pin to stop Generation of Clock Signal or remove and to carry out the switching of this central processing unit power down mode, and this interruption status indication path is an interruption status indication pin, be electrically connected on this second output input interrupt control device and this stops between the clock control module, it is to stop clock control module in order to this interruption status indication information is sent to this, and then can remove this and stop on the clock signal pin this and stop clock signal.
4. look-at-me control system as claimed in claim 1, wherein be to have one to stop clock control module in this South Bridge chip, this stops clock control module and stops the clock signal pin by one and be electrically connected to this central processing unit, and then utilize this to stop one on the clock signal pin to stop Generation of Clock Signal or remove and to carry out the switching of this central processing unit power down mode, and this second output input interrupt control device is to be integrated in the bus bridge device, this bus bridge device is to be electrically connected between this second peripheral unit and this north bridge chips, and this interruption status indication path is made of one first data bus between this bus bridge device and this north bridge chips and one second data bus between this north bridge chips and this South Bridge chip, it is to stop clock control module in order to this interruption status indication information is sent to this, and then can remove this and stop on the clock signal pin this and stop clock signal.
5. look-at-me control system as claimed in claim 4, wherein this bus bridge device is that a computer external links the bus bridge device.
6. look-at-me control system as claimed in claim 1, wherein these output input interrupt control devices are to finish with the advanced programmable interrupt controller of output input.
7. look-at-me control method, be applied in the computer system, this computer system has a central processing unit, a north bridge chips, a South Bridge chip, one first peripheral unit and one second peripheral unit, and this look-at-me control method comprises the following step:
The triggering of one first look-at-me of being sent according to this first peripheral unit that is electrically connected on this South Bridge chip produces a wake-up signal to this South Bridge chip, and then makes this South Bridge chip remove the power down mode of this central processing unit;
The triggering of one second look-at-me of being sent according to this second peripheral unit that is electrically connected on this north bridge chips produces an interruption status indication information; And
By interruption status indication path, this interruption status indication information is sent to this South Bridge chip, and then makes this South Bridge chip can remove the power down mode of this central processing unit.
8. look-at-me control method as claimed in claim 7, wherein this wake-up signal is produced according to this first look-at-me by the one first output input interrupt control device that comprises on this South Bridge chip.
9. look-at-me control method as claimed in claim 7, wherein this interruption status indication information is produced according to this second look-at-me by the one second output input interrupt control device that comprises in this computer system.
10. look-at-me control method as claimed in claim 7, wherein these look-at-mes are that a kind of information signal interrupts.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101180959A CN100442261C (en) | 2003-12-01 | 2003-12-01 | Interrupt signal control system and control method |
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| CNB2003101180959A CN100442261C (en) | 2003-12-01 | 2003-12-01 | Interrupt signal control system and control method |
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| CN1547127A CN1547127A (en) | 2004-11-17 |
| CN100442261C true CN100442261C (en) | 2008-12-10 |
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| CN100426273C (en) * | 2007-05-31 | 2008-10-15 | 威盛电子股份有限公司 | Memorizer access device and its method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1252546A (en) * | 1998-10-23 | 2000-05-10 | 宏碁电脑股份有限公司 | Computer device and its change method from power economizing mode into operation mode |
| US6065122A (en) * | 1998-03-13 | 2000-05-16 | Compaq Computer Corporation | Smart battery power management in a computer system |
| US20020083349A1 (en) * | 2000-12-21 | 2002-06-27 | Khatri Mukund Purshottam | System and method for handling numerous power management signals |
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2003
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6065122A (en) * | 1998-03-13 | 2000-05-16 | Compaq Computer Corporation | Smart battery power management in a computer system |
| CN1252546A (en) * | 1998-10-23 | 2000-05-10 | 宏碁电脑股份有限公司 | Computer device and its change method from power economizing mode into operation mode |
| US20020083349A1 (en) * | 2000-12-21 | 2002-06-27 | Khatri Mukund Purshottam | System and method for handling numerous power management signals |
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