CN1266569C - Interrupt signal control method - Google Patents
Interrupt signal control method Download PDFInfo
- Publication number
- CN1266569C CN1266569C CN 200310120492 CN200310120492A CN1266569C CN 1266569 C CN1266569 C CN 1266569C CN 200310120492 CN200310120492 CN 200310120492 CN 200310120492 A CN200310120492 A CN 200310120492A CN 1266569 C CN1266569 C CN 1266569C
- Authority
- CN
- China
- Prior art keywords
- look
- bridge chip
- status indication
- south bridge
- control method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000002093 peripheral effect Effects 0.000 claims abstract description 56
- 230000005611 electricity Effects 0.000 abstract 1
- 230000015654 memory Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 101100016034 Nicotiana tabacum APIC gene Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Landscapes
- Power Sources (AREA)
Abstract
The present invention discloses a method for controlling an interrupt signal, which is applied to a computer system. The computer system is provided with a central processing unit (CPU), a north bridge chip, a bus bridge connecting device, a south bridge chip, a first peripheral device and a second peripheral device. The method for controlling an interrupt signal comprises the following steps: the first peripheral device electrically connected to the south bridge chip sends out a first interrupt signal to the north bridge chip; the second peripheral device electrically connected to the bus bridge connecting device sends out a second interrupt signal to the north bridge chip; the received interrupt signals are decoded and identified by the north bridge chip, and interrupt state indicating information is correspondingly generated when the interrupt signals are confirmed; the interrupt state indicating information is conveyed to the south bridge chip through an interrupt state indicating path, and thereby, the south bridge chip can release the electricity saving state of the central processing unit.
Description
Technical field
The present invention relates to a kind of look-at-me control method, finger is applied to the look-at-me control method in the computer system especially.
Background technology
Electricity-saving mechanism is quite extensive in the utilization of computer system, be applied to battery saving mode on the central processing unit (CPU) and then be divided into considerable level and kind (ACPI (Advanced Configuration and Power Interface for example, abbreviation ACPI) defined C1, C2 and C3 isotype in the specification), but its purpose is nothing more than being in order to the minimizing energy resource consumption and providing lower temperature stable circuit operation environment.And under general framework, (see also existing computer system configuration diagram shown in Figure 1), the central processing unit of computer system (CPU) 1 is by 2 management of the South Bridge chip in the chipset (South Bridge is called for short SB) by the mechanism that returns to normal operation in the battery saving mode.Following steps are to illustrate simply how central processing unit (CPU) 1 in the computer system enters C2 or C3 battery saving mode and recover the step of operate as normal again by C2 or C3 battery saving mode as follows:
1. the operating system (Operating System is called for short OS) of working as computer system is in the time of will entering battery saving mode, and central processing unit 1 is just issued a power-saving mode instruction (Sleep Command) to South Bridge chip 2.
2. when stopping clock pulse control module (STPCLK control module) 20 and receive this power-saving mode instruction in the South Bridge chip 2, produce (assert) immediately and stop clock signal (STPCLK#) and stop clock signal pin 21 passing to central processing unit 1 by one.
3. when this stops clock signal (STPCLK#) generation, central processing unit 1 just transmits a suspension of licence special instruction (STPGNT) to South Bridge chip 2 by the data bus of 2 of central processing unit 1, north bridge chips (North Bridge is called for short NB) 3 and South Bridge chips.
4. when South Bridge chip 2 received this suspension of licence special instruction (STPGNT), central processing unit 1 will all enter into battery saving mode together with whole computer system.
5. when first peripheral unit 4 sends look-at-me (interrupt) to South Bridge chip 2 by a look-at-me pin 41, it is to be received by the interrupt control device in the South Bridge chip 2 22, sends a wake-up signal by interrupt control device 22 again and stops clock pulse control module (STPCLK controlmodule) 20 and stop clock signal (STPCLK#) with what remove that (de-assert) produced to trigger this.
6. work as this clock signal (STPCLK#) that stops that stopping on the clock signal pin 21 and be disengaged, central processing unit 1 just can return to normal mode of operation from battery saving mode together with whole computer system.
But for continuous increase and elevator system overall efficiency in response to the peripheral unit number, the design of computer system architecture constantly produces change.See also shown in Figure 2, its information signal that is utilization computing machine periphery links in (PCI) specification interrupts (message signaled interrupt, abbreviation MSI) the future generation computer system configuration diagram that framework developed out, its different being in existing general computer system architecture is more set up on north bridge chips 3 as peripheral component interface bus bridge device (PCI to PCI Bridge) 5, uses to connect newly-increased peripheral unit (second peripheral unit 6 as shown in FIG.) and improve system effectiveness.
Thus, when central processing unit 1 is in the battery saving mode of C2 or C3 and first peripheral unit 4 when sending an information signal and interrupt (MSI) to South Bridge chip 2 by a peripheral component interface bus (PCI bus) 40, South Bridge chip 2 just can be directly interrupts (MSI) with this information signal, and the mode that writes instruction (memorywrite cycle) with internal memory is sent to north bridge chips 3 by the data bus of 3 of South Bridge chips 2, north bridge chips again.
In addition, when central processing unit 1 is in the battery saving mode of C2 or C3 and second peripheral unit 6 when sending an information signal and interrupt (MSI) to peripheral component interface bus bridge device (PCI to PCI Bridge) 5 by another peripheral component interface bus (PCI bus) 60, peripheral component interface bus bridge device (PCI toPCI Bridge) 5 just can interrupt information signal (message signaled interrupt, be called for short MSI), also the mode that writes instruction (memory write cycle) with internal memory is sent.
But because above-mentioned two kinds information signal interrupts (message signaled interrupt, be called for short MSI) all be the kenel existence that writes instruction (memory write cycle) with internal memory, and with normal existing tupe, it is to be connected in north bridge and can't to be sent to South Bridge chip 2 at being connected in Installed System Memory 70 on the north bridge chips 3 that internal memory writes instruction, therefore can't normally trigger this and stop clock pulse control module (STPCLK control module) 20 and stop clock signal (STPCLK#) with what remove that (de-assert) produced.Therefore under this system state of new generation, first peripheral unit 4 and second peripheral unit 6 all can't be waken up computer system effectively and return to normal mode of operation by battery saving mode.And how effectively to solve the above problem that has means now, for developing fundamental purpose of the present invention.
Summary of the invention
The invention provides a kind of look-at-me control method, be applied in the computer system, this computer system has a central processing unit, a north bridge chips, a bus bridge device, a South Bridge chip, one first peripheral unit and one second peripheral unit, and this look-at-me control method comprises the following step: this first peripheral unit that is electrically connected on this South Bridge chip sends one first look-at-me to this north bridge chips; This second peripheral unit that is electrically connected on this bus bridge device sends one second look-at-me to this north bridge chips; North bridge chips is deciphered identification to these received look-at-mes, just corresponding generation one interruption status indication information when confirming as look-at-me; And, this interruption status indication information is sent to this South Bridge chip, and then makes this South Bridge chip can remove the power down mode of this central processing unit by interruption status indication path.
According to above-mentioned conception, look-at-me control method of the present invention, wherein these look-at-mes be an information signal interrupt (message signaled interrupt, MSI).
According to above-mentioned conception, look-at-me control method of the present invention, wherein this bus bridge device is a peripheral component interface bus bridge device.
According to above-mentioned conception, look-at-me control method of the present invention, wherein this first peripheral unit is electrically connected to this South Bridge chip by a peripheral component interface bus, and this second peripheral unit is electrically connected to this bus bridge device by another peripheral component interface bus.
According to above-mentioned conception, look-at-me control method of the present invention, wherein this interruption status indication path is an interruption status indication pin, it is connected in one in north bridge chips 3 and this South Bridge chip and stops the clock pulse control module, and then the interruption status indication information be sent to this stop the clock pulse control module, and then remove that this stops that the clock pulse control module produced one stop clock signal.
According to above-mentioned conception, look-at-me control method of the present invention, wherein this interruption status indication path is a data bus, it is connected between north bridge chips and this South Bridge chip, stop the clock pulse control module in order to this interruption status indication information that this north bridge chips produced is sent to one in this South Bridge chip, so remove that this stops that the clock pulse control module produced one stop clock signal.
Description of drawings
The present invention must further specify by following accompanying drawing and detailed description:
Fig. 1 is the existing computer system configuration diagram.
Fig. 2 has the computer system architecture synoptic diagram that Advanced Programmable Interrupt Controllers APICs is gone in a plurality of outputs.
Fig. 3 is that the present invention is the preferred embodiment function block diagram that the existing defective of improvement is proposed.
Fig. 4 is that the present invention is another preferred embodiment function block diagram that the existing defective of improvement is proposed.
Wherein, description of reference numerals is as follows:
1 central processing unit (CPU), 2 South Bridge chips
20 stop clock pulse control module 21 stops the clock signal pin
3 north bridge chips, 22 interrupt control devices
4 first peripheral units, 40 peripheral component interface buses
5 peripheral component interface bus bridge devices, 6 second peripheral units
301 interruption statuss indication pin, 31 data buss
60 peripheral component interface buses, 70 Installed System Memories
Embodiment
See also Fig. 3, it is that the present invention is the preferred embodiment function block diagram that the existing defective of improvement is proposed, the present invention is mainly a kind of look-at-me control system, it can be arranged in the computer system, and this computer system has central processing unit 1 as shown in FIG., north bridge chips 3, Installed System Memory 70, South Bridge chip 2, first peripheral unit 4 and second peripheral unit 6, and look-at-me control system of the present invention consist predominantly of on the north bridge chips 3 interruption status indication pin 301 be integrated in the South Bridge chip 2 this and stop clock pulse control module (STPCLK control module) 20.
Thus, when central processing unit 1 is in the battery saving mode of C2 or C3, and first peripheral unit 4 or second peripheral unit 6 interrupt (MSI) when being sent to north bridge chips 3 by peripheral component interface bus 40, South Bridge chip 2 or peripheral component interface bus 60, peripheral component interface bus bridge device 5 with this information signal, north bridge chips 3 must have the information signal that first peripheral unit 4 or second peripheral unit 6 are sent and interrupt the ability that (MSI) deciphers, rather than only changes the action of biography.Specifically, when first peripheral unit 4 interrupts (MSI) when being sent to north bridge chips 3 by peripheral component interface bus 40 and South Bridge chip 2 with this information signal, north bridge chips 3 just deciphers to it whether it is a look-at-me with identification, and pick out it when being a look-at-me really when north bridge chips 3, facility is sent an interruption status indication information with the indication of the interruption status on the north bridge chips 3 pin 301, in order to notifying in this South Bridge chip 2 this to stop clock pulse control module (STPCLK controlmodule) 20, and then this clock signal (STPCLK#) that stops that stopping on the clock signal pin 21 is disengaged.In the same manner, when second peripheral unit 6 interrupts (MSI) when being sent to north bridge chips 3 by peripheral component interface bus 60 and peripheral component interface bus bridge device 5 with this information signal, north bridge chips 3 also will decipher whether it is a look-at-me with identification to it, and pick out it when being a look-at-me really when north bridge chips 3, also be to utilize the interruption status indication pin 301 on the north bridge chips 3 to send an interruption status indication information, in order to notifying in this South Bridge chip 2 this to stop clock pulse control module (STPCLK control module) 20, and then this clock signal (STPCLK#) that stops that stopping on the clock signal pin 21 is disengaged.Therefore, in preferred embodiment of the present invention, these peripheral units still can be effectively waken up central processing unit and computer system and return to normal mode of operation by C2 or C3 battery saving mode, and then can solve the problem of existing means effectively, reach to propose fundamental purpose of the present invention.Interruption status indication information as for this interruption status indication pin 301 can represent by following example that on behalf of north bridge chips 3, low voltage level do not receive look-at-me, and on behalf of north bridge chips 3, high-voltage level then receive look-at-me.
And for avoiding increasing pin, the data bus 31 that the present invention also can use 2 of this north bridge chips 3 and this South Bridge chips instead transmits the interruption status indication information (another preferred embodiment function block diagram as shown in Figure 4) that north bridge chips 3 is sent, it is to be sent to this in the mode of an information by data bus 31 in order to this interruption status indication that north bridge chips 3 is produced to stop clock pulse control module 20, so remove (de-assert) this stop that clock pulse control module 20 produced stop clock signal (STPCLK#).
In sum, the present invention is under this system state of new generation, still can effectively utilize these peripheral units and computer system is waken up by battery saving mode be returned to normal mode of operation, successfully solve the problem of existing means, reach and propose fundamental purpose of the present invention.Any those of ordinary skill in the art changes and modification according to the equalization that the present invention did in the field of the invention,, all belong to protection scope of the present invention.
Claims (6)
1. look-at-me control method, be applied in the computer system, this computer system has a central processing unit, a north bridge chips, a bus bridge device, a South Bridge chip, one first peripheral unit and one second peripheral unit, and this look-at-me control method comprises the following step:
This first peripheral unit that is electrically connected on this South Bridge chip sends one first look-at-me to this north bridge chips;
This second peripheral unit that is electrically connected on this bus bridge device sends one second look-at-me to this north bridge chips;
This north bridge chips is deciphered identification to these received look-at-mes, just corresponding generation one interruption status indication information when confirming as look-at-me; And
By interruption status indication path, this interruption status indication information is sent to this South Bridge chip, and then makes this South Bridge chip can remove the power down mode of this central processing unit.
2. look-at-me control method as claimed in claim 1, wherein these look-at-mes are that an information signal interrupts.
3. look-at-me control method as claimed in claim 1, wherein this bus bridge device is a peripheral component interface bus bridge device.
4. look-at-me control method as claimed in claim 1, wherein this first peripheral unit is electrically connected to this South Bridge chip by a peripheral component interface bus, and this second peripheral unit system is electrically connected to this bus bridge device by another peripheral component interface bus.
5. look-at-me control method as claimed in claim 1, wherein this interruption status indication path is an interruption status indication pin, it is connected in one in north bridge chips and this South Bridge chip and stops the clock pulse control module, and then the interruption status indication information be sent to this stop the clock pulse control module, and then remove that this stops that the clock pulse control module produced one stop clock signal.
6. look-at-me control method as claimed in claim 1, wherein this interruption status indication path is a data bus, it is connected between north bridge chips and this South Bridge chip, stop the clock pulse control module in order to this interruption status indication information that this north bridge chips produced is sent to one in this South Bridge chip, so remove that this stops that the clock pulse control module produced one stop clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310120492 CN1266569C (en) | 2003-12-16 | 2003-12-16 | Interrupt signal control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310120492 CN1266569C (en) | 2003-12-16 | 2003-12-16 | Interrupt signal control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1547088A CN1547088A (en) | 2004-11-17 |
| CN1266569C true CN1266569C (en) | 2006-07-26 |
Family
ID=34338297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200310120492 Expired - Lifetime CN1266569C (en) | 2003-12-16 | 2003-12-16 | Interrupt signal control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1266569C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI787042B (en) * | 2022-01-05 | 2022-12-11 | 大陸商北京集創北方科技股份有限公司 | Touch data transmission method, touch data transmission control circuit and information processing device |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7730337B2 (en) * | 2007-01-24 | 2010-06-01 | Via Technologies, Inc. | Method and apparatus for asserting a hardware pin to disable a data bus connecting a processor and a chipset during power saving state |
| CN100426273C (en) * | 2007-05-31 | 2008-10-15 | 威盛电子股份有限公司 | Memorizer access device and its method |
| CN100511048C (en) * | 2007-10-17 | 2009-07-08 | 威盛电子股份有限公司 | Power supply management method and management system thereof |
| CN101150809B (en) * | 2007-11-03 | 2011-02-02 | 青岛海信移动通信技术股份有限公司 | Method for arousing and stream control of mobile terminal processor serial port |
| US8667193B2 (en) * | 2011-04-29 | 2014-03-04 | Qualcomm Incorporated | Non-ported generic device (software managed generic device) |
-
2003
- 2003-12-16 CN CN 200310120492 patent/CN1266569C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI787042B (en) * | 2022-01-05 | 2022-12-11 | 大陸商北京集創北方科技股份有限公司 | Touch data transmission method, touch data transmission control circuit and information processing device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1547088A (en) | 2004-11-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7330926B2 (en) | Interruption control system | |
| US6708278B2 (en) | Apparatus and method for awakening bus circuitry from a low power state | |
| US6460143B1 (en) | Apparatus and method for awakening bus circuitry from a low power state | |
| US5596756A (en) | Sub-bus activity detection technique for power management within a computer system | |
| CN101976217B (en) | Anomaly detection method and system for network processing unit | |
| EP0666528B1 (en) | Integrated processor providing indications of internal activity to an external power management bus | |
| CN1818828A (en) | Information processing apparatus and control method for the same | |
| CN105487638B (en) | Electronic circuit system and its method for reducing power consumption | |
| CN1821973A (en) | Fault tolerant computer system and interrupt control method for the same | |
| CN1873585A (en) | Information processing apparatus and controlling method thereof | |
| CN1889050A (en) | System and method for raising single-board exception handling ability | |
| CN103377081A (en) | Implementation method for interrupt mechanism between embedded numerical control system dual-core chip and peripheral | |
| TWI752291B (en) | Application processor, automotive electronic processor, and computing device including application processor | |
| CN1266569C (en) | Interrupt signal control method | |
| CN101051242A (en) | Power supply control method and device for computer system | |
| CN100452005C (en) | System and method for controlling interrput | |
| CN105739666A (en) | Conversion method for reducing power consumption and computing apparatus using the same | |
| US7363408B2 (en) | Interruption control system and method | |
| US7802119B2 (en) | Method and system for saving power of central processing unit | |
| CN1577213A (en) | Method for pci express power management using a pci pm mechanism in a computer system | |
| US7206883B2 (en) | Interruption control system and method | |
| CN1619467A (en) | Computer system and power source management state | |
| CN100442261C (en) | Interrupt signal control system and control method | |
| CN1158614C (en) | High-integated-level hot-standby industrial control motherboard | |
| US20060221751A1 (en) | Memory power supply backup system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20060726 |
|
| CX01 | Expiry of patent term |