CN100426273C - Memorizer access device and its method - Google Patents
Memorizer access device and its method Download PDFInfo
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- CN100426273C CN100426273C CNB2007101087197A CN200710108719A CN100426273C CN 100426273 C CN100426273 C CN 100426273C CN B2007101087197 A CNB2007101087197 A CN B2007101087197A CN 200710108719 A CN200710108719 A CN 200710108719A CN 100426273 C CN100426273 C CN 100426273C
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Abstract
A memory access device is used for accessing a memory of one memory module in a computer system besed on an index instruction and a data instruction. The memory access device in the invention includes a register and a memory access logic unit. The register for receiving the index instruction stroes an index value corresponding to the index instruction. The memory access logic unit performs an access operation corresponding to the data instruction for the memory based on the index value stroed in the register when the memory access logic unit receives the data instruction. Wherein, a interrupt handler of computer system can access the memory via another index instruction and another data instruction in order that an interroption is executed.
Description
Technical field
The present invention relates to a kind of memory access device, particularly relate to a kind of memory access device of the storer in order to the access south bridge.
Background technology
Data in the memory module in the VGA of the inside computer system software need access south bridge, when for example being picture buffer size (frame buffer size), VGA software need be called out a callback procedure (call-back function).Callback procedure memory module is thus obtained required information, passes information needed back VGA software.
The memory module of south bridge only has an indexed registers (index register) and a data register (data register).On software application, come this indexed registers of access and data register with paired index port (index port) instruction and FPDP (data port) instruction, and then the storer of access memory module.Paired index instruction and data command for example come access indexed registers and data register by index port 70h port and FPDP 71h port or index port 74h port and FPDP 75h port.That is index port 70h port and 74h port correspond to same indexed registers, and FPDP 71h port and 75h port correspond to same data register.
Yet callback procedure is when this storer of access, if an interruption (interrupt) takes place, its interrupt handling routine (interrupt handler) may unexpectedly change the address of the storer of the access of wanting originally.After so will causing End of Interrupt, the data of the misaddress of callback procedure access in the storer make computer system produce unexpected result.
Use the index instruction and the data command of corresponding 70h port and 71h port with interrupt handling routine, callback procedure uses the index instruction of corresponding 74h port and 75h port and data command to come access memory to be example, illustrates how above-mentioned mistake takes place.Fig. 1 shows the synoptic diagram of the example that the generation interruption leads to errors when the callback procedure access memory.The instruction that square 110,120 and 130 is respectively in VGA software, callback procedure and interrupt handling routine.In square 110, VGA software call callback procedure.Afterwards, in square 120, callback procedure sends index instruction, and index value A0h is sent to index port 74h port, and index value A0h is stored in (mov a1, A0h among the address register a1; Out 74h a1), is promptly storing index value A0h among the register a1 now.The interruption of one high priority takes place afterwards, unfortunately.In square 130, interrupt handling routine sends index instruction, and the index value A0h that will be positioned at address register a1 by index port 70h changes error indexes value 0ch (mov a1, a 0ch into; Out70h, a1; In a1 71h), is promptly storing index value 0ch among the register a1 now.After interrupting end, get back to square 120, callback procedure sends data command, index value according to address register, FPDP 75h port by south bridge, when coming access memory, that be referenced to is not original index value A0h, but the error indexes value 0ch that index instruction changed into of interrupt handling routine.Therefore the data of access in the misaddress of the pairing storer of 0ch, but not A0h the data in the pairing storage address.
Summary of the invention
The present invention is relevant for the storer of memory access device in order to a memory module of access one computer system.Memory access device of the present invention is wanted the index value of access with register-stored.When receiving data command, the storage access logical block is just carried out the accessing operation of corresponding data instruction to the storer of memory module according to index value.Thus, even an interruption took place before the storage access logical block is received data command, and access is to the indexed registers of memory module, and the storage access logical block still can be carried out access to the storer of memory module according to correct index value, and the influence of not interrupted.
A kind of memory access device is proposed, in order to a storer according to a memory module of one first index instruction and one first data command access, one computer system according to the present invention.Memory access device of the present invention comprises one first register and a storage access logical block.First register is in order to receiving first index instruction, and stores pairing one first index value of first index instruction.When the storage access logical block is used to receive first data command,, storer is carried out the accessing operation of corresponding first data command according to first index value that is stored in first register.Wherein, the interrupt handling routine of computer system is by one second index instruction and one second data command access memory, to carry out an interruption.
A kind of access method of storage is also proposed, in order to a storer according to a memory module of one first index instruction and one first data command access, one computer system according to the present invention.Access method of storage of the present invention comprises: at first, receive first index instruction, and one first index value of storing first index instruction is in one first register.Afterwards, receive first data command.Then, according to first index value that is stored in first register storer is carried out the accessing operation of corresponding first data command.Wherein, the interrupt handling routine of computer system is by one second index instruction and one second data command access memory, to carry out an interruption.
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 shows the synoptic diagram of the example that the generation interruption leads to errors when the callback procedure access memory.
Fig. 2 shows the calcspar of the memory access device of the embodiment of the invention.
Fig. 3 shows the calcspar of the memory access device of another embodiment of the present invention.
Fig. 4 shows the access method of storage of the embodiment of the invention.
The reference numeral explanation
210,310,330: register
220,320: the memory access logical block
240,340: memory module
Embodiment
Fig. 2 shows the calcspar of the memory access device 200 of the embodiment of the invention.Memory access device 200 is in order to a storer of a memory module 240 of foundation one index port (index port) instruction I1 and a FPDP (dataport) instruction D1 access one computer system.Memory access device 200 comprises register 210 and storage access logical block 220.Register 210 is in order to reception hint instruction I1, and the pairing index value VI1 of storage index instruction I1.When storage access logical block 220 is used to receive data command D1, the storer in the memory module 240 is carried out the accessing operation of corresponding data instruction D1 according to the index value VI1 that is stored in register 210.Wherein, the interrupt handling routine of computer system comes this storer of access by another index instruction I2 and another data command D2, to carry out an interruption.
The storer of the memory module 240 of 200 accesses of memory access device is that example is done explanation with the storer of the memory module in the south bridge of computer system.Memory module 240 only has an indexed registers and a data register.In embodiments of the present invention, access indexed registers and data register palpus are by paired index port 70h port and FPDP 71h port, or index port 74h port and FPDP 75h port.
In embodiments of the present invention, when index instruction I1 and data command D1 are the computer system executive software, sent by program software.Index instruction I1 and data command D1 are for example for when the VGA of inside computer system software needs the storer of the memory module in the access south bridge, the callback procedure of VGA software (callback function) sends, with the storer of access memory module 240.
In embodiments of the present invention, index instruction I2 and data command D2 are sent when desiring the storer of access memory module 240 by the operating system of computer system, with the storer of access memory module 240.For example for when one interrupts needing the storer of the memory module 240 in the access south bridge, the interrupt handling routine of interruption sends for index instruction I2 and data command D2.The right of priority of index instruction I2 and data command D2 is higher than index instruction I1 and data command D1.
In embodiments of the present invention, index instruction I1 is stored to register 210 by the index port 74h of south bridge with an index value VI1.When the index port 75h of data command D1 by south bridge is sent to storage access logical block 220, storage access logical block 220 send corresponding stored in the index instruction I3 of the index value VI1 of register 210 and data command D1 to memory module 240.
Index instruction I3 and data command D1 are by the indexed registers and the data register of index port 74h port and FPDP 75h port access memory module 240, with the storer of access memory module 240.When the corresponding read operation of data command D1, then reference key value VI1 reads data R1 by the storer of memory module 240.When the corresponding write operation of data command D1, reference key value VI1 writes the storer of data to memory module 240.
The advantage of the memory access device of the embodiment of the invention now is described.When the callback procedure of VGA sent index instruction I1 to register 210, the index value VI1 of manipulative indexing instruction I1 was stored in the register 210.
At this moment, one interrupts taking place.The interrupt handling routine of this interruption sends an index instruction I2 and a data command D2 to storage access logical block 220.Storage access logical block 220 is sent index instruction I2 and data command D2 again, come the indexed registers and the data register of access memory module 240 by index port 70h port and FPDP 71h port respectively, with the storer of access memory module 240.At this moment, this indexed registers stores the pairing index value VI2 of index instruction I2.
After interrupting end, the callback procedure of the VGA beginning is sent data command D1 to storage access logical block 220.When storage access logical block 220 received data command D1, the index instruction I3 of the manipulative indexing value that starts out VI1 and data command D1 were to the indexed registers and the data register of memory module 240, with the storer of access memory module 240.At this moment, this indexed registers promptly stores index value VI1, but not the index value VI2 of corresponding interrupt handling routine.Therefore, storage access logical block 220 is able to reference key value VI1, the correctly storer of access memory module 240.
Fig. 3 shows the memory access device 300 of another embodiment of the present invention.Different with memory access device 200 is, memory access device 300 also comprises a register 330, in order to reception hint instruction I2, and the pairing index value VI2 of storage index instruction I2.When data command D2 is sent to storage access logical block 320, storage access logical block 220 send corresponding stored in the index instruction I4 of the index value VI2 of register 330 and data command D2 to memory module 340.
Index instruction I3 and data command D1 are by the indexed registers and the data register of index port 70h port and FPDP 71h port access memory module 340, with the storer of access memory module 340.When the corresponding read operation of data command D2, then reference key value VI2 reads data R2 by the storer of memory module 340.When the corresponding write operation of data command D2, reference key value VI2 writes the storer of data to memory module 340.
In all embodiment of the present invention, index instruction I1 and data command D1 are respectively by index port 74h port and FPDP 75h port, and index instruction I2 and data command D2 pass through the storer of index port 70h port and FPDP 71h port access memory module respectively.In the practical application, be not limited to by above-mentioned 70h port, 71h port, 74h port and 75h port.Index instruction I1, I2 and data command D1, D2 can come access by any index port and FPDP in order to the storer of access memory module.
According to the present invention the memory access device of notion can be designed to be positioned within the south bridge of computer system or outside, as long as memory access device is positioned at before the memory module, make that index instruction I1, I2 and data command D1, D2 are sent to register earlier and storage access logical block 220 gets final product.
Fig. 4 shows the access method of storage of the embodiment of the invention, is used for above-mentioned memory access device 200, in order to a storer of foundation index instruction I1 and data command D1 access memory module 240.Please refer to Fig. 4.At first, in step 410, reception hint instruction I1, and the index value VI1 of storage manipulative indexing instruction I1 is in register 210.Afterwards, in step 420, receive data command D1.Then, in step 430, the storer of memory module 240 is carried out the accessing operation of corresponding data instruction D1 according to the index value VI1 that is stored in register 210.The interrupt handling routine of computer system is by the storer of index instruction I2 and data command D2 access memory module 240, to carry out an interruption.
The memory access device of the embodiment of the invention is with the index value VI1 of access that register-stored is desired.When receiving data command D1, the storage access logical block beginning is carried out the accessing operation of corresponding data instruction D1 to the storer of memory module according to index value VI1.Therefore, even an interruption took place before the storage access logical block is received data command D1, and access the indexed registers of memory module, the storage access logical block still can be carried out access to the storer of memory module according to correct index value, and the influence of not interrupted.
In addition, the memory access device of using the embodiment of the invention can directly apply to present computer system, does not need significantly to change original framework of computer system.Therefore, the memory access device of using the embodiment of the invention also can be saved production cost, increase production efficiency.
In sum, though the present invention discloses as above with a preferred embodiment, it is not in order to limit the present invention.Those skilled in the art under the premise without departing from the spirit and scope of the present invention, can do some changes and modification.Therefore, protection scope of the present invention should be as the criterion with the application's claim.
Claims (10)
1. memory access device, the storer in order to according to a memory module of one first index instruction and one first data command access, one computer system is characterized in that, comprising:
One first register in order to receiving this first index instruction, and is stored pairing one first index value of this first index instruction; And
One storage access logical block when receiving this first data command, according to being stored in this first index value of this first register, is carried out accessing operation that should first data command this storer;
Wherein, an interrupt handling routine of this computer system is by one second index instruction and one second this storer of data command access, to carry out an interruption.
2. memory access device as claimed in claim 1 is characterized in that, this second index instruction and this second data command have precedence over this first index instruction and this first data command.
3. memory access device as claimed in claim 1, it is characterized in that, this memory module comprises an indexed registers and a data register, this first index instruction is by one first this first register of index port access, second index instruction is by one second this indexed registers of index port access, and this first and second data command is respectively by one first FPDP and one second this data register of FPDP access.
4. memory access device as claimed in claim 3, it is characterized in that, when this storage access logical block receives this first data command, send one the 3rd index instruction and this first data command, wherein the 3rd index instruction comes this indexed registers of access and this data register respectively, with this storer of access corresponding to this first index value that is stored in this first register, wherein, the 3rd index instruction comes this indexed registers of access by this first index port.
5. memory access device as claimed in claim 1 is characterized in that, this memory access device also comprises:
One second register in order to receiving this second index instruction, and is stored pairing one second index value of this second index instruction;
Wherein, when this storage access logical block also is used to receive this second data command, this storer is carried out accessing operation that should second data command according to this second index value that is stored in this second register.
6. memory access device as claimed in claim 1 is characterized in that, this memory module is the memory module of the south bridge of this computer system.
7. access method of storage, the storer in order to according to a memory module of one first index instruction and one first data command access, one computer system is characterized in that, comprising:
Receive this first index instruction, and one first index value of storing this first index instruction is in one first register;
Receive this first data command; And
According to this first index value that is stored in this first register this storer is carried out accessing operation that should first data command;
Wherein, an interrupt handling routine of this computer system is by one second index instruction and one second this storer of data command access, to carry out an interruption.
8. access method of storage as claimed in claim 7 is characterized in that, this second index instruction and this second data command system have precedence over this first index instruction and this first data command.
9. access method of storage as claimed in claim 7 is characterized in that, this storer is the storer of the south bridge of this computer system.
10. access method of storage as claimed in claim 7 is characterized in that, also comprises one second register, in order to store one second index value of this second index instruction.
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| CNB2007101087197A CN100426273C (en) | 2007-05-31 | 2007-05-31 | Memorizer access device and its method |
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| CNB2007101087197A CN100426273C (en) | 2007-05-31 | 2007-05-31 | Memorizer access device and its method |
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| CN101419541B (en) * | 2007-10-25 | 2011-03-30 | 晶心科技股份有限公司 | Method for accessing one destination register in multi registers and relevant device thereof |
| CN105900060B (en) * | 2014-11-07 | 2019-05-03 | 华为技术有限公司 | Memory pool access method, device and computer equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540539A (en) * | 2003-10-28 | 2004-10-27 | 威盛电子股份有限公司 | System and method for controlling interrput |
| CN1547127A (en) * | 2003-12-01 | 2004-11-17 | 威盛电子股份有限公司 | Interrupt signal control system and control method |
| CN1547088A (en) * | 2003-12-16 | 2004-11-17 | 威盛电子股份有限公司 | Interrupt signal control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540539A (en) * | 2003-10-28 | 2004-10-27 | 威盛电子股份有限公司 | System and method for controlling interrput |
| CN1547127A (en) * | 2003-12-01 | 2004-11-17 | 威盛电子股份有限公司 | Interrupt signal control system and control method |
| CN1547088A (en) * | 2003-12-16 | 2004-11-17 | 威盛电子股份有限公司 | Interrupt signal control method |
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