CN110554979A - time-piece device and method for operating same - Google Patents

Abstract

A timing device and a method of operating the same. The timing device includes: single-chip module and digital timing module. The single chip module is configured to perform event processing according to at least two internal interrupt signals inside. The digital timing module is configured to time and generate a timing interrupt signal to the single chip module when a timing event occurs; the priority level of the timing interrupt signal is higher than that of the at least two internal interrupt signals, so that the single chip module performs priority processing on the interrupt service program corresponding to the timing interrupt signal when receiving the timing interrupt signal.

Description

Timing device and method of operation thereof

technical field

The invention relates to timing technology, and in particular to a timing device and an operating method thereof.

Background technique

Single-chip modules such as (but not limited to) 8051 chips integrate various basic circuits into a single chip, and are widely used as controllers in many electronic devices because of their small size. When the single-chip module is processing data, it can handle more urgent events according to the internal interrupt signal. However, as the application becomes more and more complex, more and more events need to be processed. When the priority level of the internal interrupt signal is not enough to distinguish more types of events, it often makes internal modules such as (but not limited to) timers unable to The occurrence of the single-chip module event is notified in time by an internal interrupt signal.

Therefore, how to design a new timing device and its operation method to solve the above-mentioned defects is an urgent problem to be solved in this industry.

Contents of the invention

The object of the present invention is to provide a timing device, including: a single-chip module and a digital timing module. The single-chip module is configured to perform event processing according to at least two internal interrupt signals. The digital timing module is configured to perform timing, and when a timing event occurs, generate a timing interrupt signal to the single-chip module, wherein the priority level of the timing interrupt signal is higher than at least two internal interrupt signals, so that the single-chip module receives the timing interrupt Signals are prioritized to execute the interrupt service routine corresponding to the timing interrupt signal.

Another object of the present invention is to provide a method for running a timing device, including: enabling the single-chip module to perform event processing according to at least two internal interrupt signals; and enabling the digital timing module to perform timing, and when timing events occur, generate The timer interrupt signal is sent to the single-chip module, wherein the priority level of the timer interrupt signal is higher than at least two internal interrupt signals; and the single-chip module is given priority to process and execute the interrupt service program corresponding to the timer interrupt signal when receiving the timer interrupt signal.

The advantage of applying the present invention is that through the design of the timing device, the digital timing module can use the timing interrupt signal with a higher priority level than the internal interrupt signal, so that the single chip module can process timing events first.

Description of drawings

Fig. 1 is a block diagram of a timing device in an embodiment of the present invention; and

Fig. 2 is a flow chart of the operation method of the timing device in an embodiment of the present invention.

Symbol Description

1: Timing device 10: Single chip module

100: CPU 101: Internal interrupt signal

102: memory 103: setting signal

104: Timer 105: Interrupt Service Routine

106: Input and output interface 12: Digital timing module

121: Timing interruption signal 200: Timing device operation method

201-203: Steps

Detailed ways

Please refer to Figure 1. FIG. 1 is a block diagram of a timing device 1 in an embodiment of the present invention. The timing device 1 includes: a single chip module 10 and a digital timing module 12 .

The single-chip module 10 can be any microcomputer such as (but not limited to) the central processing unit 100, the memory 102, the timer 104, various input and output interfaces 106, etc. are integrated on one integrated circuit chip. In one embodiment, the CPU 100 can be electrically connected and communicated with the memory 102 , the timer 104 and the I/O interface 106 through a bus (not shown). In one embodiment, the single-chip module 100 is, for example (but not limited to), an 8051 chip.

The single-chip module 10 can process and calculate various data through the central processing unit 100 , and can process events according to the internal interrupt signal 101 . For example, when the I/O interface 106 receives an external signal that needs to be processed, it will generate an internal interrupt signal 101 and send it to the central processing unit 100 through the bus. The central processing unit 100 will temporarily stop the data being processed, and give priority to the demand of the internal interrupt signal 101 .

The circuits included in the single-chip module 10 can generate internal interrupt signals 101 with at least two priority levels. In one embodiment, the internal interrupt signal 101 may have two priority levels. Therefore, the internal interrupt signal 101 includes a high-priority internal interrupt signal and a low-priority internal interrupt signal.

When an internal interrupt signal with a high priority level is generated, another internal interrupt signal with a low priority level can be forced to stop running. When an internal interrupt signal of a low priority level is generated, it can only be executed by the single-chip module 10 under the condition that no internal interrupt signal is running. As for an internal interrupt signal with a high priority level in execution, no internal interrupt signal with a lower or the same priority level can stop its operation.

The digital timing module 12 is a digital timing circuit arranged outside the single-chip module 10 and is configured to perform timing. In one embodiment, the central processing unit 100 of the single-chip module 10 is further configured to set the digital timing module 12 through, for example (but not limited to), the setting signal 103 .

In one embodiment, the single-chip module 10 sets the digital timing module 12 to run in, for example (but not limited to), an auto reload (auto reload) mode. That is, the digital timing module 12 will automatically return to zero when the timing parameter overflows. In one embodiment, when the parameter overflows, it is a timing event for the digital timing module 12 .

In one embodiment, the single-chip module 10 can set the timing accuracy of the digital timing module 12 .

The digital timing module 12 generates a timing interrupt signal 121 to the single-chip module 10 when a timing event (such as but not limited to the above-mentioned parameter overflow) occurs. In more detail, the digital timing module 12 can generate a timing interrupt signal 121 to the CPU 100 in the single-chip module 10 . The priority level of the timing interrupt signal 121 is higher than the above two internal interrupt signals, so that when the single-chip module 10 receives the timing interrupt signal 121, it can preferentially process and execute the interrupt service program 105 corresponding to the timing interrupt signal 121 .

In one embodiment, the timing interrupt signal 121 is, for example (but not limited to), a power fail interrupt signal.

Interrupt service routine 105 may be stored in, for example, but not limited to, memory 102 . In one embodiment, the single-chip module 10 executes the interrupt service routine 105 to accumulate its internal timing variables. In one embodiment, whenever the single-chip module 10 receives a timing interrupt signal 121 , it executes the interrupt service program 105 to increase the timing variable by 1 to achieve the technical effect of timing.

Since the single-chip module 10 needs to handle quite a variety of different events in the current application, when the priority level of the internal interrupt signal is not enough to distinguish more types of events, the internal timer 104 is often unable to use the internal interrupt signal in time. Inform the single-chip module 10 of the occurrence of the timing event. Therefore, through the design of the timing device 1 , the digital timing module 12 can enable the single-chip module 10 to process timing events preferentially through the timing interrupt signal 121 with a higher priority level than the internal interrupt signal.

Please refer to Figure 2. FIG. 2 is a flowchart of a timing device operating method 200 in an embodiment of the present invention. It can be applied to the timing device 1 of FIG. 1 . The timing device operating method 200 includes the following steps (it should be understood that, unless the order of the steps mentioned in this embodiment is specifically stated, the order of the steps can be adjusted according to actual needs, and can even be executed simultaneously or partially simultaneously).

In step 201 , make the single-chip module 10 perform event processing according to at least two internal interrupt signals 101 .

In step 202, the digital timing module 12 is enabled to perform timing, and when a timing event occurs, a timing interrupt signal 121 is generated to the single-chip module 10, wherein the priority level of the timing interrupt signal 121 is higher than at least two internal interrupt signals 101 .

In step 203 , when the single-chip module 10 receives the timing interrupt signal 121 , the interrupt service routine 105 corresponding to the timing interrupt signal 121 is preferentially processed and executed.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A timing device comprising: a single-chip module configured to perform event processing based on internal at least two internal interrupt signals; and A digital timing module configured to perform timing, and when a timing event occurs, generate a timing interrupt signal to the single-chip module, wherein the priority level of the timing interrupt signal is higher than the at least two internal interrupt signals, so that the When the single-chip module receives the timing interrupt signal, it preferentially processes and executes an interrupt service program corresponding to the timing interrupt signal. 2. The timing device as claimed in claim 1, wherein the single-chip module is further configured to set the digital timing module to operate in an auto-reload mode. 3. The timing device as claimed in claim 2, wherein the single-chip module is further configured to set the digital timing module to generate the timing interrupt signal at a fixed time interval. 4. The timing device as claimed in claim 1, wherein the single-chip module executes the interrupt service routine to accumulate a timing variable. 5. The timing device as claimed in claim 1, wherein the timing interrupt signal is a power failure interrupt signal. 6. The timing device as claimed in claim 1, wherein the single-chip module is an 8051 chip. 7. A method for operating a timing device, comprising: enabling a single-chip module to perform event processing according to at least two internal interrupt signals; enabling a digital timing module to perform timing, and generating a timing interrupt signal to the single-chip module when a timing event occurs, wherein the priority level of the timing interrupt signal is higher than that of the at least two internal interrupt signals; and When the single-chip module receives the timing interrupt signal, it preferentially processes and executes an interrupt service program corresponding to the timing interrupt signal. 8. The timing device operating method as claimed in claim 7, further comprising: The single-chip module is also configured to set the digital timing module to run in an automatic reload mode. 9. The timing device operating method as claimed in claim 8, further comprising: The single-chip module is further configured to set the digital timing module to generate the timing interrupt signal at a fixed time interval. 10. The timing device operating method as claimed in claim 7, further comprising: The single-chip module executes the interrupt service routine to accumulate a timing variable.