CN101221518A - Method, device and system for preventing timing device overflow of hardware watchdog - Google Patents
Method, device and system for preventing timing device overflow of hardware watchdog Download PDFInfo
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Abstract
The invention discloses a method, a device and a system for preventing watchdog feeding time-out, wherein, a control device detects whether a timer of a hardware watchdog is cleared by a hardware watchdog monitoring device within set time; if the timer is cleared, the control device sends a clearing signal to the hardware watchdog and/or sends an external interrupt signal with highest priority to the hardware watchdog monitoring device. By utilization of the method and the system which are provided by the embodiment of the invention, the hardware watchdog monitoring device like a CPU operating field can be protected, and operation related information can be preserved, thereby analysis of reasons of operation exception is convenient.
Description
Technical field
The present invention relates to field of computer technology, relate to method, device and system that a kind of timer that prevents hardware watchdog overflows especially.
Background technology
Interrupt: interruption is the important technology that CPU handles outside accident.It can make CPU in operational process the interrupt request that external event sends be handled in time.When CPU received interrupt request, the program that interruption is being carried out was changeed and is gone to handle comprising in the interrupt request of task, continued to carry out the original program of CPU after finishing dealing with again.The source that the reason that causes interruption is sent interrupt request in other words is called interrupt source.According to the difference of interrupt source, can be divided into hardware interrupts and software interruption two big classes to interruption, and hardware interrupts can be divided into external interrupt and internal interrupt two classes.Internal interrupt is produced under certain situation by CPU inter-process module, and its priority generally is lower than external interrupt.The general external circuit of external interrupt passes to CPU by the interrupt pin of CPU.In externally interrupting a kind of interruption is arranged, its priority is to be higher than all internal interrupt and other external interrupt, and the look-at-me of this limit priority is passed to CPU or passed to CPU from one of CPU special pin by the interrupt pin of external circuit by CPU.
Hardware watchdog: as shown in Figure 1, device 11 is commonly called as hardware watchdog, mainly comprise a watchdog timer, it regularly exports the reset signal input pin 13 that is connected to CPU12, CPU sends instruction by bus 14 to CPLD15, make control device 15 periodically send high level or low level to the feeding-dog signal input pin 16 of hardware watchdog, this timing makes its timing that is shorter than hardware watchdog through setting, thereby the timer in the hardware watchdog 11 just was cleared before overflowing.CPU12 is commonly called as " feeding dog " by bus 14 to the operation that CPLD15 transmission clear command is cleared the timer in the hardware watchdog 11,, then is called " it is overtime to feed dog " if this clear operation before overflowing of the timer in the hardware watchdog 11 is not carried out.When CPU12 was working properly, the timer in the hardware watchdog 11 did not overflow because of zero clearing, so can not send reset signal to CPU12.If thereby the work of CPU12 makes a mistake in the time of can't feeding dog, its timing end after will overflow when timer this moment, thereby send reset signal to CPU12, CPU12 receives the task that reset signal termination is afterwards being handled, get back to the original state of its work, thereby the work state information of CPU12 before resetting is eliminated also.
Summary of the invention
The device that monitors when hardware watchdog, as CPU etc., work take place unusual and when causing being resetted by hardware watchdog, the work state information before resetting is also lost immediately, is not easy to the reason that profiling error produces.
For addressing the above problem, the embodiment of the invention provides following technical scheme:
The method that a kind of timer that prevents hardware watchdog overflows, the device that control device detection hardware house dog monitors when arriving setting-up time whether not with the timer zero clearing of hardware watchdog, if control device sends reset signal and/or sends the limit priority external interrupt signal to the device that hardware watchdog monitors to hardware watchdog.
The device that the embodiment of the invention provides a kind of timer that prevents hardware watchdog to overflow comprises detecting unit and reset signal transmitting element, wherein,
Described detecting unit, be used for device that the detection hardware house dog monitors when arriving setting-up time whether not with described timer zero clearing;
Described reset signal transmitting element is used for the device that monitors when hardware watchdog and sends reset signal to hardware watchdog during not with described timer zero clearing when arriving setting-up time.
The device that the timer that the embodiment of the invention provides another to prevent hardware watchdog overflows comprises detecting unit and look-at-me transmitting element, wherein,
Described detecting unit, be used for device that the detection hardware house dog monitors when setting-up time whether not with described timer zero clearing,
Described look-at-me transmitting element is used for the device that the device that monitors when hardware watchdog monitors to hardware watchdog during not with described timer zero clearing and sends the highest priority interrupt signal when arriving setting-up time.
The device that the timer that the embodiment of the invention provides another to prevent hardware watchdog overflows comprises detecting unit, reset signal transmitting element and look-at-me transmitting element, wherein,
Described detecting unit, be used for device that the detection hardware house dog monitors when arriving setting-up time whether not with described timer zero clearing,
Described reset signal transmitting element is used for the device that monitors when hardware watchdog and sends reset signal to hardware watchdog during not with described timer zero clearing when arriving setting-up time,
Described look-at-me transmitting element, the device that is used for monitoring to hardware watchdog sends the highest priority interrupt signal.
The system that the embodiment of the invention provides a kind of timer that prevents hardware watchdog to overflow comprises control device, interrupt response device and interruption processing module, wherein,
Described control device comprises detecting unit, reset signal transmitting element, look-at-me transmitting element and judging unit, wherein,
Described detecting unit, be used for device that the detection hardware house dog monitors when arriving setting-up time whether with described timer zero clearing,
Described reset signal transmitting element is used for the device that monitors when hardware watchdog and sends reset signal to hardware watchdog during not with described timer zero clearing when arriving setting-up time,
Described look-at-me transmitting element, the device that is used for monitoring to hardware watchdog sends the highest priority interrupt signal,
Described judging unit, be used for if the device that described hardware watchdog monitors when arriving setting-up time not with described timer zero clearing, judge whether the device that this moment, described hardware watchdog monitored is in the process of highest priority interrupt service, if then described detecting unit stops described detection;
Described interrupt response device is used to receive the highest priority interrupt signal;
Described interruption processing module is used for carrying out interrupt service routine when described interrupt response device is received the highest priority interrupt signal.
The method and system that uses the embodiment of the invention to provide; at the device that occurs can protecting hardware watchdog to monitor when unusual, as CPU etc., the working site; and make that the relevant information of work of the device that hardware watchdog monitors is preserved, be convenient to analyze the reason of its operation irregularity.
Description of drawings
Fig. 1 is a system and device synoptic diagram in the prior art;
A kind of system and device synoptic diagram that Fig. 2 provides for the embodiment of the invention;
A kind of system and device synoptic diagram that Fig. 3 provides for the embodiment of the invention;
A kind of system and device synoptic diagram that Fig. 4 provides for the embodiment of the invention.
Embodiment
The embodiment of the invention provides method, device and the system that a kind of timer that prevents hardware watchdog overflows.The device that control device detection hardware house dog monitors whether in setting-up time not with the timer zero clearing of hardware watchdog, if control device sends reset signal and/or sends the limit priority external interrupt signal to the device that hardware watchdog monitors to hardware watchdog.
System with hardware watchdog and CPU and CPLD (Complex Programmable LogicDevice, CPLD) composition in the present embodiment is that example describes the method in the present embodiment.As shown in Figure 1, CPU12 is when working properly, every time interval T
1Promptly feed dog instruction to the CPLD15 transmission with the instruction of the timer zero clearing of hardware watchdog by bus 14, CPLD15 receives that it is feeding-dog signal that the reset signal input pin 16 of feeding after the dog instruction immediately to hardware watchdog 11 sends reset signals, hardware watchdog 11 is received behind the feeding-dog signal the timer zero clearing, thereby is guaranteed that CPU12 can not reset.
Unusual when the work generation of CPU12, for example enter the program endless loop or keep waiting status because of certain is wrong, feed the dog instruction and just can't send.So CPLD15 detects CPU12 T after sending the instruction of hello dog last time
2Do not send in the time interval and feed the dog instruction, this moment, CPLD15 was at the hardware watchdog 11 timing Ts of CPU12 after sending the instruction of hello dog last time
0Before, have following operation available:
1, CPLD15 sends reset signal to the dog pin of feeding of hardware watchdog 11, and this operation also can be referred to as " feeding dog ", so this signal also can be called " feeding-dog signal ", can avoid CPU12 to be reset.T herein
1＜T
2CPLD15 need be arranged to every T
3Time sends feeding-dog signal, T
3＜T
0, CPU12 also keeps not being reset like this, and managerial personnel can study the working condition of CPU12 at this point.
2, CPLD15 sends the highest priority interrupt signal to CPU12, thereby makes CPU12 jump out current task, then carries out interrupt service routine.The instruction that comprises in the interrupt service routine has following available:
(1), feeds the dog instruction.Interrupt service routine sends immediately and feeds the dog instruction after response is interrupted, then every T
4＜T
0Time send feeding-dog signal, CPU12 also keeps not being reset like this, managerial personnel can study the working condition of CPU12 at this point.
(2), recording instruction, with the information of record CPU12 performed task before receiving the limit priority external interrupt signal.
(3) if the recording process in (2) is consuming time more than T
1-T
2, then CPU12 is resetted by hardware watchdog 11 writing down imperfect tense, so if estimate this situation to occur, must comprise in the interrupt service routine and feed dog instruction, the combination of also promptly above-mentioned (1), (2).
3, above-mentioned 1 and 2 two operation combination is carried out.This moment is as if the operation that comprises in the interrupt service routine in above-mentioned (1), promptly every T
4＜T
0Time send feeding-dog signal, then needn't be in the aforesaid operations 1 every T
3＜T
0Time send feeding-dog signal, but detect feed dog overtime in CPLD15 only send and once feed the dog instruction, next keep the dog instruction of feeding that CPU12 is not reset and in interrupt service routine, comprise.The dog that feeds that does not comprise in (1) if only comprise the recording instruction in above-mentioned (2) in the interrupt service routine is instructed, and then CPLD15 still need be arranged to every T
3＜T
0Time send feeding-dog signal.
In interrupt service routine, operation irregularity still might take place in CPU12, and this moment, whether CPLD15 should stop to detect CPU12 every T
4Time sends feeds the dog instruction.Can be in CPLD15 setting program, to judge at CPU12 taking place to feed whether CPU12 is in the process of interrupt service routine under the overtime situation of dog.
CPU12 preserves the information of receiving carrying out before the highest priority interrupt signal of task in the interrupt service routine, comprises the title of these tasks, the memory address section that takies, the intermediate data of generation etc.
According to above-mentioned method, the embodiment of the invention provides device and the system that some timers that prevent hardware watchdog overflow.
As shown in Figure 2, the embodiment of the invention provides device that a kind of timer that prevents hardware watchdog overflows, i.e. control device among the figure 21, it comprises detecting unit 211 and reset signal transmitting element 212 among the figure.CPU22 is connected with device 21 by bus 24.Whether detecting unit 211 detection CPU22 promptly do not feed dog with the timer zero clearing of hardware watchdog 23 in setting-up time overtime, to feed dog overtime as CPU22, reset signal transmitting element 212 sends reset signal to hardware watchdog 23 and promptly feeds dog, should reset to avoid CPU22 the interval time of feeding dog less than the timer timing value of hardware watchdog 23, and personnel can study the working condition of CPU22 at this point.
As shown in Figure 3, the embodiment of the invention provides the device that another timer that prevents hardware watchdog overflows, i.e. control device among the figure 31, and it links to each other by bus 34 with CPU32, and detecting unit 311 detects CPU32, and whether to feed dog overtime.That dog has taken place to feed is overtime as CPU32, and look-at-me transmitting element 312 sends the highest priority interrupt signal to CPU32, and this moment, the interrupt response device 321 will respond this highest priority interrupt signal, so CPU32 jumps out from the task of current execution.
As shown in Figure 4, the embodiment of the invention provides the system that a kind of timer that prevents hardware watchdog overflows, and it is made up of the control device among the figure 41, interrupt response device 421 and interruption processing module 422.Control device 41 comprises detecting unit 411, look-at-me transmitting element 412 and reset signal transmitting element 413.Detecting unit 411 detects CPU42, and whether hello dog is overtime, take place to feed dog overtime as CPU42, reset signal transmitting element 413 sends reset signal to hardware watchdog, look-at-me transmitting element 412 sends the highest priority interrupt signal to CPU42, interrupt response device 421 response highest priority interrupt signals among the CPU42 activate interruption processing module 422.Interruption processing module device 422 comprises clear command transmitting element 4221 and record cell 4222, clear command transmitting element 4221 sends clear command to control device 41, after control device 41 was received clear command, reset signal transmitting element 413 sent reset signal to hardware watchdog 43.The information of record cell 4222 record CPU42 performed task before receiving described limit priority external interrupt signal.
According to the method that the embodiment of the invention provides, can also comprise judging unit among Fig. 3 and Fig. 4, be respectively 414 among 313 among Fig. 3 and Fig. 4.If it is overtime that CPU takes place to feed dog, whether judgment unit judges CPU this moment is in the process of highest priority interrupt service, if then detecting unit stops to detect.This moment, managerial personnel need check interrupt handling routine in the system of Fig. 3.In the system of Fig. 4, because include reset signal transmitting element 413, so hardware watchdog 43 still can receive feeding-dog signal.
Because in the prior art, promptly restart under the effect of hardware watchdog after the CPU operation irregularity, the working site is destroyed, thereby can't confirm CPU takes place in which task unusually.The method and system that uses the embodiment of the invention to provide; can avoid restarting immediately after the CPU operation irregularity; and protect the CPU working site by the spontaneous mode of feeding dog of relevant control device; and use the interruption of limit priority to insert relevant handling procedure; make that the relevant information of CPU work is preserved, be convenient to analyze the reason of its operation irregularity.
In addition, hardware watchdog also can monitor the work of other devices except monitoring the work of CPU.The device that is monitored must be able to receive external reset signal and possess limit priority external interrupt function, so just can use the method and system in the embodiment of the invention.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. the method that the timer that prevents hardware watchdog overflows is characterized in that, comprising:
The device that control device detection hardware house dog monitors when arriving setting-up time whether not with the timer zero clearing of hardware watchdog, if control device sends reset signal and/or sends the limit priority external interrupt signal to the device that hardware watchdog monitors to hardware watchdog.
2. the method for claim 1, it is characterized in that, if the device that described hardware watchdog monitors when arriving setting-up time not with described timer zero clearing, judge then whether the device that this moment, described hardware watchdog monitored is in the process of highest priority interrupt service, if, then stop to detect device that described hardware watchdog monitors whether in setting-up time not with described timer zero clearing, if not, then carrying out described control device sends reset signal and/or sends the step of limit priority external interrupt signal to the device that described hardware watchdog monitors to described hardware watchdog.
3. the method for claim 1, it is characterized in that, further comprise after the device that described hardware watchdog monitors is received described limit priority external interrupt signal: the device that described hardware watchdog monitors enters interrupt service routine, sends the instruction of described timer zero clearing and/or writes down the information instruction of device performed task before receiving described limit priority external interrupt signal that described hardware watchdog monitors.
4. the device that the timer that prevents hardware watchdog overflows is characterized in that, comprises detecting unit and reset signal transmitting element, wherein,
Described detecting unit, be used for device that the detection hardware house dog monitors when arriving setting-up time whether not with described timer zero clearing;
Described reset signal transmitting element is used for the device that monitors when hardware watchdog and sends reset signal to hardware watchdog during not with described timer zero clearing when arriving setting-up time.
5. the device that the timer that prevents hardware watchdog overflows is characterized in that, comprises detecting unit and look-at-me transmitting element, wherein,
Described detecting unit, be used for device that the detection hardware house dog monitors when setting-up time whether not with described timer zero clearing,
Described look-at-me transmitting element is used for the device that the device that monitors when hardware watchdog monitors to hardware watchdog during not with described timer zero clearing and sends the highest priority interrupt signal when arriving setting-up time.
6. device as claimed in claim 5, it is characterized in that, also comprise judging unit, be used for if the device that described hardware watchdog monitors when arriving setting-up time not with described timer zero clearing, judge whether the device that this moment, described hardware watchdog monitored is in the process of highest priority interrupt service, if then described detecting unit stops described detection.
7. the device that the timer that prevents hardware watchdog overflows is characterized in that, comprises detecting unit, reset signal transmitting element and look-at-me transmitting element, wherein,
Described detecting unit, be used for device that the detection hardware house dog monitors when arriving setting-up time whether not with described timer zero clearing,
Described reset signal transmitting element is used for the device that monitors when hardware watchdog and sends reset signal to hardware watchdog during not with described timer zero clearing when arriving setting-up time,
Described look-at-me transmitting element, the device that is used for monitoring to hardware watchdog sends the highest priority interrupt signal.
8. device as claimed in claim 7, it is characterized in that, also comprise judging unit, be used for if the device that described hardware watchdog monitors when arriving setting-up time not with described timer zero clearing, judge whether the device that this moment, described hardware watchdog monitored is in the process of highest priority interrupt service, if then described detecting unit stops described detection.
9. the system that the timer that prevents hardware watchdog overflows is characterized in that, comprises control device, interrupt response device and interruption processing module, wherein,
Described control device comprises detecting unit, reset signal transmitting element, look-at-me transmitting element and judging unit, wherein,
Described detecting unit, be used for device that the detection hardware house dog monitors when arriving setting-up time whether with described timer zero clearing,
Described reset signal transmitting element is used for the device that monitors when hardware watchdog and sends reset signal to hardware watchdog during not with described timer zero clearing when arriving setting-up time,
Described look-at-me transmitting element, the device that is used for monitoring to hardware watchdog sends the highest priority interrupt signal,
Described judging unit, be used for if the device that described hardware watchdog monitors when arriving setting-up time not with described timer zero clearing, judge whether the device that this moment, described hardware watchdog monitored is in the process of highest priority interrupt service, if then described detecting unit stops described detection;
Described interrupt response device is used to receive the highest priority interrupt signal;
Described interruption processing module is used for carrying out interrupt service routine when described interrupt response device is received the highest priority interrupt signal.
10. system as claimed in claim 9 is characterized in that described interruption processing module comprises clear command transmitting element and record cell, wherein,
Described clear command transmitting element is used for sending clear command to described control device, and after described control device was received clear command, described reset signal transmitting element sent reset signal to described hardware watchdog;
Described record cell is used to write down the information of device performed task before receiving described limit priority external interrupt signal that described watchdog timer monitors.
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| CN2008100066554A CN101221518B (en) | 2008-01-29 | 2008-01-29 | Method, device and system for preventing timing device overflow of hardware watchdog |
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| WO2014161373A1 (en) * | 2013-04-01 | 2014-10-09 | 中兴通讯股份有限公司 | System fault detection and processing method, device, and computer readable storage medium |
| CN104679606A (en) * | 2015-03-18 | 2015-06-03 | 北京全路通信信号研究设计院有限公司 | Method and device for detecting watchdog circuit |
| CN105630621A (en) * | 2015-12-30 | 2016-06-01 | 宁波三星医疗电气股份有限公司 | Watchdog feeding method |
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| CN104679606B (en) * | 2015-03-18 | 2018-02-09 | 北京全路通信信号研究设计院集团有限公司 | Watchdog circuit detection method and device |
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| CN104679606B (en) * | 2015-03-18 | 2018-02-09 | 北京全路通信信号研究设计院集团有限公司 | Watchdog circuit detection method and device |
| CN105630621A (en) * | 2015-12-30 | 2016-06-01 | 宁波三星医疗电气股份有限公司 | Watchdog feeding method |
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| CN105718326A (en) * | 2016-01-27 | 2016-06-29 | 惠州市德赛西威汽车电子股份有限公司 | Restorability testing method of embedded system |
| CN105718326B (en) * | 2016-01-27 | 2018-12-11 | 惠州市德赛西威汽车电子股份有限公司 | The restorability test method of embedded system |
| CN110554979A (en) * | 2018-05-31 | 2019-12-10 | 瑞昱半导体股份有限公司 | time-piece device and method for operating same |
| CN109062718A (en) * | 2018-07-12 | 2018-12-21 | 联想(北京)有限公司 | A kind of server and data processing method |
| CN110262920A (en) * | 2019-06-28 | 2019-09-20 | 广州鲁邦通物联网科技有限公司 | The indirect dog-feeding method of the external house dog of linux system, house dog feed dog and act on behalf of drive module, watchdog system |
| CN110262920B (en) * | 2019-06-28 | 2021-07-09 | 广州鲁邦通物联网科技有限公司 | Linux system external watchdog indirect feeding method, watchdog feeding agent driving module and watchdog system |
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