KR100240658B1 - Hierarchical controller and interrupt management circuit for high-level synthesis - Google Patents

Abstract

The present invention relates to a hierarchical controller and interrupt processing circuit for higher level synthesis.

The development of ultra-large-scale integration (VLSI) technology allows more than one million devices to be integrated on a single chip, but it is difficult to design such complex chips manually. As features vary and designs become more complex, the need for CAD tools to describe and validate algorithmic behavior of circuits at higher levels and to automatically design by synthesis tools is increasing. Synthetic CAD tools, which are widely applied in the design of integrated circuit (ASIC) design field, are the logic to generate circuit diagram from physical synthesis, logic or state transition information that generate drawing information from netlist. Synthesis is classified into higher-level synthesis that generates schematics from programs that implement algorithms for circuits. Physical synthesis and logic synthesis have been developed and used in the design of integrated circuit (ASIC) for application purpose, but high-level synthesis is actively researched as future technology. The circuit automatically generated by the high level synthesis has the structure of a controller and a data processor.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hierarchical controller and interrupt processing circuit for high-level synthesis capable of handling interrupts for the purpose of application to control-dominated circuits.

Description

Hierarchical Controller and Interrupt Handling Circuit for Higher-Level Synthesis

The present invention relates to a hierarchical controller and interrupt processing circuit for high-level synthesis, and more particularly to a structure of a controller having a hierarchical structure necessary to implement a control-oriented circuit in design automation using high-level synthesis.

The controller of the present invention consists of a main finite state machine (main FSM) block, a sub finite state machine (sub FSM) block, and an interrupt finite state machine block.

In general, the architecture of the system depends on the designer's design style. It also depends on the target architecture on which the higher-level synthesis algorithm or program is based. The members of the architecture used for higher-level synthesis are operators such as Arithmetic Logic Units (ALUs) and multipliers, memory such as registers and RAM, and connectors such as buses and signals. These members are used to implement system algorithms to create various circuits with different areas, performances, and so on.

High-level synthesis is a CAD technology that automates the design of logic circuits for application-specific integrated circuits (ASICs). An algorithm to be implemented using a programming language is used to automatically design logic circuits using register transfer level cells. . Higher-level synthesis starts from higher-level design information than physical or logical synthesis, and automatic design is aimed at a structured structure. The target architecture is largely divided into digital signal processing (DSP) and microcontroller. The former focuses on the synthesis of the signal processor, while the latter focuses on the synthesis of the controller. The controller of the microcontroller is very complicated because the data processing order in the data processor must be determined according to the algorithm execution order. In order to process this complexity programmatically, we introduce a hierarchical structure and model it as a finite state machine that exchanges information. It must also have the ability to handle one or more interrupts. As such, the controller of the microcontroller may have a hierarchical structure in relation to the CAD technology, and the target architecture capable of handling interrupts is differentiated from the conventional technology.

Accordingly, the present invention has a structure of a control-centric circuit such as a microcontroller, wherein the control block that specifies the processing order of the data is composed of primary and secondary interrupt finite state machine blocks, and each finite state machine block operates independently. However, the operation order is controlled in the main finite state machine block, has the function of interrupt priority processing, and provides a hierarchical controller and interrupt processing circuit for hierarchical structure with hierarchical structure to facilitate circuit design and implementation. Its purpose is to.

The present invention for achieving the above object is a main finite state machine block, a plurality of sub finite state machine blocks operated by a plurality of output control signals output from the main finite state machine block, and the sub finite state machine block An oar gate that detects a signal indicating that the operation of the secondary finite state machine is terminated and outputs a control signal to the primary finite state machine block, and transmits an interrupt request signal to the primary finite state machine block, And a plurality of interrupt finite state machine blocks operated according to a process permission signal supplied from the system.

In addition, a first latch circuit for receiving a plurality of input control signals as inputs for the interrupt processing of the main finite state machine block and transferring the control signals to the main finite state machine block according to the first clock; A second latch circuit for transmitting a state value to the main finite state machine block according to a first clock, and a control signal output from the main finite state machine block as an input to output a plurality of control signals according to the second clock; And a third latch circuit. Further, a first NOR gate for inputting an output signal of the interrupt finite state machine block and an upper interrupt signal for interrupt priority processing in the upper and lower interrupt finite state machine blocks, and another output of the interrupt finite state machine block. A second NOR gate for inputting an upper interrupt signal different from the signal, a first AND gate for inputting an output of the second NOR gate, and a global reset signal, an output of the first NOR gate, and an output of the first AND gate A D flip-flop circuit for outputting a control signal in accordance with an output and a second clock, a second and gate for inputting an output of the D flip-flop circuit and a global reset signal, and an output of the second and gate, respectively. And a lower interrupt finite state machine block as an input.

In addition, a first false gate which takes an output of the primary finite state machine block and an output of the secondary finite state machine block as an input for allowing interrupt processing start permission of the primary finite state machine block and the secondary finite state machine block; A NAND gate for outputting the OH gate and a second clock, a second OHAL gate for inputting a plurality of interrupt request signals, a third OHAL gate for inputting a plurality of interrupt termination signals, and the second OL An inverter having an output of a gate as an input, a first AND gate having an output of the inverter and an output of the third OR gate, an output of the second OR gate, an output of the first AND gate, and the NAND A JK type flip-flop circuit having an output of a gate as an input, and a second N & A having an output of the flip-flop circuit and a first clock as an input. Characterized in that configured to include a gate and a third AND gate to the output of the second clock of the JK flip-flop circuit as an input.

1 is a block diagram of a hierarchy controller for higher level synthesis in accordance with the present invention.

2 is a circuit diagram for interrupt processing of a main finite state machine.

3 (a) and 3 (b) are circuit diagrams for interrupt priority processing in upper and lower interrupt finite state machines.

Fig. 4 is a circuit diagram for permission to start processing interrupts in main and minor finite state machines.

<Description of the code | symbol about the principal part of drawing>

1: Main finite state machine block

2A to 2N: Sub Finite State Machine (Sub FSM) Block

3A to 3N: Interrupt Finite State Machine Block

4: OR gate 5: Main finite state machine block

6 to 8: Latch Circuit 11: Interrupt Finite State Machine

12: main finite state machine 13, 14: noah gate

15, 16: AND gate 17: D flip-flop circuit

18: Lower Interrupt Finite State Machine 19: Main Finite State Machine

20: minor finite state machine 21 to 23 oal gate

24: inverter 25, 28, 29: end gate

26: NAND gate 27: JK type flip-flop circuit

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of a hierarchy controller for higher level synthesis in accordance with the present invention. The operations of the sub-finite state machine blocks 2A to 2N are operated according to the plurality of control signals StartSubProc1 to StartSubProcN output from the main finite state machine block 1, and only one signal among the multiple output signals is activated. . When the operation of the sub-finite state machine block receiving the active signal is completed, an operation completion signal (FinishSubProc) is output. According to the signal, the main finite state machine block 1 performs the following operation. Therefore, sequential execution is performed in which only one control signal is active at the same time.

The operation of the interrupt finite state machine blocks 3A to 3N sends an interrupt request signal (RequestInterrupt) to the main finite state machine block 1 and operates when the processing permission signal (ApproveInterrupt) comes.

2 is a circuit diagram for interrupt processing of the main finite state machine, in which input and output control signals are synchronized using a non-overlap two phase clock and latch circuit. The input signal is activated by the first clock Phi1 and the output signal is activated by the second clock phi2. The period of the first clock Phi1 is determined according to the critical path delay of the main finite state machine block 5, and is the main finite state for one period of the next rising period from the rising edge of the second clock Phi2. The output control signal of the machine block 5 is valid. For the operation of the main finite state machine block 5, which is the actual processing part of this block, the input control signal is an external input (ExtIn), an input from the data path (Flag), an input (StartSelf) indicating the start of the finite state machine operation. A first and second latch circuit 6 whose input indicating the completion of the operation of the sub-finite state machine block (FinishSubProc) and the current state value inputs (StateSig) of the main finite state machine block are synchronized to the first clock (Phi1). And 7). In addition, the output control signal of the main finite state machine block 5 includes an output to the outside (ExtOut), an output (lastOP) indicating the end of each control step, and an operation operation of the main finite state machine block 5. It is output by the third latch circuit 8 in synchronization with the second clock Phi2 with an output FinnishSelf for notifying the end of, and an output StartSubProcN for notifying the start of the sub-state machine.

3 (a) and 3 (b) are circuit diagrams for interrupt priority processing in upper and lower interrupt finite state machines.

In FIG. 3 (a), the input / output of the basic interrupt finite state machine block 11 inputs an interrupt request signal ExtInterrupt and an interrupt processing enable signal ApproveInterrupt from the outside to signal an interrupt occurrence and request processing. The lower interrupt cancellation request signal (ResetInferiorInterrupt) and the signal for finishing the interrupt processing (FinishInterrupt) are outputted. If multiple interrupts occur, it is necessary to execute interrupts with higher processing order and cancel lower priority interrupts.

The operations for processing interrupts in the interrupt finite state machine block 12 and the lower interrupt finite state machine block 18 of FIG. 3 (b) are as follows. The operation of the interrupt finite state machine block 12 generates a control signal ResetInferiorInterrupt that cancels the operation of the lower interrupt finite state machine block 18 of lower processing priority than this block. This signal is connected to the set terminal of the D flip-flop circuit 17 so that when the signal is active, the output of the D flip-flop circuit 17 has a value of '1'. The first NOR gate 13 is also used for other interrupt processing above the lower interrupt finite state machine block 18. When the operation of the interrupt finite state machine block 12 is completed, an interrupt processing end signal (FinishInterrupt) is generated. This signal is connected to the clear (clr) terminal of the D flip-flop circuit 17 so that when the signal is active, the output of the D flip-flop 17 has a value of '0'. In addition, a second NOR gate 14 is used for lower interrupt finite state machine block 18 and other upper interrupt processing, and a first AND gate 15 is used for global reset signal processing. do. Accordingly, the lower interrupt finite state machine block 18 is reset when the lower interrupt cancel signal (ResetInferiorInterrupt) or another upper interrupt signal is activated when the global reset signal is activated. When the interrupt processing end signal FinnishInterrupt is activated, the lower interrupt finite state machine block 18 is operable.

4 is a circuit diagram for permission to start processing interrupts in the main and secondary finite state machines. When the operation of the primary finite state machine block 19 or the secondary finite state machine block 20 is completed, the operation completion signal LastOP is activated so that the output of the first OR gate 21 becomes '1'. The result of the NAND gate 26 which inputs this output and the second clock phi2 is the clock of the JK flip-flop circuit 27. When there is an interrupt processing permission request (RequestInterrupt), the JK flip-flop circuit 27 outputs an interrupt processing permission signal (ApproveInterrupt) in accordance with the clock described above. At this time, the interrupt processing permission is output after the instruction currently being executed is completed. The processing permission signal is generated by the second and third AND gates 28 and 29 to which the first and second clocks phi1 and phi2 are input. When the interrupt is processed, a finish signal (FinishInterrupt) is generated, from which the clock signal entering the main finite state machine is normalized.

As described above, the present invention can be used as a target architecture for high-level synthesis by implementing a structure for interrupt processing as a controller having a hierarchical structure. It also has a hierarchical structure, making it easy to design and verify in high level synthesis.

Claims (4)

The main finite state machine block, A plurality of sub-finite state machine blocks operated by a plurality of output control signals output from the main finite state machine block; An oar gate detecting a signal indicating that the operation of the sub-finite state machine is ended from the sub-finite state machine block and outputting a control signal to the main finite state machine block; A layer for higher level synthesis, comprising a plurality of interrupt finite state machine blocks which transmit an interrupt request signal to the main finite state machine block and operate according to a process permission signal supplied from the main finite state machine block Controller of the structure. A first latch circuit for inputting a plurality of input control signals for interrupt processing of the main finite state machine block and transferring the control signals to the main finite state machine block according to a first clock; A second latch circuit for conveying a current state value of a main finite state machine block to the main finite state machine block according to a first clock; And a third latch circuit configured to output a plurality of control signals in accordance with a second clock by using the control signal output from the main finite state machine block as an input. Circuit. A first NOR gate for inputting an output signal and an upper interrupt signal of the interrupt finite state machine block for interrupt priority processing in the upper and lower interrupt finite state machine blocks; A second NOR gate for inputting a higher interrupt signal different from another output signal of the interrupt finite state machine block; A first AND gate configured to receive an output of the second NOR gate and a global reset signal; A D-type flip-flop circuit for outputting a control signal according to an output of the first NOR gate, an output of the first and gate, and a second clock; A second AND gate having an output of the D flip-flop circuit and a global reset signal as inputs, respectively; And a lower interrupt finite state machine block for inputting the output of the second and gate. A first false gate as an input of an output of the primary finite state machine block and an output of the secondary finite state machine block for permission to start interrupt processing of the primary finite state machine block and the secondary finite state machine block; A NAND gate having an output of the first oar gate and a second clock as an input; A second false gate for inputting a plurality of interrupt request signals; A third false gate for inputting a plurality of interrupt termination signals; An inverter having an output of the second false gate as an input; A first end gate having an output of the inverter and an output of the third false gate as an input; A JK flip-flop circuit having an output of the second false gate, an output of the first AND gate, and an output of the NAND gate; A second end gate having an output of the JK flip-flop circuit and a first clock as an input; And a third end gate having an output of the JK flip-flop circuit and a second clock as an input.

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