CN100423269C - 在半导体装置中形成电容器之存储节点的方法 - Google Patents

在半导体装置中形成电容器之存储节点的方法 Download PDF

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Publication number
CN100423269C
CN100423269C CNB2005101172595A CN200510117259A CN100423269C CN 100423269 C CN100423269 C CN 100423269C CN B2005101172595 A CNB2005101172595 A CN B2005101172595A CN 200510117259 A CN200510117259 A CN 200510117259A CN 100423269 C CN100423269 C CN 100423269C
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China
Prior art keywords
insulating barrier
storage node
contact hole
layer
etching
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CNB2005101172595A
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English (en)
Chinese (zh)
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CN1794455A (zh
Inventor
宣俊劦
李圣权
赵诚允
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Covenson wisdom N.B.868 company
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Hynix Semiconductor Inc
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Publication of CN1794455A publication Critical patent/CN1794455A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
CNB2005101172595A 2004-12-20 2005-10-31 在半导体装置中形成电容器之存储节点的方法 Active CN100423269C (zh)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
KR10-2004-0108694 2004-12-20
KR1020040108694 2004-12-20
KR1020040108694A KR100721548B1 (ko) 2004-12-20 2004-12-20 반도체 소자의 캐패시터 스토리지 노드 형성방법
KR10-2004-0110083 2004-12-22
KR1020040110083 2004-12-22
KR1020040112821 2004-12-27
KR10-2004-0112821 2004-12-27

Publications (2)

Publication Number Publication Date
CN1794455A CN1794455A (zh) 2006-06-28
CN100423269C true CN100423269C (zh) 2008-10-01

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CNB2005101172595A Active CN100423269C (zh) 2004-12-20 2005-10-31 在半导体装置中形成电容器之存储节点的方法

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KR (1) KR100721548B1 (ko)
CN (1) CN100423269C (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107195620B (zh) * 2017-05-19 2018-07-06 睿力集成电路有限公司 一种高深径比孔洞的制备方法及结构
US20220399361A1 (en) * 2021-06-10 2022-12-15 Macronix International Co., Ltd. Memory device and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6300191B1 (en) * 2001-02-15 2001-10-09 Taiwan Semiconductor Manufacturing Company Method of fabricating a capacitor under bit line structure for a dynamic random access memory device
US6383863B1 (en) * 2001-09-27 2002-05-07 Taiwan Semiconductor Manufacturing Company Approach to integrate salicide gate for embedded DRAM devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940006682B1 (ko) * 1991-10-17 1994-07-25 삼성전자 주식회사 반도체 메모리장치의 제조방법
JP3943320B2 (ja) * 1999-10-27 2007-07-11 富士通株式会社 半導体装置及びその製造方法
KR20010039179A (ko) * 1999-10-29 2001-05-15 윤종용 반도체 장치의 실린더형 커패시터 스토리지 전극 형성 방법
KR100527401B1 (ko) * 2002-06-03 2005-11-15 주식회사 하이닉스반도체 반도체소자 제조방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6300191B1 (en) * 2001-02-15 2001-10-09 Taiwan Semiconductor Manufacturing Company Method of fabricating a capacitor under bit line structure for a dynamic random access memory device
US6383863B1 (en) * 2001-09-27 2002-05-07 Taiwan Semiconductor Manufacturing Company Approach to integrate salicide gate for embedded DRAM devices

Also Published As

Publication number Publication date
CN1794455A (zh) 2006-06-28
KR20060070069A (ko) 2006-06-23
KR100721548B1 (ko) 2007-05-23

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Owner name: 658868N.B. INC.

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Effective date: 20120620

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Address before: Gyeonggi Do, South Korea

Patentee before: Hairyoksa Semiconductor Co., Ltd.

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Owner name: CONVERSANT INTELLECTUAL PROPERTY N.B.868 INC.

Free format text: FORMER NAME: 658868N.B. INC.

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Address after: new brunswick

Patentee after: Covenson wisdom N.B.868 company

Address before: new brunswick

Patentee before: 658868N.B. company