CN100419842C - Driving apparatus for driving an LCD monitor - Google Patents
Driving apparatus for driving an LCD monitor Download PDFInfo
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- CN100419842C CN100419842C CNB2005100669365A CN200510066936A CN100419842C CN 100419842 C CN100419842 C CN 100419842C CN B2005100669365 A CNB2005100669365 A CN B2005100669365A CN 200510066936 A CN200510066936 A CN 200510066936A CN 100419842 C CN100419842 C CN 100419842C
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Abstract
The present invention provides a driving device for driving a flat panel display apparatus. The driving device comprises a first driving unit, which includes a first output buffer, and a first switch coupled between an output terminal of the first driving unit and an output terminal of the first output buffer; a second driving unit, which includes a second output buffer, and a second switch coupled between an output terminal of the second driving unit and an output terminal of the second output buffer; and a third switch, coupled between an output terminal of the second driving unit and an output terminal of the third output buffer, wherein the third switch can selectively conduct so as to alow the output voltage of the first output buffer and the output voltage of the second output buffer to be an average voltage.
Description
The application is that denomination of invention is " a kind of method and relevant apparatus thereof that drives LCD Panel " (application number: 03122005.3; The applying date: the dividing an application of application on April 21st, 2003).
Technical field
The present invention relates to a kind of drive unit that drives flat display apparatus, particularly a kind of drive liquid crystal board (LCD panel) go up pixel with delegation corresponding to same voltage level to show the evenly device of (uniform) gray-scale value (gray level).
Background technology
Generally speaking, the advantage of LCD Panel includes in light weight, power consumption is few, and low radiation or the like, therefore, LCD Panel has been widely used in multiple on the market portable (protable) information products, and for example (personal digital assistant PDA) waits commodity for mobile computer (notebook) and personal digital assistant.In addition, LCD Panel also replaces the employed cathode-ray tube (CRT) of traditional desktop PC (desktop computer) (cathode ray tube, CRT) display gradually.For LCD Panel, when the orientation (alignment) of liquid crystal molecule (liquid crystal molecule) not simultaneously, then an incident light can be subjected to the influence of this liquid crystal molecule and produce polarization (polarization) in various degree or reflect (refraction) effect, therefore LCD Panel mainly is to utilize the physical characteristics of above-mentioned liquid crystal molecule itself to produce the primaries (ruddiness with different gray-scale values, blue light, and exportable colorful image and green glow).
See also Fig. 1, Fig. 1 is known membrane transistor (thin film transistor, TFT) synoptic diagram of liquid crystal indicator 10.Liquid crystal indicator 10 includes a liquid crystal board (LCD panel) 12, one control circuits 14, one first driving circuits 16, one second driving circuits 18, one first supply units 20, and a second source device 22.Liquid crystal board 12 is made of the liquid crystal cell layer (LCD layer) of two substrates (substrate) and between two substrates, be provided with many data lines (data line) 24 in a substrate, respectively with many gate control lines (gate line) 26 of data line 24 vertical interlaceds, and a plurality of membrane transistor 28.Be placed in electrode (common electrode) altogether the fixed voltage Vcom that is provided via first supply unit 20 is provided on another substrate.For convenience of explanation, only there is a membrane transistor 28 to be shown among Fig. 1, yet, in fact a plurality of membrane transistors 28 are the intervening portions that are arranged at each data line 24 and each gate control lines 26 respectively, and therefore a plurality of membrane transistors 28 are that mode with matrix (matrix) is arranged in the liquid crystal board 12.In other words, each data line 24 is corresponding to row (column) of liquid crystal indicator 10, each gate control lines 26 is corresponding to the delegation (row) of liquid crystal indicator 10, and each membrane transistor 28 is corresponding to the pixel (pixel) on the liquid crystal indicator 10, in addition, the two substrates in the liquid crystal board 12 can be considered as an electric capacity (capacitor) 30 equivalently according to its corresponding operating characteristic.
The driving method of known thin film electrocrystal liquid crystal display device 10 is described below simply, control circuit 14 is used for controlling the driving flow process of liquid crystal indicator 10, when control circuit 14 receives horizontal-drive signal (horizontal synchronization) 32 and vertical synchronizing signal (verticalsynchronization) 34, control circuit 14 is exported corresponding control signal respectively to first driving circuit 16 and second driving circuit 18, then, first driving circuit 16 and second driving circuit 18 just produce the input signal to each data line 24 (for example DL3) and each gate control lines 26 (for example GL3) according to this control signal, with the voltage difference that is kept between the conducting state of controlling corresponding membrane transistor 28 and electric capacity 30 two ends, and change the orientation and the corresponding light transmission features of associated liquid crystal molecule further according to this voltage difference.For instance, second driving circuit, 18 input one signal pulses (corresponding high-voltage level) arrive gate control lines 26 with the corresponding membrane transistor 28 of conducting, so the signal of being exported by first driving circuit 16 just can drive equivalent capacity 30 via the membrane transistor 28 of this conducting, that is first driving circuit, 16 may command are corresponding to the gray-scale value of the pixel of membrane transistor 28.In addition, the unlike signal via first driving circuit, 16 input data transmission lines 24 is the voltage V that is transmitted according to second source device 22
0 '～V
M 'And produce, first driving circuit 16 includes a bleeder circuit (voltage divider) 17 with foundation voltage V
0 '～V
M 'And export a plurality of voltage V
0～V
n, for instance, second source device 22 can produce 10 kinds of different voltage V
0 '～V
9 ', and bleeder circuit 17 can be to above-mentioned voltage V
0 '～V
9 'Carry out the branch press operation and produce 256 kinds of different voltage V at last
0～V
255, then, first driving circuit 16 just according to display driver data 36 in all voltage available V
0～V
255In choose an appropriate voltage and drive membrane transistor 28, generally speaking, different voltages are corresponding to different gray-scale values, therefore via the control of the gray-scale value of each pixel, the image of corresponding display driver data 36 just can be shown on the liquid crystal board 12 at last.
See also Fig. 1 and Fig. 2, Fig. 2 is the synoptic diagram of first driving circuit 16 shown in Figure 1.First driving circuit 16 also includes a voltage selecting circuit 56 and an operational amplification circuit 37, the different voltage V that provided with foundation bleeder circuit 17
0～V
nDrive corresponding membrane transistor 28 respectively.Operational amplification circuit 37 includes a plurality of operational amplifiers (operational amplifier) 44,45,46,47,48,49, each operational amplifier 44,45,46,47,48,49 is used as an output buffer (output buffer), and its yield value (gain) is 1.In addition, each operational amplifier 44,45,46,47,48,49 in operational amplification circuit 37 is electrically connected to corresponding multiplex's selector switch (multiplexer, MUX), (MUX3 as shown in Figure 2～MUX8) is to be arranged among the voltage selecting circuit 56 to this multiplex's selector switch, please note, for convenience of description, therefore only there are six operational amplifiers to be shown among Fig. 2 with corresponding multiplex's selector switch.The control signal D3 that is exported according to control circuit 14 is to D8, the different voltage V that corresponding multiplex's selector switch can be produced by bleeder circuit 17
0～V
nIn choose a specific voltage level, (for example the operation of MUX3～MUX8) can be considered an analog/digital converter (analog-to-digital converter to each multiplex's selector switch, DAC) or demoder (decoder) is to carry out conversion of signals or decode operation to display driver data 36, that is finish the processing of display driver data 36 in multiplex's selector switch after, this multiplex's selector switch just begins by different voltage V according to display driver data 36
0～V
nIn choose a specific voltage level, and export the corresponding pixel of this specific voltage level to one to drive this pixel.Note that each voltage V
0～V
nBe individually to transmit via a power transmission line (plain conductor 66 for example shown in Figure 2), when control circuit 14 receives horizontal-drive signal 32 and vertical synchronizing signal 34, control circuit 14 can produce corresponding signals and also import first and second driving circuit 16,18.For instance, when second driving circuit 18 produces pulses and impels with all the membrane transistor 28 equal conductings in the delegation, first driving circuit 16 is according to display driver data 36 DL3 in the judgment data transmission line 24 further then, DL4, DL5, DL6, DL7, DL8 needs to drive with voltage V1, and drive membrane transistor 38 via operational amplification circuit 27,39,40,41,42,43 trend voltage level V1, so, corresponding operational amplifier 44,45,46,47,48, multiplex's selector switch MUX3 of 49, MUX4, MUX5, MUX6, MUX7, MUX8 then can be controlled to choose required voltage level (for example V1) respectively, and operational amplifier 44,45,46,47,48,49 are used multiplex's selector switch MUX3, MUX4, MUX5, MUX6, MUX7, the selected voltage level (for example V1) of MUX8 is used as its input voltage, and further drives membrane transistor 38,39,40,41,42,43.Yet, each operational amplifier 44,45,46,47,48,49 itself has different output voltage side-play amounts (offset) respectively, so can influence its actual output voltage, that is work as operational amplifier 44,45,46,47,48,49 and all use under the same input voltage V1, the voltage difference difference that can cause electric capacity 50,51,52,53,54,55 two ends to keep at last.In addition, by display driver data 36 as can be known, the pixel of corresponding data transmission line DL3, DL4, DL5, DL6, DL7, DL8 ought to show same gray scale, yet, because the output voltage of operational amplifier 44,45,46,47,48,49 is subjected to its output voltage offset affect respectively and difference, that is each pixel can present uneven intensity profile on display screen and cause the display quality of liquid crystal indicator 10 not good.
Summary of the invention
Therefore fundamental purpose of the present invention is the method and the relevant apparatus thereof that can show even gray-scale value on a kind of driving one liquid crystal board with the pixel of delegation corresponding to same voltage level is provided, to address the above problem.
The invention provides a kind of drive unit that drives flat display apparatus, this drive unit includes: one first driver element, and this first driver element includes: one first output buffer; And one first switch, be connected between the output terminal of the output terminal of this first output buffer and this first driver element; One second driver element, this second driver element includes: one second output buffer; And a second switch, be connected between the output terminal of the output terminal of this second output buffer and this second driver element; And one the 3rd switch, be connected between the output terminal of the output terminal of this first driver element and this second driver element; Wherein the 3rd switch optionally conducting so that output voltage convergence one average voltage of the output voltage of this first output buffer and this second output buffer.
Description of drawings
Fig. 1 is the synoptic diagram of known thin film electrocrystal liquid crystal display device.
Fig. 2 is the synoptic diagram of first driving circuit shown in Figure 1.
Fig. 3 is the synoptic diagram of first kind of operational amplification circuit of the present invention.
Fig. 4 is the synoptic diagram of second kind of operational amplification circuit of the present invention.
Fig. 5 is the synoptic diagram of the third operational amplification circuit of the present invention.
Fig. 6 is operational amplification circuit shown in Figure 5 and the connection diagram between the pixel.
Fig. 7 is the functional block diagram of time schedule controller of the present invention.
Fig. 8 is the time sequential routine figure of time schedule controller shown in Figure 7.
The reference numeral explanation
10 liquid crystal indicators, 12 liquid crystal boards
14 control circuits, 16 first driving circuits
17 bleeder circuits, 18 second driving circuits
20 first supply units, 22 second source devices
24 data lines, 26 gate control lines
28,38,39,40,41,42,43 membrane transistors
30,50,51,52,53,54,55 electric capacity
32 horizontal-drive signals, 34 vertical synchronizing signals
36 display driver data
37,60,70,80 operational amplification circuits
44,45,46,47,48,49,62,72,73,74,75 operational amplifiers
56 voltage selecting circuits, 64 switches
66 plain conductors, 82 pixels
90 time schedule controllers, 92 frequency dividers
94 counters, 96 comparers
98 logic controllers
Embodiment
See also Fig. 1, Fig. 2, and Fig. 3, Fig. 3 is the synoptic diagram of first kind of operational amplification circuit 60 of the present invention.Operational amplification circuit 60 of the present invention is used for replacing the known operational amplification circuit 37 in first driving circuit 16 shown in Figure 2.The detail operations that note that voltage selecting circuit 56 is discussed in above-mentioned prior art paragraph explanation in detail, is not therefore influencing under the disclosed situation of the technology of the present invention, and the tediously long operation instructions of above-mentioned voltage selecting circuit 56 is in following no longer repeated description.Operational amplification circuit 60 includes a plurality of operational amplifiers 62 or a plurality of operation transconductance amplifier (operationaltransconductance amplifier, OTA) with formation output buffer (output buffer), and the yield value that this output buffer has is 1.In addition, operational amplification circuit 60 also includes a plurality of switches (switch) 64 with the Control current path.When second driving circuit 18 is imported a signal pulse (corresponding high-voltage level) to gate control lines 26 according to horizontal-drive signal 32, all membrane transistors 28 that are positioned on this gate control lines 26 all can conducting, then, first driving circuit 16 just can export respectively according to display driver data 36 DL1 of corresponding voltage in the data line 24 to DLn with the corresponding gray-scale value of output on liquid crystal board 12.Simultaneously, multiplex's selector switch of corresponding operational amplifier also can be selected a required voltage (for example V1), and switch 64 also can switch to select conducting two-end-point E1 and E2, so voltage V1 just can drive electric capacity 30 via operational amplifier 62.Yet, can not have a specific output voltage side-play amount because its semiconductor fabrication does not match (mismatch) between each operational amplifier 62, that is to say, under the situation of identical input voltage (for example V1), the output voltage of each operational amplifier 62 can be because different output voltage side-play amounts and difference to some extent, so, DL1 in the data line 24～DLn meeting voltage level corresponding different because of the influence of the output voltage side-play amount of above-mentioned operational amplifier 62, and the pairing electric capacity 30 of the DL1～DLn in the data line 24 just can store different voltage levels.In the present embodiment, switch 64 and then can switch further and conducting end points E1 and E3 to change current path, because the switching state of switch 64 changes, so the voltage V1 that is transmitted via plain conductor 64 just can't continue to drive electric capacity 30 by operational amplifier 62, yet each electric capacity 30 can be electrically connected to same plain conductor 66 owing to the conducting of end points E1 and E3.Therefore, 30 operations that average electric charge via plain conductor 66 apace of all electric capacity, that is all electric capacity 30 can be therefore and corresponding to an average output voltage side-play amount (averaged offset), and have identical voltage level at last.
For instance, switch 64 at first switches to the position of connection end point E1 and E2, if voltage V1 is 5 volts, DL1 in the data line 24, DL2, DL3, the voltage of DL4 then can drive and 5 volts of convergences by the formed output buffers of operational amplifier 62, yet, each operational amplifier 62 itself has different output voltage side-play amounts, so corresponding DL1 in the data line 24, DL2, DL3, the voltage of DL4 also can be inequality, for example, DL1 in the data line 24, DL2, DL3, the voltage of DL4 can become 4.8 volts respectively at last, 5.1 volt, 4.7 volt, 4.9 volt.In present embodiment, switch 64 switches to the position of connection end point E1 and E3 this moment immediately, since DL1 in the data line 24, DL2, DL3, DL4 all is electrically connected to same plain conductor 66 by end points E1 and E3, so DL1 in the corresponding data transmission line 24, DL2, DL3, the different voltage levels of DL4 are the same average voltage of convergence apace, in other words, each DL1 in the data line 24, DL2, DL3, DL4 originally distinguished corresponding 4.8 volts, 5.1 volt, 4.7 volt, 4.9 volt, but make the different voltage levels all can convergence one average voltage via same plain conductor 66.Please note, for above-mentioned each data line 24, original different output voltage side-play amounts then can be distinguished corresponding same average output voltage side-play amount via the auxiliary of plain conductor 66, therefore when the same input voltage of each data line 24 input, for each data line 24, because this input voltage all is subjected to same average output voltage offset affect, therefore each data line 24 all can be driven into same output voltage at last, in addition, if drive via the same voltage that bleeder circuit 17 is produced with the pixel in the delegation, then being somebody's turn to do all can corresponding identical gray-scale value with the pixel in the delegation.
See also Fig. 4, Fig. 4 is the synoptic diagram of second kind of operational amplification circuit 70 of the present invention.Operational amplification circuit 70 includes a plurality of operational amplifiers 72,73,74,75 with as output buffer, please note, for convenience of explanation, only have four operational amplifiers to be shown on Fig. 4, and operational amplifier 72,73,74,75 and switch S 1, S2 are used for via data line DL1, DL2, DL3, DL4 and drive corresponding pixel.The operation of operational amplification circuit 70 is described below, at first, each switch S 1 of conducting is so that operational amplifier 72,73,74,75 are electrically connected to corresponding data line DL1 respectively, DL2, DL3, DL4, as previously mentioned, each operational amplifier 72,73,74,75 have specific output voltage side-play amount separately and influence actual output voltage skew input voltage, in other words, corresponding operational amplifier 72, though 73 pixel uses same input voltage (for example V1) to drive, yet, because operational amplifier 72, the influence of 73 own output voltage side-play amounts and make data line DL1, the voltage of DL2 differs from one another.Then, all switch S 1 of corresponding operational amplifier 72,73,74,75 all are turned off simultaneously, if and operational amplifier 72,73 via data line DL1, DL2 the predetermined same gray-scale value of corresponding pixel convergence that drives, the switch S 2 meeting conductings of then corresponding operational amplifier 72,73, so the voltage level of data line DL1, DL2 can promptly be that original output voltage side-play amount produces the average voltage on data line DL1, the DL2 via average back apace by two same average voltages of different voltage convergences just.Similarly, if operational amplifier 73,74 is the predetermined same gray-scale value of corresponding pixel convergence that drives via data line DL2, DL3, the switch S 2 of then corresponding operational amplifier 73,74 also can conducting, so via the help of switch S 2, any neighbor that driven by same input voltage all can have identical gray-scale value at last.Generally speaking, when about operational amplifier 72,73,74, after 75 switch S 1 conducting, data line DL1, DL2, DL3, the voltage of DL4 can be earlier by corresponding operational amplifier 72,73,74,75 drive, each switch S 2 all can be turned off then, then, if neighbor is scheduled to have same gray-scale value, then to 2 conductings immediately of switch S that should neighbor, the output voltage side-play amount of the operational amplifier by switch S 2 average corresponding adjacent pixel at last, and eliminate voltage error (voltage deviation) between the adjacent data transmission line further.In present embodiment, operational amplification circuit 70 is to be applied to delegation's polarity anti-phase (line inversion) liquid crystal board that driving method was driven, and according to the anti-phase driving method of this row polarity, all have identical polarity (polarity) with the pixel in the delegation, so the voltage level that switch S 2 just on average has same polarity on the adjacent data transmission line (for example DL1, DL2).In addition, in the present embodiment, different output voltage side-play amounts is not the processing that is averaged voltage by voltage selecting circuit shown in Figure 3 56, but average the processing of voltage via relevant switch S 2, so any bleeder circuit of operational amplification circuit 70 required different voltage levels that provides all can be applicable in corresponding first driving circuit 16 of present embodiment.
See also Fig. 5, Fig. 5 is the synoptic diagram of the third operational amplification circuit 80 of the present invention.The class of operation of operational amplification circuit 80 is similar to operational amplification circuit shown in Figure 4 70, and only is the arrangement mode difference of switch S 1, S2.As shown in Figure 5, there is a switch S 2 to be electrically connected two operational amplifiers 72,74, and another switch S 2 is electrically connected to two operational amplifiers 73,75, that is to say, in the present embodiment, adjacent data transmission line (DL1 for example, DL2) be not to connect via switch S 2, when pixel via a single-point polarity anti-phase (dot inversion) driving method, a pair of point polarity anti-phase (two dot lineinversion) driving method, or a row polarity anti-phase (column inversion) is when driving method drives, be to drive by the voltage of opposed polarity respectively then with the neighbor in the delegation, that is to say, be connected to data line DL1, DL2, DL3, the corresponding following polar relationship "+" "-" "+" "-" or "-" "+" "-" "+" of the pixel of DL4.So, when driving the same gray-scale value of pixel convergence of corresponding identical polar, operational amplification circuit 80 is to use switch S 2 to connect the adjacent operational amplifier of corresponding same polarity to be used for average aforesaid output voltage side-play amount, for instance, if be connected to data line DL1, the pixel of DL3 is scheduled to have same gray-scale value, then corresponding operational amplifier 72,74 switch S 1 just can the guide at the beginning the time passes to makes same input voltage driving data transmission line DL1, the voltage level of DL3, because operational amplifier 72, the 74 output voltage side-play amount differences that have itself are so cause data line DL1, voltage level on the DL3 also can be inconsistent.Then, switch S 1 shutoff of corresponding data transmission line DL1, DL3 and switch S 2 conductings simultaneously of corresponding data transmission line DL1, DL3 are so the output voltage side-play amount of operational amplifier 72,74 is in the voltage error that can eliminate after the average treatment between data line DL1, the DL3.Please note, the different output voltage side-play amounts of operational amplifier 72,74 are to produce an average voltage at last via average treatment on two data line DL1, DL3, in other words, in present embodiment, data line DL1, DL3 still have an average output voltage side-play amount respectively, but the voltage level on data line DL1, the DL3 is identical.In addition, if two adjacent pixels (corresponding same polarity) are not to be scheduled to be driven to same gray-scale value, the switch S 2 that then is connected between the two adjacent pixels is understood the gray-scale value that keeps off states and do not influence this neighbor.In the present embodiment, switch S 2 is connected to two data lines with same polarity driven, and be separated with the data line that another drives with opposite polarity between this two data line between then, that is to say, operational amplification circuit 80 is to can be applicable to the anti-phase driving method of single-point polarity, the anti-phase driving method of a pair of point polarity, or on the liquid crystal board that driven of the anti-phase driving method of a row polarity.In addition, in the present embodiment, different output voltage side-play amounts is not the processing that is averaged voltage by voltage selecting circuit shown in Figure 3 56, but average the processing of voltage via relevant switch S 2, so any bleeder circuit of operational amplification circuit 80 required different voltage levels that provides all can be applicable in corresponding first driving circuit 16 of present embodiment.
See also Fig. 6, Fig. 6 is operational amplification circuit 80 shown in Figure 5 and the connection diagram between the pixel 82.A known particular color is by generation that primaries mixes, for example by the ruddiness of varying strength, blue light, and the different color of green glow mixing generation, so 82 of pixels that are arranged at same row must individually provide corresponding ruddiness, blue light, and the gray-scale value of green glow to be to show different colors, and as shown in Figure 6, a plurality of pixels 82 are used for representing a color sequence " RGBRGBRGBRGB ".When pixel 82 via the anti-phase driving method of a single-point polarity, the anti-phase driving method of a pair of point polarity, or the anti-phase driving method of a row polarity is when driving, two close pixels 82 have opposed polarity, for example with the pixel 82 of delegation according to a polarity order "+-+-+-+-+-" and be driven, for ruddiness, pixel 82a, 82c has identical polar "+", and pixel 82b, 82d has identical polar "-", and for the pixel 82a that is used for showing ruddiness, 82b, 82c, 82d, one switch S 2 is connected to the pixel 82a that drives with same polarity "+", between the 82c, in addition, another switch S 2 is connected to the pixel 82b that drives with same polarity "-", between the 82d.So, when operational amplification circuit 80 drives corresponding one specific monochromatic a plurality of pixel, for the neighbor with same polarity driven and predetermined corresponding same gray-scale value, the driving voltage of 2 responsible these neighbors of average driving of switch S.Note that the method for above-mentioned driving pixel also can similarly be applied to drive the pixel of corresponding green glow and blue light, and the operation of the pixel of corresponding green glow of associated drives and blue light is identical with the operation of the pixel that drives corresponding ruddiness, therefore no longer repeats to give unnecessary details.
As mentioned above, operational amplification circuit 70 is to be applied to go the liquid crystal indicator that the anti-phase driving method of polarity driven, operational amplification circuit 80 then is applied to the anti-phase driving method of row polarity, the anti-phase driving method of single-point polarity, or the liquid crystal indicator that driven of the anti-phase driving method of two point polarity.In other words, operational amplification circuit of the present invention can be applicable to use the problem that the liquid crystal indicator of an intended pixel driving method is brought with the output voltage side-play amount that solves known operational amplifier.In addition, also include an XOR (exclusive OR in the liquid crystal indicator disclosed by the invention, XOR) whether a logical circuit or a comparer (comparator) need conducting or shutoff to be used for determine switch S2, that is this XOR circuit be used for comparison about the numeral of two pixels input display driver data judging whether two pixels need be driven into same gray-scale value, and this comparer be used for comparison about the analog input display driver data of two pixels to judge whether two pixels need be driven into same gray-scale value.When this XOR circuit or this comparer are confirmed that two pixels are predetermined and are driven into same gray-scale value, the switch S 2 of corresponding two pixels just can conducting with of the influence of the different output voltage side-play amounts of further elimination to actual image display quality, in other words, liquid crystal indicator disclosed by the invention includes a testing circuit, the XOR circuit of for example corresponding numeral input display driver data or the comparer of corresponding analog input display driver data, be used for the input display driver data of comparison about two pixels, when two pixels are predetermined when having the same grayscale value, switch S 2 can be switched on according to comparative result that this XOR circuit or this comparer produced.In addition, (operational transconductance amplifier OTA) replaces operational amplifier to drive pixel also can to use operation transconductance amplifier in the operational amplification circuit of the present invention.
See also Fig. 8, Fig. 8 is the time sequential routine figure of time schedule controller 90 shown in Figure 7, and from top to bottom shows five waveforms.The horizontal-drive signal 32 that the representative of first waveform is shown in Figure 1, start a gate control lines 26 with deciding, known each gate control lines 26 is triggered and is started by horizontal-drive signal 32, and begins to drive the pixel that is positioned on the same gate control lines 26 after gate control lines 26 is activated.In addition, in the present embodiment, negative edge (falling edge) in horizontal-drive signal 32 is the operation of a corresponding gate control lines 26, for example this gate control lines 26 will be started by second driving circuit 18, and first driving circuit 16 begins to drive the pixel that is positioned on this gate control lines 26 and distinguishes the corresponding gray-scale value of convergence.Each gate control lines 26 is to be activated in order and repeatedly, that is a gate control lines 26 is to be started by horizontal-drive signal 32 termly so that ceaselessly drive position pixel thereon.As shown in Figure 8, one gate control lines is activated a drive cycle (driving period) in time T 1, and another gate control lines is activated another drive cycle in time T 2, and wherein the interval between time T 2 and the time T 1 is the drive cycle that horizontal-drive signal 32 drives a gate control lines 26.Second waveform is represented clock signal clk 1, and the output signal 102 that the 3rd waveform representative frequency divider 92 shown in Figure 7 is exported, significantly, the frequency of output signal 102 is half of frequency of clock signal clk 1, in other words, the control signal Pd of input frequency divider 92 is that setting divisor N1 is 2.If counter 94 obtains its desired count value N2 (being set at 8), then counter 94 can be exported corresponding signal C0, C1, C2, C3 is to comparer 96, so control signal Pc also input comparator 96 to set the signal C0 of corresponding count value N2, C1, C2, the fiducial value N3 of C3, as shown in the figure, the 4th waveform is represented output signal 104, and before counter 94 obtains the numerical value 8 of count value N2, output signal 104 can keep (hold) logical value " 1 ", yet, when the numerical value of counter 94 acquisition count value N2 equals 8,104 of output signals change logical value " 0 " in time T 3 into by logical value " 1 ", output signal 104 can keep logical value " 0 " between time T 3 and time T 2 simultaneously, and in horizontal-drive signal 32 in time T 2 when starting another gate control lines, counter 94 and comparer 96 can be reset (reset) and reply its original state, promptly be counter 94 periodicity of count output signal 102 again, and comparer 96 is exported original initial logic value " 1 " again.The 5th waveform is represented the voltage level on the data line, and when time T 1, first driving circuit 16 begins to drive a pixel by voltage V
1To voltage V
254, and this pixel to be exchange ground (alternatively) drive to avoid known flicker (flicker) problem with the magnitude of voltage of opposite polarity.About switch shown in Figure 3 64, switch 64 be by logic controller 98 controls with foundation output signal 104 connection end point E1 and E2, that is when output signal 104 is transformed into logical value " 1 " by logical value " 0 ", logic controller 98 orders about switch 64 connection end point E1 and E2, and operational amplifier 62 is just according to voltage V
254Drive corresponding pixel, so behind time t4, the driving voltage of importing this pixel can convergence voltage V
254, and output signal 104 is converted to logical value " 0 " by logical value " 1 " when time T 3, and logic controller 98 detects above-mentioned logic level transformation simultaneously, and therefore after time T 3, logic controller 98 can order about switch 64 connection end point E1 and E3.As previously mentioned, because with same voltage V
254The a plurality of pixels that drive are via this voltage of transmission V
254Plain conductor and be electrically connected mutually, so after time T 5, these a plurality of pixels are predetermined towards predetermined voltage V
254The actual driving voltage that drives then can reach this predetermined voltage of convergence V at last via average treatment
254An average voltage (V for example
a).With compare the last time driving between time T 2 and time T 1 operation, another that this pixel can be after time T 2 drives in the operation by the driven of opposite polarity to avoid producing the problem of known flicker.As mentioned above, frequency divider 92, counter 94, and comparer 96 is used for producing this output signal 104, and logic controller 98 is controlled the operation of switch shown in Figure 3 64 according to output signal 104, output signal 104 can be via suitable divisor N1 in the time T 1 and the duration of T3 maintenance logical value " 1 ", count value N2, and fiducial value N3 adjusts.In addition, in the present embodiment, operational amplifier 62 no longer is used for driving pixel after time T 3, therefore present embodiment can be in time T 3 to the associative operation voltage that interrupts input operational amplifier 62 between the time T2, and for example the required bias voltage (biasvoltage) of drives interrupts operational amplifier 62 is to reduce the overall power consumption of operational amplification circuit.Because different liquid crystal indicators itself has its particular electrical circuit load (loading), in other words, compare with another liquid crystal indicator, one liquid crystal indicator may need the long period to drive pixel to reach predetermined gray-scale value, and time T 1 is the corresponding drive cycle of operational amplifier 62 to time T3, so for liquid crystal indicator with less circuit load, its required time T 1 is shorter to the interval of time T3, therefore time schedule controller 90 just can be via suitable adjustment so that time T 1 to corresponding short interval between the time T3, operational amplifier 62 interrupts its operating voltage to reach purpose of power saving in just can be in time T 3 to the interval of time T2, similarly, for liquid crystal indicator with big circuit load, its required time T 1 is longer to the interval of time T3, so time schedule controller 90 just can be via suitable adjustment so that time T 1 reaches required gray-scale value to corresponding long interval between the time T3 so that successfully drive pixel, so operational amplifier 62 interrupts its operating voltage to reach purpose of power saving in just also can be in time T 3 to the interval of time T2.By above-mentioned narration as can be known, same time schedule controller of the present invention 90 can be applicable to various liquid crystal indicators with different circuit loads, and the waveform of output signal 104 is adjustable, reaches best power saving ability (optimum power saving capacity) so that meet the specific driving demand of each liquid crystal indicator.Fig. 4 is similar to switch shown in Figure 3 62 to the running program of switch S shown in Figure 61, S2, in time T 1 to time T3, switch S 1 is switched on so that operational amplifier 72,73,74,75 can drive corresponding pixel, when time T 3, switch S 1 is turned off, and arrive with a rank value with same input voltage driving neighbor if operational amplifier is predetermined before time T 3, then to the also conducting simultaneously of the switch S 2 of right neighbor, the voltage that therefore drives neighbor just can be in time T 3 to T2 by on average and all corresponding to an average voltage.Similarly, operational amplifier 72,73,74,75 also no longer is used for driving pixel after time T 3.In the present embodiment, the operating voltage of output operational amplifier 72,73,74,75 (for example bias voltage) can interrupt input to reduce power consumption, in addition, also can cut off be used in second source device 22 and bleeder circuit 17 the power supply significantly to reduce power consumption, and can come appropriateness to adjust the period of time T 1 to T3 according to the circuit load of liquid crystal indicator, and by divisor N1 in the time schedule controller 90, count value N2, and the suitable setting of fiducial value N3 makes liquid crystal indicator can save maximum power.
Compare with known technology, driving method use switch of the present invention connects the output terminal of output buffer, so the exportable target voltage level of supply unit drives with a plurality of pixel convergence same target voltage levels in the delegation.Though the magnitude of voltage of the output terminal of different driving element is inconsistent because of the output voltage offset affect of this driving element itself, yet when the output terminal of output buffer auxiliary and when being electrically connected mutually via switch, the different magnitudes of voltage of the output terminal of original each driving element can drive towards the average voltage of this difference magnitude of voltage, although this average voltage may not be accurately to equal this target voltage level, but can make all corresponding at last same average voltage of pixel that is positioned at delegation and is scheduled to drive towards same target voltage standard via driving method of the present invention, so driving method of the present invention can solve known because gray scale output consistance (uniformity) problem that different output voltage side-play amounts are brought.In addition, behind the operation start of average voltage, relevant output buffer (for example operational amplifier) no longer needs to be used for driving pixel in the operating process of average voltage, so driving method of the present invention just cuts off the operating voltage (for example driving the bias voltage of this output buffer) of this output buffer to reduce power consumption behind the operation start of average voltage.Moreover, driving method of the present invention uses time schedule controller to decide the starting time of average voltage operation, and this starting time can be adjusted further via the setting value of this time schedule controller of control input, so that meet the demand of the liquid crystal indicator of different circuit loads.Via the adjustment of suitable starting time, corresponding liquid crystal indicator just can have maximum power saving ability.
The above only is the preferred embodiments of the present invention, and all equivalences of making according to claims of the present invention change and revise, and all should belong to covering scope of the present invention.
Claims (14)
1. drive unit that drives flat display apparatus, this drive unit includes:
One first driver element, this first driver element includes:
One first output buffer; And
One first switch, the output terminal and this first driving that are connected this first output buffer are single
Between the output terminal of unit;
One second driver element, this second driver element includes:
One second output buffer; And
One second switch is connected between the output terminal of the output terminal of this second output buffer and this second driver element; And
One the 3rd switch is connected between the output terminal of the output terminal of this first driver element and this second driver element;
Wherein the 3rd switch optionally conducting so that output voltage convergence one average voltage of the output voltage of this first output buffer and this second output buffer.
2. drive unit as claimed in claim 1, this drive unit also includes:
One testing circuit is with deciding the whether conducting of the 3rd switch.
3. drive unit as claimed in claim 1, wherein said first driver element and described second driver element are non-conterminous.
4. drive unit as claimed in claim 2, wherein said first driver element is according to one first driven, described second driver element is according to one second driven, and described testing circuit determines the whether conducting of the 3rd switch according to this first voltage and this second voltage.
5. drive unit as claimed in claim 4, wherein if described first voltage is identical with described second voltage, then described the 3rd switch is understood conducting with the output terminal that connects described first driver element and the output terminal of this second driver element.
6. drive unit as claimed in claim 2, wherein said first driver element is according to one first display driver data-driven, described second driver element is according to one second display driver data-driven, and described testing circuit determines the whether conducting of described the 3rd switch according to the described first display driver data and this second display driver data.
7. drive unit as claimed in claim 6, wherein if the described first display driver data are identical with these second display driver data, then described the 3rd switch is understood conducting with the output terminal that connects this first driver element and the output terminal of described second driver element.
8. drive unit as claimed in claim 1 also comprises:
Time schedule controller is used for controlling the driving of a plurality of pixels of described flat display apparatus, and described time schedule controller includes:
One frequency divider is used for according to a predetermined divisor frequency of the clock signal of importing this frequency divider being carried out frequency division and being produced an output signal;
One counter is used for that this output signal is produced a count value and counts;
One comparer is used for relatively this count value and a fiducial value; And
One logic controller is used for disconnecting described first switch and second switch according to the comparative result of this comparer, and closed the 3rd switch.
9. drive unit as claimed in claim 8, wherein said frequency divider includes an input port, and being used for receiving a control signal should predetermined divisor to set.
10. drive unit as claimed in claim 8, wherein said comparer includes an input port, is used for receiving a control signal to set described fiducial value.
11. drive unit as claimed in claim 8, wherein said time schedule controller also includes a logic controller, it includes a first input end mouth to receive the comparative result that this comparer is exported, and this logic controller judges according to this comparative result whether this count value equals this fiducial value.
12. drive unit as claimed in claim 11, wherein said logic controller also include one second input port, are used for receiving an external timing signal, and whether described logic controller disconnects this first switch according to this external timing signal decision.
13. drive unit as claimed in claim 12, wherein said logic controller also includes one the 3rd input port, be used for receiving one and choose control signal, the described control signal of choosing is used for controlling this logic controller and uses described comparative result or described external timing signal.
14. drive unit as claimed in claim 8, the operating voltage of wherein said first output buffer stops to import this first output buffer according to the comparative result of this comparer.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/064,207 | 2002-06-21 | ||
| US10/064,207 US7102608B2 (en) | 2002-06-21 | 2002-06-21 | Method and related apparatus for driving pixels located in a row of an LCD panel toward the same average voltage value |
| US10/065,665 | 2002-11-07 | ||
| US10/065,665 US7136039B2 (en) | 2002-06-21 | 2002-11-07 | Method and related apparatus for driving an LCD monitor |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031220053A Division CN100498906C (en) | 2002-06-21 | 2003-04-21 | Method and related apparatus for driving an LCD monitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1670811A CN1670811A (en) | 2005-09-21 |
| CN100419842C true CN100419842C (en) | 2008-09-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100669365A Expired - Fee Related CN100419842C (en) | 2002-06-21 | 2003-04-21 | Driving apparatus for driving an LCD monitor |
| CNB031220053A Expired - Fee Related CN100498906C (en) | 2002-06-21 | 2003-04-21 | Method and related apparatus for driving an LCD monitor |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031220053A Expired - Fee Related CN100498906C (en) | 2002-06-21 | 2003-04-21 | Method and related apparatus for driving an LCD monitor |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2004029752A (en) |
| CN (2) | CN100419842C (en) |
| TW (1) | TWI254899B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8144100B2 (en) | 2003-12-17 | 2012-03-27 | Samsung Electronics Co., Ltd. | Shared buffer display panel drive methods and systems |
| US8179345B2 (en) | 2003-12-17 | 2012-05-15 | Samsung Electronics Co., Ltd. | Shared buffer display panel drive methods and systems |
| NL1027799C2 (en) * | 2003-12-17 | 2008-01-08 | Samsung Electronics Co Ltd | Source line driving method for display apparatus, involves driving another source line alternatively using buffer connected to source line, based on comparison of hue data |
| JP4179194B2 (en) * | 2004-03-08 | 2008-11-12 | セイコーエプソン株式会社 | Data driver, display device, and data driver control method |
| KR100614661B1 (en) | 2005-06-07 | 2006-08-22 | 삼성전자주식회사 | Source driver output circuit of liquid crystal device and driving method of data line |
| KR101182538B1 (en) * | 2005-12-28 | 2012-09-12 | 엘지디스플레이 주식회사 | Liquid crystal display device |
| US20080165171A1 (en) | 2007-01-09 | 2008-07-10 | Himax Technologies Limited | Display Driving Circuit and Method Thereof |
| US7911435B2 (en) * | 2007-03-28 | 2011-03-22 | Himax Technologies Limited | Display and source driver thereof |
| JP5319100B2 (en) * | 2007-10-31 | 2013-10-16 | ローム株式会社 | Source driver and liquid crystal display device using the same |
| JP4775408B2 (en) * | 2008-06-03 | 2011-09-21 | ソニー株式会社 | Display device, wiring layout method in display device, and electronic apparatus |
| JP4595008B2 (en) | 2008-08-12 | 2010-12-08 | ティーピーオー ディスプレイズ コーポレイション | Display device, electronic device, electronic system |
| KR20140127666A (en) * | 2013-04-25 | 2014-11-04 | 주식회사 실리콘웍스 | Display driving circuit and display device |
| CN104464597B (en) | 2014-12-23 | 2018-01-05 | 厦门天马微电子有限公司 | Multiplexer circuit and display device |
| CN106841993B (en) * | 2017-02-16 | 2019-09-06 | 泰州镭昇光电科技有限公司 | A kind of LCD detection device and method |
| CN109496427B (en) * | 2018-10-25 | 2021-04-27 | 深圳市汇顶科技股份有限公司 | Image sensor and sensing method thereof |
| CN111524487B (en) * | 2019-02-01 | 2021-07-27 | 上海和辉光电股份有限公司 | Data driving circuit, method and display panel |
| US10991290B1 (en) * | 2020-10-07 | 2021-04-27 | Novatek Microelectronics Corp. | Control method of channel setting module applied to display panel |
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- 2003-04-21 JP JP2003116058A patent/JP2004029752A/en active Pending
- 2003-04-21 CN CNB2005100669365A patent/CN100419842C/en not_active Expired - Fee Related
- 2003-04-21 CN CNB031220053A patent/CN100498906C/en not_active Expired - Fee Related
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2004029752A (en) | 2004-01-29 |
| CN1670811A (en) | 2005-09-21 |
| CN100498906C (en) | 2009-06-10 |
| CN1467699A (en) | 2004-01-14 |
| TW200400484A (en) | 2004-01-01 |
| TWI254899B (en) | 2006-05-11 |
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