1254899 九、發明說明： 【發明所屬之技術領域】 本發_._動-《顯示f幕MW di_ 麵it〇r，LCD臟it0r)之方法及其相關裝置，尤指一種可驅動液 晶面板（LCDpanel)上同-行之像讀應於同—糕位準以顯示 均勻（uniform)灰階值（graylevel)之方法及其相關裝置。 【先前技術】 一般而言，液晶顯示螢幕的優點包括有重量輕，功率消 耗少，以及低輻射等等，因此，液晶顯示螢幕已廣泛地應 用於市面上多種可攜式（portable)資訊產品，倒如筆記型 電月給（notebook )以及個人數位助理（personai digital assistant，PDA)等商品。此外，液晶顯示螢幕亦已逐漸取 代傳統桌上型電腦（desktop computer )所使用的陰極射線 管（cathode ray tube，CRT )顯示器。對於液晶顯示螢幕來 說，當液晶分子（liquid crystal molecule )的排列方向 (alignment)不同時，則一入射光會受該液晶分子的影響 而產生不同程度的偏振（polarization)或折射（refraction) 效應，因此液晶顯示螢幕主要係利用上述液晶分子本身的 物理特性來產生具有不同灰階值的三原色光（紅光’藍光’ 以及綠光），並且可輸出多彩的影像。 1254899 請參閱圖一’圖一為習知薄膜電晶體（thin film transistor, TFT)液晶顯不裝置10的不意圖。液晶顯示裝置ι〇包含 有一液晶面板（LCD panel) 12，一控制電路14，一第一驅 動電路16, 一第二驅動電路18，一第一電源供應裝置20， 以及一第二電源供應裝置22。液晶面板12係由兩基板 · (substrate )以及一介於兩基板之間的液晶元件層（LCD layer)所構成，於一基板上設置有複數條資料傳輸線.（data φ line) 24，分別與資料傳輸線24垂直交錯的複數條閘極控 制線（gate line) 26，以及複數個薄膜電晶體28。一共用 電極（common electrode)係安置於另一基板上來輸出經由 第一電源供應裝置20所提供的固定電壓Vcom。為了便於 說明，僅有一薄膜電晶體28顯示於圖一中，然而，實際上 複數個薄膜電晶體28係分別設置於每一資料傳輸線24與 每一閘極控制線26的交錯位置，因此複數個薄膜電晶體春 28係以矩陣（matrix)的方式排列於液晶面板12中。換句 話說，每一資料傳輸線24對應於液晶顯示裝置1〇之一列 (column)’每一閘極控制線26對應於液晶顯示裝置1〇之 一灯（row)’以及每一薄膜電晶體28係對應於液晶顯示裝 置ίο上之像素（pixel)，此外，液晶面板12中的兩基板 可依據其對應的操作特性而可等效地視為一電容 1254899 (capacitor) 30 習知薄膜電晶體液晶顯示裝置10 衣直川的驅動方法簡單地描 述如下’控制電路14係絲控制液晶顯示mo的驅動 流程，當控制電路14接收皮卓π也 收水十冋步訊號（horizontal synchronization ) 32 以及垂吉 n 心 I置同步訊號（vertical 訊號至第一麟電路16以及第二驅動電路18’然後’第 一驅動電路16與第二驅動電路18便 。 生輸入訊號予每-資料傳輸線24 Ί ⑻虎而產 Α 1例如DL3)以及每一閘 =:=—)以控制相對應薄_體則 導通狀纽及電容30兩端之間所保1254899 IX. Description of the invention: [Technical field to which the invention pertains] The method of the present invention _._动-"displaying the screen MW di_face it〇r, LCD dirty it0r) and related devices, especially a liquid crystal panel ( LCDpanel) The method of reading the same-line image should be the same as the method of displaying the uniform gray level and its related devices. [Prior Art] In general, the advantages of the liquid crystal display screen include light weight, low power consumption, low radiation, and the like. Therefore, the liquid crystal display screen has been widely used in a variety of portable information products on the market. It is like a notebook, a notebook, and a personal digital assistant (PDA). In addition, liquid crystal display screens have gradually replaced the cathode ray tube (CRT) displays used in traditional desktop computers. For a liquid crystal display screen, when the alignment of liquid crystal molecules is different, an incident light is affected by the liquid crystal molecules to cause different degrees of polarization or refraction. Therefore, the liquid crystal display screen mainly utilizes the physical characteristics of the liquid crystal molecules themselves to generate three primary color lights (red 'blue light' and green light) having different gray scale values, and can output a colorful image. 1254899 Please refer to FIG. 1 ' is a schematic view of a conventional thin film transistor (TFT) liquid crystal display device 10. The liquid crystal display device ι includes a liquid crystal panel (LCD panel) 12, a control circuit 14, a first driving circuit 16, a second driving circuit 18, a first power supply device 20, and a second power supply device 22. . The liquid crystal panel 12 is composed of two substrates and a liquid crystal element layer (LCD layer) interposed between the two substrates. A plurality of data transmission lines (data φ line) 24 are disposed on a substrate, respectively. The transmission line 24 is vertically interleaved with a plurality of gate lines 26 and a plurality of thin film transistors 28. A common electrode is disposed on another substrate to output a fixed voltage Vcom supplied via the first power supply device 20. For convenience of explanation, only one thin film transistor 28 is shown in FIG. 1. However, in practice, a plurality of thin film transistors 28 are respectively disposed at the staggered positions of each of the data transmission lines 24 and each of the gate control lines 26, and thus a plurality of The thin film transistor spring 28 is arranged in a matrix on the liquid crystal panel 12. In other words, each of the data transmission lines 24 corresponds to a column of the liquid crystal display device 1 'each of the gate control lines 26 corresponding to one of the liquid crystal display devices 1 ' and each of the thin film transistors 28 Corresponding to the pixel on the liquid crystal display device, in addition, the two substrates in the liquid crystal panel 12 can be equivalently regarded as a capacitor 1254899 (capacitor) according to their corresponding operational characteristics. 30 Conventional thin film transistor liquid crystal The driving method of the display device 10 Yi Zhichuan is simply described as follows: 'The control circuit 14 controls the driving flow of the liquid crystal display mo, and when the control circuit 14 receives the skin π, it also receives the horizontal synchronization signal (horizontal synchronization) 32 and The heart I sets the synchronization signal (vertical signal to the first lining circuit 16 and the second driving circuit 18' and then the first driving circuit 16 and the second driving circuit 18. The input signal is sent to each data transmission line 24 8 (8) Α 1 such as DL3) and each gate =:=-) to control the corresponding thin _ body, the conduction state and the capacitor 30 are protected between the two ends
地依據該絲更動相驗晶分子的排^ 進一 V 的透光特性。舉例來說，第二 ^方向與相對應 初电路18輪入一訊號脈衝 (對應尚電壓準位）至閘極控制線 曰以導通相對應薄膜電 驅動電路16所輪出的訊號便可經由 2通的相電晶體28_料效電容3() 號係根據第_ 15動電路16輸入資料傳輸線24的不同訊 ^第源供縣置22所傳輸的㈣n而產 弟一驅動電路16包含有—分㈣路（痛gedivider) 1254899 17以依據電I vG，〜Vm，而輸出複數個電壓n，舉例來 說’第一電源供應裝置22可產生10種不同電壓V0，〜V9,， 而分壓電路17可對上述電壓ν〇,〜V9,進行分壓操作而最後 產生256種不同電壓ν〇〜V255，然後，第一驅動電路16便 依據顯不驅動資料36而於所有可用電壓V。〜V255中選取-適當電壓來驅動薄膜電晶體28，-般而言，不同電壓係對 應於不同的灰階值’因此經由各像素之灰階值的控制，對 應顯不驅動貧料36的影像最後便可顯示於液晶面板12上。 •请參閱圖一與圖二，圖二為圖一所示之第一驅動電路16 的不意圖。第一驅動電路16另包含有一電壓選擇電路56 以及一運算放大電路37，以依據分壓電路17所提供的不 同電壓v〇〜vn來分別驅動相對應薄膜電晶體28。運算放大 電路37包3有複數個運算放大器（ampimer) 44、45、46、47、48、49，每一運算放大器 44、45、46、 47 48 49係用來作為一輸出緩衝器（〇叫如buffer)，其 增益值（gain)為1。此外，於運算放大電路37中的每一 運算放大器44、45、46、47、48、49係電連接於一相對應 多工選擇器（multiplexer, MUX)，該多工選擇器（如圖二 所示之MUX3〜MUX8)係設置於電壓選擇電路56之中， 請注意，為了方便說明，因此僅有六個運算放大器與相對 1254899 應多工選擇器顯示於圖二中。依據控制電路14所輸出的控 制訊號D3至D8’相對應多工選擇器會由分壓電路17所產 生之不同電壓V〇〜Vn中選取一特定電壓準位，每一多工選 擇器（例如MUX3〜MUX8)的運作可視為—類比/數位轉換 器（anal〇g_to_digital converter, DAC)或是解碼器（dec〇der) 以對顯示驅動資料36進行訊號轉換或解碼操作，亦即於多 工選擇器完成顯示驅動資料36的處理後，該多工選擇器便 依據顯示驅動資料3 6而開始由不同電壓〜％中選取一特 定電壓準位’並且輸出該特定電壓準位至一相對應像素以 驅動該像素。請注意，每一電壓V〇〜Vn係個別地經由一電 源傳輸線（例如圖二所示之金屬導線66)而傳送，當控制 電路14接收到水平同步訊號32以及垂直同步訊號％，控 制電路14會產生相對應訊號並輸入第一、二驅動電路16、 18。舉例來說，當第二驅動電路w產生一脈衝而促使同一 行上的所有薄膜電晶體28均導通，然後第一驅動電路16 依據顯示驅動資料36進一步地判斷資料傳輸線24中 DL3、DL4、DL5、DL6、DL7、DL8 需以電壓 vi 驅動， 並經由運算放大電路37來驅動薄膜電晶體38、39、40、 41、42、43趨向電壓位準λπ，所以，對應運算放大器44、 45、46、47、48、49 的多工選擇器 MUX3、MUX4、MUX5、 MUX6、MUX7、MUX8則會受控制以分別選取所需的電壓 1254899 準位（例如VI )，而運算放大器44、45、46、47、48、49 則使用多工選擇器 MUX3、MUX4、MUX5、MUX6、MUX7、 MUX8所選取的電壓準位（例如vi )來作為其輸入電壓， 並進一步驅動薄膜電晶體38、39、40、4卜42、43。然而， 各運算放大器44、45、46、47、48、49本身分別具有不同 的輸出電壓偏移量（0ffset )，所以會影響其實際的輸出電 壓，亦即當運算放大器44、45、46、47、48、49均使用同 一輸入電壓V1下，最後會造成電容50、51、52、53、54、 φ 55兩端保持的電壓差不同。此外，由顯示驅動資料36可 知，對應資料傳輪線DL3、DL4、DL5、DL6、DL7、DL8 • * 的像素理應顯示同一灰階，然而，由於運算放大器44、45、 46、47、48、49的輸出電壓分別受到其輸出電壓偏移量影 響而不同’亦即各像素會於顯示螢幕上呈現不均勻的灰階 分佈而造成液晶顯示裝置1〇的顯示品質不佳。 【發明内容】 因此本發明之主要目的在於提供一種驅動一液晶面板 上同一行之像素對應於同一電壓位準而可顯示均勻灰階值 之方法及其相關裝置，以解決上述問題。 本發明之申凊專利範圍提供一種驅動液晶（1丨叩记cr^stal 12 1254899 di_y，LCD)顯示裝置之方法，該液晶顯示裝置包含有一液晶面 板（LCDpanel)用來顯示以矩陣（matrix)方式排列之複數個像 素(PiXel)，一電壓選擇電路用來依據一顯示驅動資料(di_ydata) 輸出複數個轉電壓準位，以及複數個輸出緩衝器（〇攀t buffer) ’每-輸出_||係電連接於該電壓選擇電路以及該液晶 面板。該方法包含有依據該輕選擇電路所輸出之複數個驅動電 壓準位而使_複數個輸出緩衝器來驅動位於同—行之複數個像 素，中斷（disconnect)該複數個像素與該相對應複數個輸出緩衝 益之間之電連接’以及電連接關—鶴電醉健動之複數個 像素而使輸入該複數個像素之電壓相等。 本發明之申請專利範圍另提供一種液晶〇iquid crystal出卬丨办， LCD)顯示裝置，其包含有一液晶面板（LCDpand)用來顯示以 矩陣（matrix)方式排列之複數個像素（ρ&ι)，一電壓選擇電路 用來依據一顯示驅動資料（出叩1矽data)輸出複數個驅動電壓準 位’複數個輸出緩衝器（outpUt buffer)，每一輸出緩衝器係電連接 至该電壓選擇電路與該液晶面板以依據一驅動電壓準位驅動一相 對應像素’以及一時序控制器（timing^^0^)，用來控制該複 數個像素之驅動。該時序控制器包含有一除頻器（fre(luency divider )用來依據一預定除數對輸入該除頻器之時脈訊號之頻率進 行除頻而產生一輸出訊號，一計數器（counter)，用來計數該輸出 1254899 訊號而產生一計數值，以及一比較器（comparator)，用來比較該 計數值與一比較值。當該計數值等於該比較值時，該複數個輪出 緩衝器會中斷（disconnect)與該複數個像素之間之電連接，且該 複數個像素中原先被同一驅動電壓準位所驅動之複數個第一像素 則互相電連接以平均（average)輸入該複數個第一像素之電壓。 本發明之t請專概II[另提供—種㈣液晶㈤砲叩如 display，LCD)顯示裝置之驅動裝置，該液晶顯示裝置包含有一液 晶面板acDpanel)，其包含有矩陣（驗ix)方式翻之複數個 像素（pixel)。該驅動裝置包含有一電壓選擇電路，複數個解碼器， 以及複數個轉單元。該輕獅魏包含有—電驗應装置， 其包含有複數條金屬導_來傳送複數個。每—解碼器係用 來依據-顯示轉賴displaydata)而選擇性崎出該複數條金 屬導線所傳送之複數個電壓中之―電壓。每—驅動單祕電連接 於一相對應解碼n，且每—鶴單元包含有—輸隨翻（畴说 祕er)以及―_ (福），該關之 雜出緩衝&之輸_歧該輸出緩衝紅輸人端，該開關之第 Γ端係連接於該驅動單元之輸出端。該開關之第-端係可連接至 =輸出緩衝ϋ之輸_以驅動軸單元之_壓細電源 、應裝置之魏條金屬導線中—金屬導線所傳送之電壓，以及該 汗㈣-端#、糊’峨极轉該驅動單 1254899 兀之輸出電顯近—平均電屢，該平均電覆係由平均（㈣哪） 所树過相對應解碼器而電連接於同一金屬導線之複數個輸出缓 衝器之輸出端之電壓而產生。 本么月之申％專利範圍另提供一種驅動液晶（】㈣啊^ _打之鶴裝置，_晶顯枝私含有一液 個俊卿d)，其包含有以矩陣（驗ix)方式排列之複數 '、Ρ_) ’該驅動裝置包含有複數個解碼器（如⑺㈣與複 數個驅動單7^。每—解碼器_來依據—顯示驅動資料（dispIay ㈣而選擇性地輸出複數個電壓中之—電壓。每—驅動單元係電 連接於-相對應解碼器。每一驅動單元包含有一輸出緩衝器 ^output buffer)’ -第一開關連接於該輸出緩衝器之輸出端與該驅 動单元之輸出端之間，該輸出緩衝器之輸出端於該第__啟動 伽電連接_轉單元讀_，以及―第二_連接於該驅 動早疋之輸_與另-鱗單元讀㈣之間，該鶴單元之輸 出端於該第二關啟動後則電連接於該另—驅動單元之輸出端。 亥第開關可啟動以驅動該驅動單元之輸出電壓趨近該相對廉解 端所輸出之，以及該第二_可選擇性地啟動以驅動娜 動早几之輪ilif壓趨近-平均電壓，該平號壓係由平均 (average )互械連接之複數個驅動單元之輸出端的電壓而產生。 1254899 本發明之申請專利範圍另提供一種驅動平面顯示裝置（細 ㈣!cHSplay)之驅動裝置，該平面顯示裝置包含有以矩陣㈤則 方式排列之複數個像素（pixel)，該驅動裝置包含有一第一驅動單 二用來接收—第—糕，並依據該第—電壓驅動-相對應像素， -弟二驅動單元时接收一第二電壓，並依據該第二電屋驅動一 相對應像素’―帛三卩連接於該帛-組之輪出端盘該 第二輸出緩衝11之輸出端，以及—_電路絲依據該第-電壓 以及該第二電壓控_第三_是否啟動。該第—鶴單元包含 有一第一輸出緩衝器以及—第—_連接於該第—輸出緩衝器之 輸出端與該第一驅動單元之輸出端。該第二驅動單元包含有二第 二輸出緩衝器以及一第二開關連接於該第二輸出緩衝器之輸出端 與該第二驅動單元之輸出端之間。 本毛明之巾料利範圍另提供—種购平面顯示裝置（細 PaneldiSPlay)之驅練置，解面齡裝置包含有錢陣（崎ix) 方式排列之複數悔素（pixel)，該_置包含有—第—驅動單 兀用來接收—第—顯示驅動資料，並依據該第-顯示驅動資料驅 動-相對應像素，一第二驅動單元用來接收—第二顯示驅動資 料，並依據該第二顯示驅動資料驅動一相對應像素，一第三開關 連接於該第-輸出緩衝器之輸出端與該第二輸出緩衝器之輸出 端，以及—_電路用來依據該第—顯示驅動資料以及該第 16 1254899 示驅動資料控制該第三開關是否啟動。 ^輸出緩衝⑽11咖_^⑻包含有〜 端與该第-驅動單元之輪 後緩衝器之輪出 二輸出緩衝器以及—第二開關連接於=動單吻^ 與该第一,驅動單元之輸出端之問 ]出緩衝為之輪出蠕 【實施方式】 请參閱圖一，圖二，m 一 十 圖二’圖三為本發明第一插、富 算放大電路60的示咅圄。士々 月第一種運 圖。切明運算放 取代圖二所示之笫一舨I吩叫你用來 37 ^立φ 動勉16中的習知運算放大電路 明選擇電路56的詳細操作已經於上述先前 技術段落說明中詳細論述，因 U此在不衫響本發明技術揭露 的情況下’上述電壓選擇電路56的冗長操作制於下不再 重複敘述。運算放大電路60包含有複數個運算放大器幻 或是複數個運算轉導放大器（Gperati刪！ t删議如伽⑽ amplifier, OTA)以形成輸出緩衝器（〇鄉utbuffer)，而該 輸出緩衝器具有的增益值為1。此外，運算放大電路6〇另 包含有複數個開關（switch ) 64以控制電流路徑。當第二 驅動電路18依據水平同步訊號32而輸入一訊號脈衝（對 應南電壓準位）至閘極控制線26時，所有位於該閘極控制 線26上的薄膜電晶體28均會導通，然後，第一驅動電路 1254899 16便可依據顯示驅動資料36而分別地輸出相對應電壓至 資料傳輸線24中的DL1至DLn以於液晶面板12上輸出相 對應灰階值。同時，對應運算放大器的多工選擇器亦會選 擇一所需電壓（例如VI)，以及開關64亦會進行切換以選 擇導通兩端點E1與E2,所以電壓VI便可經由運算放大器 62來驅動電容30。然而，各運算放大器62之間會因為其 半導體製程不匹配（mismatch)而具有一特定輸出電壓偏 移量，即是說，於相同輸入電壓（例如VI )的情況下，各 φ 運算放大器62的輸出電壓會因為不同輸出電壓偏移量而 有所差異，所以，資料傳輸線24中的DL.1〜DLn會因為上 述運算放大器62之輸出電壓偏移量的影響而對應不同的 電壓準位，而資料傳輸線24中的DL1〜DLn所對應的電容 30便會儲存不同的電壓準位。本實施例中，開關64緊接 著會進一步地切換而導通端點E1與E3以改變電流路徑， 由於開關64的切換狀態改變，所以經由金屬導線66所傳春 遞的電壓VI便無法繼續透過運算放大器62來驅動電容 30，然而，每一電容30會由於端點E1與E3的導通而電連 接於同一金屬導線66。因此，所有的電容30則經由金屬 導線66而快速地進行平均電荷的運作，亦即所有的電容 30會因此而對應於一平均輸出電壓偏移量（averaged offset)，並且最後具有相同的電壓準位。 18 1254899 舉例來說，開關64首先切換至連接端點E1AE2的位 置，假若電壓V1係為5伏特，資料傳輸線24中du、dl2、 DL3、DL4的電壓則會透過運算放大器62所形成的輸出緩 衝器驅動而趨近5伏特，然而，每—算放大器⑺本身具有 不同的輸出電壓偏移量，因此資料傳輸線24中相對應 DU、DL2、DL3、DL4的電壓亦會不相同，例如，資料傳 輸線24中DL1、DL2、DL3、DL4的電壓最後分別會成為 4.8伏特、5.1伏特、4.7伏特、4.9伏特。於本實施例中， 開關64此時隨即切換至連接端點E4與E3的位置，既然資 料傳輸線24中DL1、DL2、DL3、DL4均透過端點E1與 E3而電連接至同一金屬導線66，所以對應資料傳輸線24 中DL1、DL2、DL3、DL4的不同電壓準位必然會快速地趨 近同一平均電壓，換句話說，資料傳輪線24中每一 DL1、 DL2、DL3、DL4原先分別對應4.8伏特、51伏特、4·7伏 特、4.9伏特，但是經由同一金屬導線66而使不同電壓準 位均會趨近一平均電壓。請注意，對於上述每一資料傳輸 線24而言’原先的不同輸出電壓偏移量則經由金屬導線 66的輔助而會分別對應同一平均輸出電壓偏移量，因此當 每一資料傳輸線24輸入同一輸入電壓時，對於每一資料傳 輸線24而言’由於該輸入電壓均受同一平均輸出電壓偏移 19 1254899 量影響，因此每一資料傳輸線24最後均會驅動至同一輸出 電壓，此外，若同一行上的像素經由分壓電路17所產生的 同一電壓所驅動，則該同一行上的像素均會對應相同的灰 階值。 請參閱圖四，圖四為本發明第二種運算放大電路7〇的 示意圖。運算放大電路70包含有複數個運算放大器72、 73、 74、75以作為輸出緩衝器，請注意，為了便於說明， 僅有四個運鼻放大為顯不於圖四上，且運算放大哭72、73、 74、 75與開關SI、S2係用來經由資料傳輸線DL1、DL2、 DL3、DL4而驅動相對應像素。運算放大電路7〇的運作敘 述如下，首先，啟動每一開關Si以使運算放大器72、73、 74、75》別電連接於相對應資料傳輸線、 DL4，如前所述，每一運算放大器、73、％、75各自具 有特定輸出電壓偏#量而影響實際輸出電壓偏移輸入電 壓’換句話說，對應運算放大器72、73的像素雖使用同一 ^入電壓（例如V1 )來驅動，然、而，由於運算放大器^、 本身輪出電壓偏移量的影響而使資料傳輸線DL1、DL2 的電壓彼此不同。然、後，對應運算放大器72、73、74、75 麫由有開關Sl均同時被關閉，而假如運算放大器72、73 碑傳輪線DL1、DL2而預定驅動相對應像素趨近同 20 1254899 一灰階值，則對應運算放大器72、73的開關S2會啟動， 所以資料傳輸線DL1、DL2的電壓準位便會快速地由兩個 不同電壓趨近同—平均電壓’即是原先的輸出電壓偏移量 經由平均後而產生資料傳輸線DL1、DL2上的平均電壓。 同樣地，假如運算放大器73、74經由資料傳輸線DL2、 DL3而預疋驅動相對應像素趨近同一灰階值，則對應運算 放大器73、74的開關S2亦會啟動’所以經由開關幻的幫 助，任何受同一輸入電壓所驅動的相鄰像素最後均會擁有 相同的灰階值。總而言之，當關於運算放大器、73、74、 75的開關S1啟動後’資料傳輸線Du、DL2、dl3、DL4 的電壓會先透過相對應運算放大器72、73、74、75來驅動， 然後每S1均會被關’接著，若相鄰像素預定具有 同一灰階值，則對應該相鄰像素的開關S2則會隨即啟動， 最後透過卩箱S2來平均對應相鄰像素之運算放大器的輸 出電壓偏移量，並進—步地消除相鄰:#料傳輸線之間的電 壓誤差（voltage deviation )。於本實施例中，運算放大電路 70係應用於以-行極性反相丨黯siQn)驅動方法所 驅動的液晶面板’而依據該行極性反相騎方法，同一行 上的像素均擁有相同的極性（pQlarity )，所以開關％便可 平均相鄰資料傳輸線（例如Du、DL2)上具有同一極性 的電壓準位。此外，本實施例中，不同的輪出電Μ偏移量 !254899 由圖三所示之電壓選擇電路56來進行平均電壓的處 理’而是經由相關的開關S2來進行平均電壓的處理，所 ^ ’任何可提供運算放大電路70所需不同電壓準位的分壓 電路岣可應用於本實施例之相對應第一驅動電路16中。 請參閱圖五，圖五為本發明第三種運算放大電路80的 不意圖。運算放大電路80的運作類似於圖四所示之運算放 大電路70 ’而僅是開關si、S2的排列方式不同。如圖五 所不’有一開關S2電連接兩運算放大器72、74，以及另 —開關S2電連接於兩運算放大器73、75，即是說，本實 例中’相鄰資料傳輸線（例如DL1、DL2 )並非經由開 關S2來連接，當像素經由一單點極性反相（d〇t inversion ) 口動方法’一雙點極性反相（two dot line inversion)驅動 方去’或一列極性反相（c〇lumn inversi〇n)驅動方法來驅 夺貝]同行上的相鄰像素係分別由不同極性的電壓來 °動即疋說，連接於資料傳輸線DL1、DL2 ' DL3、DL4 的像素對應下列極性關係，，+，，，，_“，，+，，，，_“或，，_“，，+，，，，_“，，+，，。所 以’當驅動對應相同極性的像素趨近同—灰階值時，運算 ，大電物係使用開關S2來連接對應同—極性之相鄰運 异玫大㈣用來平均前述的輸出電壓偏移量，舉例來說， 饭如連接於貧料傳輸線Du、DL3的像素預定具有同一灰 1254899 階值，則對應運算放大器72、74的開關S1 —開始時便會 先啟動以使同一輸入電壓驅動資料傳輸線DL1、DL3之電 壓準位，因為運算放大器72、74本身具有的輸出電壓偏移 量不同，所以造成資料傳輸線DL1、DL3上的電壓準位亦 會不一致。然後，對應資料傳輸線DL1、DL3的開關S1 關閉且對應資料傳輸線DL1、DL3的開關S2會同時啟動， 所以運算放大器72、74之輸出電壓偏移量於平均處理後會 消除資料傳輸線DL1、DL3之間的電壓誤差。請注意，運 算放大器72、74之不同輸出電壓偏移量係經由平均處理而 最後產生一平均電壓於兩資料傳輸線DL1、DL3上，換句 话說’於本實施例中’資料傳輸線DL1、DL3仍分別具有 一平均輸出電壓偏移量，但是資料傳輸線DL1、DL3上的 電壓準位是相同的。此外，若兩相鄰像素（對應同一極性） 並非預定被驅動至同一灰階值，則連接於兩相鄰像素之間 的開關S2會保持關閉狀態而不影響該相鄰像素的灰階 值。本實施例中，開關S2係連接於以同一極性驅動之兩資 料傳輸線，且該兩資料傳輸線之間則間隔有另一以相反極 性驅動的資料傳輸線，即是說，運算放大電路80係可應用 於以單點極性反相驅動方法，一雙點極性反相驅動方法， 或一列極性反相驅動方法所驅動的液晶面板上。此外，本 實施例中，不同的輸出電壓偏移量並非由圖三所示之電壓 1254899 選擇電路56來進行平均電壓的處理，而是經由相關的開關 S2來進行平均電壓的處理，所以，任何可提供運算放大電 路80所需不同電壓準位的分壓電路均可應用於本實施例 之相對應第一驅動電路16中。 明參閱圖六，圖六為圖五所示之運算放大電路與像 素82之間的連接示意圖。已知一特定顏色係由三原色光所 混合產生，例如由不同強度的紅光，藍光，以及綠光混合 產生不同的色彩，所以，設置於同—列的像素82則必須個 別地提供對應紅光，藍光，以及綠光的灰階值以顯示不同 的色彩，如圖六所示，複數個像素82用來表示一顏色次 序，，RGBRGBRGBRGB，，。當像素82經由—單點極性反相驅 動方法，一雙點極性反相驅動方法，或一列極性反相驅動 方法來驅動時，兩相近像素82擁有不同極性，例如同一行 之像素82依據一極性次序“而被驅動，對於 紅光來說，像素82a、82c擁有相同極性，，+”，以及像素82b、 82d擁有相同極性，，_，，，而對於用來顯示紅光之像素 82b、82c、82d而言，一開關S2連接於連接於以同一極性，，+，， 驅動的像素82a、82c之間，此外，另—開關⑴系連接於 以同一極性，，·，，驅動的像素82b、82d之間。所以，當運算 放大電路8G驅㈣應1定單色光的複數個像素時，對於 24 1254899 以同一極性驅動且預定對應同一灰階值之相鄰像素，開關 S2則負責平均驅動該相鄰像素之驅動電壓。請注意，上述 驅動像素之方法亦可同樣地應用於驅動對應綠光及藍光的 像素，而相關驅動對應綠光及藍光之像素的操作與驅動對 應紅光之像素的操作相同，因此不再重複贅述。 圖三所示之電壓選擇電路56係用來提供運算放大電路 •60所需之適當電壓準位，此外，電壓選擇電路56中的金 屬導線66不僅用來傳送電力，並且可平均不同資料傳輸線 24的電壓準位，即是說，當同一行上不同位置的像素經由 電壓選擇電路56所提供的同一電壓驅動時，該不同位置的 像素會擁有相同的灰階值，而金屬導線66則是用來平均大 範圍之驅動電壓。相反地，分別於圖四與圖五所示之運算 放大電路70、80則使用開關S2來平均小範圍之驅動電壓， 換句話說，僅有當兩相鄰像素預定透過一相同電壓驅動 時，對應該兩相鄰像素之開關S2才會啟動。一般而言，使 用者只會察覺兩相鄰像素之間的灰階值差異，而不會在意 每一像素之實際灰階值，所以當兩相鄰像素係經由同一輸 入電壓驅動時，運算放大電路70、80的主要目的則在於消 除兩相鄰像素之間的灰階值差異，亦即運算放大電路70、 80所使用之開關S2係取代運算放大電路60中電壓選擇電 1254899 路56所使用之金屬導線66，並用來消除兩相鄰像素之間 的灰階值差異而達到均勻化灰階值及改善顯示品質之目 的0 如上所述，運算放大電路70係應用於以行極性反相驅 動方法所驅動之液晶顯示裝置，而運算放大電路80則應用 於以列極性反相驅動方法，單點極性反相驅動方法，或雙 點極性反相驅動方法所驅動之液晶顯示裝置。換句話說， 本發明運算放大電路可應用於使用一預定像素驅動方法之 液晶顯示裝置以解決習知運算放大器之輸出電壓偏移量所 帶來的問題。此外，本發明揭露之液晶顯示裝置中另包含 有一互斥或（exclusive OR，X〇R)邏輯電路或者一比較器 (comparator)以用來決定開關82是否需啟動或是關閉， 亦即該互斥或邏輯電路係用來比較關於兩像素之數位輸入 顯示驅動資料以判斷兩像素是否需驅動至同一灰階值，而 該比較器係用紐㈣於兩像素之類比輸人顯示驅動資料 判斷兩像素疋否需驅動至同—灰階值。當該互斥或邏輯 電^或是該比較器確認兩像素預定驅動至同-灰階值時， =Γ開關S2便會啟動以進-步消除不同輪出電 揭零之^日 像龄Μ㈣#，換句減，本發明 ，示裳置包含有1測電路，例如對應數位輪 26 1254899 入顯示驅動資料之互斥或邏輯電路或對應類比輸入顯示驅 動資料之比較器，用來比較關於兩像素之輸入顯示驅動資 料，當兩像素預定擁有相同灰階值時，開關S2會依據該互 斥或邏輯電路或該比較器所產生的比較結果而被啟動。另 外，本發明之運算放大電路中亦可使用運算轉導放大器 (operational transconductance amplifier, OTA)來取代運算 放大器以驅動像素。 圖三所示之開關64以及圖四至圖六所示之開關si、S2 之操作係由一時序控制器（timing controller)所控制，亦 即該時序控制器與圖一所示之控制電路14互相配合以正 確地驅動圖一所示之液晶面板12。請參閱圖七，圖七為本 發明時序控制器90的功能方塊圖。時序控制器9〇包含有 一除頻器（frequency divider ) 92，一 計數器（counter ) 94， 比較器96，以及一邏輯控制器（1〇扯c〇ntr〇uer) 98。時_ 序控制器90的運作敘述如下，除頻器％使用一除數 (divisor) N1來針對輸入之時脈訊號CLK1的頻率進行除 頻的操作，而除數N1的數值係、由—控制訊號pd所決定， 例如控制訊號Pd可以是包含兩位元之二進位資 料 ”00”、”01”、”10”、，，n ” 之一以用來分別設定除數N1 為 ”1”、”2”、”3”、”4”，其奸 右4脈訊號CLK1的頻率為fl，則 27 1254899 一輸出訊號102具有一頻率f2,且該頻率f2會等於fl/N1， 即是說，當頻率fl等於千赫兹（KHz)，且輸入除頻 92之控制訊號Pd對應一二進位資料”11”時，則輸出訊號 102的頻率則成為27千赫茲（亦即108/4)，換句話說，輸 出訊號102之頻率可依據對應不同頻率之時脈訊號CLK1 以及不同除數N1之設定值來進一步調整以符合需求。然 後，輸出訊號102再傳輸至計數器94，而計數器94係依 據一預定計數值N2來計數（count)輸出訊號102的週期 數，舉例來說，當一訊號不斷觸發計數器94而達到一預定 次數時，計數器94會.依據該預定計數值而輪出不同訊號 CO、Cl、C2、C3至比較器96，即是不同的計數值N2會 造成訊號CO、Cl、C2、C3分別對應不同輸出資料，舉例 來說，當計數器94被輸出訊號1〇2觸發216次時，訊號 CO、Cl、C2、C3 分別對應數值”1”、”〇’’、”1”、”0，，而輸入 比較器96，如上述舉例說明可知輸出訊號102之頻率β 為27千赫茲，因此每秒之中，輸出訊號102會觸發計數器 94總共27000次，所以經過8毫秒（millisecond, ms)後， 計數器94會輸出分別對應數值’Τ’、、”1”、的訊號 CO、Cl、C2、C3以表示計數值Ν2以計數達到216，此時 比較器96便會比較該訊號CO、C卜C2、C3所對應之輪出 資料與一比較值Ν3，該比較值Ν3係由控制訊號所、、夫 28 1254899 疋例如，當控制訊號According to the wire, the phase of the crystal molecules is adjusted to reflect the light transmission characteristics of the V. For example, the second ^ direction and the corresponding initial circuit 18 wheel a signal pulse (corresponding to the voltage level) to the gate control line 导 to turn on the signal corresponding to the thin film electric drive circuit 16 to pass through 2 The phase-in-phase transistor 28_the material-efficiency capacitor 3() is transmitted according to the different signal source 24 of the input signal transmission line 24 of the _15 dynamic circuit 16 for the transmission of the (four)n of the county device 22, and the driver circuit 16 includes - The sub-fourth road (pain gedivider) 1254899 17 outputs a plurality of voltages n according to the electric I vG, ~Vm, for example, 'the first power supply device 22 can generate 10 different voltages V0, ~V9, and the partial pressure The circuit 17 can perform a voltage division operation on the voltages ν〇, 〜V9, and finally generate 256 different voltages ν 〇 V V255. Then, the first driving circuit 16 is at all available voltages V according to the display driving data 36. ～V255 selects an appropriate voltage to drive the thin film transistor 28, and generally, different voltages correspond to different grayscale values'. Therefore, the image of the grayscale value of each pixel is controlled, corresponding to the image of the poorly driven 36. Finally, it can be displayed on the liquid crystal panel 12. • Referring to FIG. 1 and FIG. 2, FIG. 2 is a schematic diagram of the first driving circuit 16 shown in FIG. The first driving circuit 16 further includes a voltage selecting circuit 56 and an operational amplifying circuit 37 for respectively driving the corresponding thin film transistors 28 according to different voltages v 〇 〜 vn provided by the voltage dividing circuit 17. The operational amplifier circuit 37 includes a plurality of operational amplifiers (ampimers) 44, 45, 46, 47, 48, 49, and each of the operational amplifiers 44, 45, 46, 47 48 49 is used as an output buffer (howling) For example, buffer, its gain value is 1. In addition, each of the operational amplifiers 44, 45, 46, 47, 48, 49 in the operational amplifier circuit 37 is electrically connected to a corresponding multiplexer (MUX), and the multiplexer (see FIG. The MUX3 to MUX8) shown are provided in the voltage selection circuit 56. Note that for convenience of explanation, only six operational amplifiers and a relative 1254899 multiplexer are shown in FIG. According to the control signals D3 to D8' outputted by the control circuit 14, the corresponding multiplexer selects a specific voltage level from the different voltages V?~Vn generated by the voltage dividing circuit 17, each multiplexer ( For example, the operation of MUX3~MUX8) can be regarded as an analog/digital converter (DAC) or a decoder (dec〇der) for performing signal conversion or decoding operation on the display driving data 36, that is, multiplexing. After the selector completes the processing of the display driver data 36, the multiplexer starts to select a specific voltage level from different voltages ~% according to the display driving data 36 and outputs the specific voltage level to a corresponding pixel. To drive the pixel. Please note that each voltage V〇~Vn is separately transmitted via a power transmission line (for example, the metal wire 66 shown in FIG. 2). When the control circuit 14 receives the horizontal synchronization signal 32 and the vertical synchronization signal %, the control circuit 14 A corresponding signal is generated and input to the first and second drive circuits 16, 18. For example, when the second driving circuit w generates a pulse to cause all of the thin film transistors 28 on the same row to be turned on, then the first driving circuit 16 further determines DL3, DL4, and DL5 in the data transmission line 24 according to the display driving data 36. DL6, DL7, and DL8 are driven by the voltage vi, and the thin film transistors 38, 39, 40, 41, 42, 43 are driven to the voltage level λπ via the operational amplifier circuit 37, so that the operational amplifiers 44, 45, 46 are corresponding. The multiplexers MUX3, MUX4, MUX5, MUX6, MUX7, and MUX8 of 47, 48, and 49 are controlled to select the required voltage 1254899 level (for example, VI), and the operational amplifiers 44, 45, 46, 47, 48, 49 use the voltage levels (such as vi) selected by the multiplexers MUX3, MUX4, MUX5, MUX6, MUX7, MUX8 as their input voltages, and further drive the thin film transistors 38, 39, 40, 4 Bu 42, 43. However, each of the operational amplifiers 44, 45, 46, 47, 48, 49 has a different output voltage offset (0ffset), so it affects its actual output voltage, that is, when the operational amplifiers 44, 45, 46, 47, 48, and 49 all use the same input voltage V1, and finally the voltage difference between the capacitors 50, 51, 52, 53, 54, and φ 55 is different. In addition, it can be seen from the display driving data 36 that the pixels corresponding to the data transfer lines DL3, DL4, DL5, DL6, DL7, DL8** should display the same gray level, however, due to the operational amplifiers 44, 45, 46, 47, 48, The output voltage of 49 is differently affected by the output voltage offset thereof, that is, each pixel may exhibit an uneven gray scale distribution on the display screen, resulting in poor display quality of the liquid crystal display device 1 . SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a method and related apparatus for driving a pixel of the same row on a liquid crystal panel to display a uniform gray level value corresponding to the same voltage level to solve the above problems. The patent application scope of the present invention provides a method for driving a liquid crystal display device comprising a liquid crystal panel (LCD panel) for displaying in a matrix manner. Arranging a plurality of pixels (PiXel), a voltage selection circuit for outputting a plurality of voltage levels according to a display driving data (di_ydata), and a plurality of output buffers (〇), each output _|| Electrically connected to the voltage selection circuit and the liquid crystal panel. The method includes causing a plurality of output buffers to drive a plurality of pixels located in the same row according to a plurality of driving voltage levels output by the light selection circuit, and disconnecting the plurality of pixels and the corresponding complex number The electrical connection between the output buffers and the electrical connection - the multiple pixels of the crane and the dizzy move make the voltages input to the plurality of pixels equal. The patent application scope of the present invention further provides a liquid crystal display (LCD) display device comprising a liquid crystal panel (LCDpand) for displaying a plurality of pixels arranged in a matrix manner (ρ & ι) a voltage selection circuit is configured to output a plurality of driving voltage levels (outpUt buffer) according to a display driving data (output data), each output buffer is electrically connected to the voltage selection circuit And the liquid crystal panel drives a corresponding pixel according to a driving voltage level and a timing controller (timing) for controlling driving of the plurality of pixels. The timing controller includes a frequency divider (fre (luency divider) for dividing the frequency of the clock signal input to the frequency divider according to a predetermined divisor to generate an output signal, a counter, Counting the output 1254899 signal to generate a count value, and a comparator for comparing the count value with a comparison value. When the count value is equal to the comparison value, the plurality of round-out buffers are interrupted. Disconnecting an electrical connection with the plurality of pixels, and the plurality of first pixels of the plurality of pixels that are originally driven by the same driving voltage level are electrically connected to each other to average input the plurality of first pixels The voltage of the pixel. The invention of the present invention II [further provided - (four) liquid crystal (five) such as display, LCD) display device driving device, the liquid crystal display device comprises a liquid crystal panel acDpanel), which comprises a matrix (test Ix) The method turns over a number of pixels (pixels). The driving device comprises a voltage selecting circuit, a plurality of decoders, and a plurality of rotating units. The light lion Wei contains an electrical test device that includes a plurality of metal guides to transmit a plurality of wires. Each decoder is used to selectively extract the "voltage" of the plurality of voltages transmitted by the plurality of metal wires in accordance with - display dependent display data. Each-drive single-sense electrical connection is connected to a corresponding decoding n, and each--the crane unit contains----------------------------------------------------------------- The output buffer is red input terminal, and the third end of the switch is connected to the output end of the driving unit. The first end of the switch can be connected to the output of the output buffer _ to the voltage of the drive shaft unit, the voltage of the metal wire of the device, the voltage transmitted by the metal wire, and the sweat (four)-end# The paste '峨 转 该 该 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 Generated by the voltage at the output of the buffer. This month's application of the % patent scope also provides a driving liquid crystal (] (four) ah ^ _ hit the crane device, _ crystal display branch contains a liquid Junjun d), which contains a matrix (test ix) way The complex ', Ρ _) 'The drive device comprises a plurality of decoders (such as (7) (four) and a plurality of drive orders 7 ^. Each - decoder _ according to - display drive data (dispIay (four) and selectively output a plurality of voltages - voltage. Each drive unit is electrically connected to the corresponding decoder. Each drive unit includes an output buffer ^' - the first switch is connected to the output of the output buffer and the output of the drive unit Between the terminals, the output of the output buffer is between the first __starting galvanic connection_transfer unit read_, and the second _ is connected to the drive early _ and the other squaring unit read (four), The output end of the crane unit is electrically connected to the output end of the other drive unit after the second switch is started. The output switch of the drive unit can be driven to drive the output voltage of the drive unit to be outputted by the relatively inexpensive end. And the second_ can be selectively activated to In the early days, the ilif pressure approaches the average voltage, which is generated by the voltage at the output of a plurality of drive units that are averaged and mechanically connected. 1254899 The patent application scope of the present invention further provides a a driving device for driving a flat display device (fine (4)! cHSplay), the flat display device comprising a plurality of pixels arranged in a matrix (five) manner, the driving device comprising a first driving unit 2 for receiving - the first a cake, and according to the first voltage driving-corresponding pixel, the second driving unit receives a second voltage, and according to the second electric house driving a corresponding pixel '--three-way connection to the 帛-group Turning off the output end of the second output buffer 11 of the end disk, and whether the circuit wire is activated according to the first voltage and the second voltage control_third_. The first crane unit includes a first output buffer and - the first - is connected to the output of the first output buffer and the output of the first driving unit. The second driving unit comprises two second output buffers and a second switch is connected to the second The output end of the buffer is between the output end of the second driving unit and the output end of the second driving unit. The scope of the invention is also provided by the purchase of a flat display device (fine PaneldiSPlay), and the face-faced device includes a money array. (Saki ix) a plurality of pixels arranged in a manner, the _set includes a -first driving unit for receiving - the first display driving data, and driving the corresponding pixel according to the first display driving data, The second driving unit is configured to receive the second display driving data, and drive a corresponding pixel according to the second display driving data, wherein a third switch is connected to the output end of the first output buffer and the second output buffer The output terminal, and the -_ circuit is configured to control whether the third switch is activated according to the first display driving data and the driving data of the 16th 1254899. ^Output buffer (10)11 _^(8) includes a round output buffer of the end of the wheel of the first drive unit and a second output switch of the second switch connected to the first and the drive unit The output end of the problem] out of the buffer for the round out of the creep [embodiment] Please refer to Figure 1, Figure 2, m 10 Figure 2 'Figure 3 is the first plug, rich arithmetic amplifier circuit 60 of the present invention. The first type of map of the gentry. The detailed operation of the clear operation circuit instead of the one shown in FIG. 2, which is used by the conventional operational amplifier circuit in the φ 勉 勉 16 , has been described in detail in the above prior art paragraph description. In the case where U is not disclosed in the present invention, the redundant operation of the voltage selection circuit 56 described above will not be repeated. The operational amplifier circuit 60 includes a plurality of operational amplifiers or a plurality of operational transconductance amplifiers (Gperati, such as gamma (10) amplifier, OTA) to form an output buffer (〇 utbuffer), and the output buffer has The gain value is 1. In addition, the operational amplifier circuit 6 〇 further includes a plurality of switches 64 to control the current path. When the second driving circuit 18 inputs a signal pulse (corresponding to the south voltage level) to the gate control line 26 according to the horizontal synchronization signal 32, all the thin film transistors 28 on the gate control line 26 are turned on, and then The first driving circuit 1254899 16 can respectively output the corresponding voltage to the DL1 to DLn in the data transmission line 24 according to the display driving data 36 to output the corresponding grayscale value on the liquid crystal panel 12. At the same time, the multiplexer corresponding to the operational amplifier also selects a desired voltage (for example, VI), and the switch 64 also switches to select the two ends E1 and E2, so that the voltage VI can be driven via the operational amplifier 62. Capacitor 30. However, each operational amplifier 62 has a specific output voltage offset due to its semiconductor process mismatch, that is, in the case of the same input voltage (eg, VI), each φ operational amplifier 62 The output voltage may vary due to different output voltage offsets. Therefore, DL.1 to DLn in the data transmission line 24 may correspond to different voltage levels due to the influence of the output voltage offset of the operational amplifier 62. The capacitors 30 corresponding to DL1 DL DLn in the data transmission line 24 store different voltage levels. In this embodiment, the switch 64 is further switched to turn on the terminals E1 and E3 to change the current path. Since the switching state of the switch 64 changes, the voltage VI transmitted through the metal wire 66 cannot continue to pass through the operation. Amplifier 62 drives capacitor 30, however, each capacitor 30 is electrically coupled to the same metal conductor 66 due to the conduction of terminals E1 and E3. Therefore, all of the capacitors 30 quickly perform an average charge operation via the metal wires 66, that is, all of the capacitors 30 thus correspond to an averaged output offset and finally have the same voltage level. Bit. 18 1254899 For example, the switch 64 first switches to the position of the connection terminal E1AE2. If the voltage V1 is 5 volts, the voltages of the du, dl2, DL3, and DL4 in the data transmission line 24 are transmitted through the output buffer formed by the operational amplifier 62. The driver drives to approach 5 volts. However, each amplifier (7) itself has a different output voltage offset, so the voltages of the corresponding DU, DL2, DL3, and DL4 in the data transmission line 24 will also be different, for example, data transmission lines. The voltages of DL1, DL2, DL3, and DL4 in 24 will eventually become 4.8 volts, 5.1 volts, 4.7 volts, and 4.9 volts, respectively. In this embodiment, the switch 64 is then switched to the position of the connection terminals E4 and E3. Since the DL1, DL2, DL3, and DL4 in the data transmission line 24 are electrically connected to the same metal wire 66 through the terminals E1 and E3, Therefore, the different voltage levels of DL1, DL2, DL3, and DL4 in the corresponding data transmission line 24 will inevitably approach the same average voltage rapidly. In other words, each of the DL1, DL2, DL3, and DL4 in the data transmission line 24 originally corresponds to each other. 4.8 volts, 51 volts, 4.7 volts, 4.9 volts, but different voltage levels will approach an average voltage via the same metal wire 66. Please note that for each of the data transmission lines 24, the original different output voltage offsets respectively correspond to the same average output voltage offset via the assistance of the metal wires 66, so when each data transmission line 24 is input to the same input. For voltage, for each data transmission line 24, 'since the input voltage is affected by the same average output voltage offset 19 1254899, each data transmission line 24 will eventually drive to the same output voltage, and if on the same line The pixels on the same row are driven by the same voltage generated by the voltage dividing circuit 17, and the pixels on the same row will correspond to the same grayscale value. Referring to FIG. 4, FIG. 4 is a schematic diagram of a second operational amplifier circuit 7〇 according to the present invention. The operational amplifier circuit 70 includes a plurality of operational amplifiers 72, 73, 74, and 75 as output buffers. Please note that for convenience of explanation, only four noses are enlarged to be less than FIG. 4, and the operational amplification is crying 72. The switches 73, 74, 75 and the switches SI, S2 are used to drive the corresponding pixels via the data transmission lines DL1, DL2, DL3, DL4. The operation of the operational amplifier circuit 7 is described as follows. First, each switch Si is activated to electrically connect the operational amplifiers 72, 73, 74, 75 to the corresponding data transmission line, DL4, as described above, each operational amplifier, 73, %, 75 each have a specific output voltage offset amount and affect the actual output voltage offset input voltage. In other words, the pixels corresponding to the operational amplifiers 72, 73 are driven by the same voltage (for example, V1), However, the voltages of the data transmission lines DL1, DL2 are different from each other due to the influence of the operational amplifier's own voltage offset. Then, the corresponding operational amplifiers 72, 73, 74, 75 麫 are simultaneously turned off by the switch S1, and if the operational amplifiers 72, 73 are transmitted by the polling lines DL1, DL2, the corresponding pixels are driven to be close to 20 1254899. The gray scale value, the switch S2 corresponding to the operational amplifiers 72, 73 will start, so the voltage levels of the data transmission lines DL1, DL2 will quickly approach the same two voltages - the average voltage 'is the original output voltage bias The shift amount is averaged to generate an average voltage on the data transmission lines DL1, DL2. Similarly, if the operational amplifiers 73, 74 pre-drive the corresponding pixels to the same grayscale value via the data transmission lines DL2, DL3, the switches S2 corresponding to the operational amplifiers 73, 74 will also be activated. Any adjacent pixel driven by the same input voltage will eventually have the same grayscale value. In summary, when the switch S1 for the operational amplifiers, 73, 74, 75 is activated, the voltages of the data transmission lines Du, DL2, dl3, and DL4 are first driven through the corresponding operational amplifiers 72, 73, 74, 75, and then every S1. Will be turned off' Next, if adjacent pixels are scheduled to have the same grayscale value, the switch S2 corresponding to the adjacent pixel will be started, and finally the output voltage offset of the operational amplifier corresponding to the adjacent pixel is averaged through the box S2. Quantity, and step by step to eliminate the adjacent: # voltage transmission line voltage deviation (voltage deviation). In the present embodiment, the operational amplifier circuit 70 is applied to the liquid crystal panel driven by the -row polarity inversion 丨黯siQn) driving method. According to the row polarity inversion riding method, the pixels on the same row have the same Polarity (pQlarity), so the switch % averages the voltage levels of the same polarity on adjacent data transmission lines (eg Du, DL2). In addition, in the present embodiment, the different wheel-out power offsets 254899 are processed by the voltage selection circuit 56 shown in FIG. 3 to perform the average voltage processing, and the average voltage is processed via the associated switch S2. ^ 'A voltage dividing circuit 可 that can provide different voltage levels required for the operational amplifier circuit 70 can be applied to the corresponding first driving circuit 16 of the present embodiment. Referring to FIG. 5, FIG. 5 is a schematic diagram of a third operational amplifier circuit 80 of the present invention. The operation of the operational amplifier circuit 80 is similar to the operational amplification circuit 70' shown in Fig. 4 except that the switches si, S2 are arranged differently. As shown in FIG. 5, there is a switch S2 electrically connecting the two operational amplifiers 72, 74, and the other switch S2 is electrically connected to the two operational amplifiers 73, 75, that is, in the present example, the adjacent data transmission lines (for example, DL1, DL2) Not connected via switch S2, when the pixel is in a single dot polarity inversion (d〇t inversion), the method of 'two dot line inversion' drive side' or a column of polarity inversion (c〇 The lumn inversi〇n) driving method to drive the adjacent pixel system on the peer is respectively driven by voltages of different polarities, that is, the pixels connected to the data transmission lines DL1, DL2 'DL3, DL4 correspond to the following polarity relationship, ,+,,,,__,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Therefore, when the pixels corresponding to the same polarity approach the same gray-scale value, the operation, the large-scale electrical system uses the switch S2 to connect the adjacent-polarity adjacent transmissions (4) to average the aforementioned output voltage offset. For example, if the pixels of the rice connected to the poor transmission lines Du and DL3 are predetermined to have the same gray level of 1254899, the switches S1 corresponding to the operational amplifiers 72 and 74 start at the beginning to drive the same input voltage. The voltage levels of the transmission lines DL1 and DL3 are different because the operational amplifiers 72 and 74 have different output voltage offsets, so that the voltage levels on the data transmission lines DL1 and DL3 are also inconsistent. Then, the switch S1 corresponding to the data transmission lines DL1, DL3 is turned off and the switches S2 corresponding to the data transmission lines DL1, DL3 are simultaneously activated, so the output voltage offset of the operational amplifiers 72, 74 will eliminate the data transmission lines DL1, DL3 after the average processing. Voltage error between. Please note that the different output voltage offsets of the operational amplifiers 72, 74 are finally averaged to generate an average voltage on the two data transmission lines DL1, DL3, in other words, in the present embodiment, the data transmission lines DL1, DL3 There is still an average output voltage offset, respectively, but the voltage levels on the data transmission lines DL1, DL3 are the same. In addition, if two adjacent pixels (corresponding to the same polarity) are not intended to be driven to the same gray scale value, the switch S2 connected between the two adjacent pixels will remain off without affecting the gray scale value of the adjacent pixel. In this embodiment, the switch S2 is connected to two data transmission lines driven by the same polarity, and the data transmission lines are separated by another data transmission line driven by the opposite polarity, that is, the operational amplification circuit 80 is applicable. In the single-point polarity inversion driving method, a two-point polarity inversion driving method, or a column of polarity inversion driving method driven on the liquid crystal panel. In addition, in the present embodiment, the different output voltage offsets are not processed by the voltage 1254899 selection circuit 56 shown in FIG. 3 for the average voltage, but the average voltage is processed via the associated switch S2, so any A voltage dividing circuit that can provide different voltage levels required for the operational amplifier circuit 80 can be applied to the corresponding first driving circuit 16 of the present embodiment. Referring to FIG. 6, FIG. 6 is a schematic diagram of the connection between the operational amplifier circuit and the pixel 82 shown in FIG. It is known that a specific color is generated by mixing three primary colors of light, for example, different colors of red, blue, and green light are mixed to produce different colors. Therefore, the pixels 82 disposed in the same column must separately provide corresponding red light. , blue light, and grayscale values of green light to display different colors, as shown in FIG. 6, a plurality of pixels 82 are used to represent a color order, RGBRGBRGBRGB,,. When the pixel 82 is driven by a single-point polarity inversion driving method, a two-point polarity inversion driving method, or a column polarity inversion driving method, the two adjacent pixels 82 have different polarities, for example, the pixel 82 of the same row is based on a polarity. The order is "driven", for red light, pixels 82a, 82c have the same polarity, +", and pixels 82b, 82d have the same polarity, _, ,, for pixels 82b, 82c used to display red light In the case of 82d, a switch S2 is connected between the pixels 82a and 82c which are driven by the same polarity, +, and, and the other switch (1) is connected to the pixel 82b which is driven by the same polarity. Between 82d. Therefore, when the operational amplifier circuit 8G drives (four) a plurality of pixels of monochromatic light, for the adjacent pixels that are driven by the same polarity and are predetermined to correspond to the same grayscale value, the switch S2 is responsible for driving the driving of the adjacent pixels on average. Voltage. Please note that the above method of driving pixels can be similarly applied to driving pixels corresponding to green light and blue light, and the operation of the pixels corresponding to the green light and the blue light is the same as the operation of driving the pixels corresponding to the red light, and therefore is not repeated. Narration. The voltage selection circuit 56 shown in FIG. 3 is used to provide the appropriate voltage level required for the operational amplifier circuit 60. Furthermore, the metal conductors 66 in the voltage selection circuit 56 are used not only to transfer power but also to average different data transmission lines 24 The voltage level, that is, when pixels of different positions on the same row are driven by the same voltage provided by the voltage selection circuit 56, the pixels of the different positions will have the same grayscale value, and the metal wires 66 are used. To average a wide range of drive voltages. Conversely, the operational amplifier circuits 70, 80 shown in FIG. 4 and FIG. 5 respectively use the switch S2 to average a small range of driving voltages. In other words, only when two adjacent pixels are intended to be driven through a same voltage. The switch S2 corresponding to two adjacent pixels will be activated. In general, the user only perceives the grayscale value difference between two adjacent pixels, and does not care about the actual grayscale value of each pixel, so when two adjacent pixels are driven by the same input voltage, the operation is amplified. The main purpose of the circuits 70, 80 is to eliminate the difference in gray scale values between two adjacent pixels, that is, the switch S2 used in the operational amplifier circuits 70, 80 is used instead of the voltage selection circuit 1254899 in the operational amplifier circuit 60. The metal wire 66 is used to eliminate the difference in gray scale value between two adjacent pixels to achieve uniform gray scale value and improve display quality. 0 As described above, the operational amplifier circuit 70 is applied to drive inversion with row polarity. The liquid crystal display device driven by the method, and the operational amplifier circuit 80 is applied to a liquid crystal display device driven by a column polarity inversion driving method, a single-point polarity inversion driving method, or a two-point polarity inversion driving method. In other words, the operational amplifier circuit of the present invention can be applied to a liquid crystal display device using a predetermined pixel driving method to solve the problem caused by the output voltage offset of the conventional operational amplifier. In addition, the liquid crystal display device disclosed in the present invention further includes an exclusive OR (X〇R) logic circuit or a comparator for determining whether the switch 82 needs to be turned on or off, that is, the mutual The repulsion or logic circuit is used to compare the digital input display driving data about two pixels to determine whether the two pixels need to be driven to the same gray level value, and the comparator uses the neon (four) two-pixel analog input driving data to judge two Does the pixel need to be driven to the same-grayscale value. When the mutual exclusion or logic circuit or the comparator confirms that the two pixels are predetermined to be driven to the same-gray scale value, the =Γ switch S2 is activated to further eliminate the different rounds of power-off and zero-off (4) #,换句减, the present invention, shows that the skirt contains a test circuit, for example, corresponding to the digital wheel 26 1254899 into the display drive data of the exclusive or logic circuit or the corresponding analog input display drive data comparator, used to compare about two The input of the pixel displays the driving data. When the two pixels are scheduled to have the same grayscale value, the switch S2 is activated according to the mutual exclusion or logic circuit or the comparison result generated by the comparator. Further, in the operational amplifier circuit of the present invention, an operational transconductance amplifier (OTA) may be used instead of the operational amplifier to drive the pixels. The operation of the switch 64 shown in FIG. 3 and the switches si and S2 shown in FIG. 4 to FIG. 6 is controlled by a timing controller, that is, the timing controller and the control circuit 14 shown in FIG. Cooperate to properly drive the liquid crystal panel 12 shown in FIG. Please refer to FIG. 7. FIG. 7 is a functional block diagram of the timing controller 90 of the present invention. The timing controller 9A includes a frequency divider 92, a counter 94, a comparator 96, and a logic controller (98). The operation of the timing controller 90 is described as follows. The frequency divider % uses a divisor N1 to perform frequency division operation on the frequency of the input clock signal CLK1, and the value of the divisor N1 is controlled by The signal pd is determined, for example, the control signal Pd may be one of two binary data "00", "01", "10", and n" for setting the divisor N1 to "1", "2", "3", "4", the frequency of the right 4 pulse signal CLK1 is fl, then 27 1254899 an output signal 102 has a frequency f2, and the frequency f2 will be equal to fl / N1, that is to say, When the frequency fl is equal to kilohertz (KHz), and the control signal Pd of the input frequency division 92 corresponds to a binary data "11", the frequency of the output signal 102 becomes 27 kHz (ie, 108/4), in other words. In other words, the frequency of the output signal 102 can be further adjusted according to the set value of the clock signal CLK1 and the different divisor N1 corresponding to different frequencies to meet the demand. Then, the output signal 102 is transmitted to the counter 94, and the counter 94 is based on a predetermined schedule. Counting the value N2 to count (count) the week of the output signal 102 For example, when a signal continuously triggers the counter 94 for a predetermined number of times, the counter 94 will rotate the different signals CO, Cl, C2, C3 to the comparator 96 according to the predetermined count value, that is, different. The count value N2 causes the signals CO, Cl, C2, and C3 to correspond to different output data. For example, when the counter 94 is triggered 216 times by the output signal 1〇2, the signals CO, Cl, C2, and C3 respectively correspond to the value “1”. "," 〇'', "1", "0", and input to the comparator 96, as exemplified above, the frequency β of the output signal 102 is 27 kHz, so that the output signal 102 triggers the counter 94 every second. A total of 27,000 times, so after 8 milliseconds (millisecond, ms), the counter 94 will output the signals CO, Cl, C2, C3 corresponding to the values 'Τ', "1", respectively, to indicate the count value Ν 2 to reach 216, At this time, the comparator 96 compares the rounded data corresponding to the signals CO, C, C2, and C3 with a comparison value Ν3, and the comparison value Ν3 is controlled by the control signal, and the husband 28 1254899 疋, for example, when the control signal
Pc以兩位元來表示一二進位資料 為1〇’而輸入比較器96時，比較值N3會被設定為以四位 兀表不之二進位資料”1010，，，當訊號CO、Cl、C2、C3所 對應之輸出資料與比較值N3相符時，比較器96便會產生 電楚位準轉變（voltage level transition)。舉例來說，於 "十數态94輪出分別對應數值，，1，，、，，0，，、，，1，，、，，0，，的訊號（：：〇、Pc uses two digits to indicate that the binary data is 1〇' and when the comparator 96 is input, the comparison value N3 is set to the four-digit data of the four digits "1010", when the signal CO, Cl, When the output data corresponding to C2 and C3 coincides with the comparison value N3, the comparator 96 generates a voltage level transition. For example, in the "ten number state, 94 corresponding values respectively, 1,,,,, 0,,,,, 1,,,,,,,,,,,,,,,,,,,,,,,,,,,
Cl、C2、η 此 則，比較器96原本輸出邏輯值”1”，而於輪出 訊號102冑發計數器94而達到預定計數值Ν2後，計數器 94隨即輸出分別對應數值，，1，，、，，0，，、，，1，，、，，〇，，的訊號c〇、 Cl、C2、C3 ’因此當比較器％偵測到訊號c〇、a、。、 C3所傳輸之輸出資料（，，1〇1〇，，）等於比較值N3 (，，⑺⑺，，） 時’比較器96會使其原本輸出的邏輯值”〗，，轉變為邏輯 值”〇”。經由選取控制訊號EN的幫助，邏輯控制器98便可 選擇使用由比較器96所產生的輸出訊號1〇4或是由一外部 時脈產生器所產生的時脈訊號CLK2,如上所述，輸出訊號 104係經由時序控制器90中的除頻器92，計數器94 ,以 及比較器96處理後產生，然而，輸出訊號1〇4 (例如時脈 訊號CLK2 )亦可由-外部時脈產生器直接產生而輸出時序 控制器90,其中時脈訊號CLK2與比較器96輸出的輸出訊 號104對應相同波形（waveform)。因此，根據選取控制訊 號EN的設定，邏輯控制器98可決定使用時序控制器9q 29 1254899 内部產生的輸出訊號104或是時序控制器9〇外部產生的時 脈訊號CLK2。例如，當選取控制訊號εν具有二進位數 值”1時，時序控制器90内部產生的輸出訊號1〇4會被選 取，相反地，當選取控制訊號ΕΝ具有二進位數值” 〇,，時， 時序控制器90外部產生的時脈訊號CLK2會被選取，請注 思，上述選取控制訊號EN之數值與相對應選擇結果係為 可調整，亦即當選取控制訊號EN具有二進位數值”〇,，時， 時序控制器90内部產生的輸出訊號1〇4會被選取而輸出邏 輯控制器98，相反地，當選取控制訊號EN具有二進位數 值”1”時，時序控制器，90外部產生的時脈訊號CLK2會被 選取而輸出邏輯控制器98,均屬本發明之範嘴。總而言之， 使用者可控制邏輯控制器98採用時序控制器9〇内部產生 的輸出訊號HM或是時序控制器⑽外部產生的時脈訊號 ⑽广便適用於對應不同驅動需求之各種液晶顯示裝 置不論疋比較g 96所輸出的輸出訊號1〇4或是時序控制 器9〇外部產生的時脈訊號CLK2均可被邏輯控制器 、進步控制圖二所示之開關64以及圖四至圖六 之開關S1、S2之知作’即是當輸出訊號104之電壓或是 r心虎CLK2之電壓由—電壓位準轉變至另—電壓位準 寺月，J述平均驅動電壓以使複數個像素最後對應 比 值之操作會被啟動。 夜匕 30 1254899 請參閱圖八，圖八為圖七所示之時序控制器9g的運作 時序圖，且由上而下顯示五個波形。第一波形代表圖—所 示之水平同步訊號32,用來決定啟動一閘極控制線％，已 知每一閘極控制線26係由水平同步職32所觸發而啟 動，並於閘極控制線26被啟動後開始驅動位於同—閘極杵 制線26上的像素。此外，本實施例中，於水平同步訊= 32之下降邊緣（famng edge )係對應一閘極控制線^ 作’例如該閘極控制線26將會被第二驅動電路18所啟動， 並且第一驅動電路16開始驅動位於談閘極控制線％上的 像素而分別趨近相對應灰階值。每一閘極控制線％係依序 地且重複地被啟動，亦即一閘極控制線26係定期地被水平 同步訊號32所啟動以便不停地驅動位於其上的像素。如圖 八所示，一閘極控制線於時間T1被啟動一驅動時間 (driving period) ’而另一閘極控制線於時間丁2被啟動另 一驅動時間，其中時間T2與時間T1之間的間隔即為水平 同步訊號32驅動一閘極控制線26之驅動時間。第二波带 代表時脈訊號CLK1，而第三波形代表圖七所示之除頻器 92所輪出的輸出訊號102，明顯地，輪出訊號1〇2的頻率 係為時脈訊號CLK1之頻率的一半，換句話說，輪入除步 器92的控制訊號Pd係設定除數N1為2。假若計數=、 31 1254899 獲得其所要的計數值N2 (設定為8)，則計數器94會輸出 相對應訊號CO、Cl、C2、C3至比較器96，所以控制訊號 Pc亦輸入比較器96以設定對應計數值N2之訊號c〇、Cl、 C2、C3的比較值N3，如圖八所示，第四波形代表輸出訊 號104 ’且於計數器94獲得計數值N2之數值為8之前， 輸出δίΐ5虎104會保持（hold )邏輯值’，ι ’’，然而，當計數器 94獲得計數值N2之數值等於8時，輸出訊號1〇4則於時 間T3由邏輯值”1”轉變為邏輯值，，〇”，同時輸出訊號1〇4於 吟Γ曰Ί 1 j興时Γ曰Ί 〜叫百，不何雙铒值” ( ^ ^ 32於時間Τ2啟動另一閘極控制線時，計數器94以及比 號 較器％會被重置（reset)❿回復其初始狀態，即是計數器 94重新計數輸出訊號102之週期數，且比㈣％重新輸 出原先的初始邏難絲—㈣傳輸線上的 電壓準位，於時間TW，第—驅動電路16開始驅動一像 素由電^至電壓να4 ’且該像素係交換地（) 以相反極性之電壓值軸以避免Μ閃爍⑽加）問題。 關於圖三所示之開關64 ’開關64係由邏輯控制器98所控 制以依據輸出訊號104而連接端點£1與Ε2，亦即a輸出 訊號104由邏輯值，，『轉換至邏輯值”1”時，^器\8 驅使開關64連接端點E1與E2，運算放大器Q便 壓V254來驅動相對應像素，所以於 ' 丨又跑入该像 1254899 素之驅動電壓會趨近電壓V254，而輸出訊號104於時間Τ3 時由邏輯值”1”轉變至邏輯值”0”，同時邏輯控制器98偵測 到上述邏輯準位轉變，因此於時間Τ3後，邏輯控制器98 會驅使開關64連接端點Ε1與Ε3。如前所述，因為以同一 電壓V254驅動的複數個像素經由傳輸該電壓V254的金屬導 線而互相電連接，所以於時間Τ5後，該複數個像素預定朝 預定電壓V254驅動之實際驅動電壓則會經由平均處理而最 後達到趨近該預定電壓V254之一平均電壓（例如Va)。相 較於前次於時間T2與時間T1之間的驅動運作，該像素會 於時間T2後之另一驅動運作中被相反極性的電壓驅動以 · · · 避免產生習知閃爍的問題。如上所述，除頻器92，計數器 94，以及比較器96係用來產生該輸出訊號104，且邏輯控 制器98依據輸出訊號104來控制圖三所示之開關64的操 作，輸出訊號104於時間T1與T3保持邏輯值”1”的持續時 間可經由適當的除數N卜計數值N2，以及比較值N3來調 整。此外，本實施例中，運算放大器62於時間T3後不再 被使用來驅動像素，因此本實施例會於時間T3至時間T2 之間中斷輸入運算放大器62的相關操作電壓，例如中斷驅 動運算放大器62所需的偏壓（bias voltage)以降低運算放 大電路的整體功率消耗。由於不同的液晶顯示裝置本身具 有其特定電路負載（loading )，換句話說，相較於另一液晶 1254899 顯示裝置，-液晶顯示裝置可能 達到預歧階值，_f0lT1至相τ=_驅動像素 的相對應〜、、、運异放大态62 干MM b W料貞_液晶顯 Γ:= 間T1至時間τ3的間隔較短，因 匕時序控制為90便可經由適當調整以使時間们至時間乃 之間對應較短的間隔，運算放大器62便可於時間T3至時 間Τ2的間隔中中斷其操作電壓以達到省電的目的 地，對於具有較大電路負載的液晶顯示裝置來說，其所需 之時間ΤΠ至時間Τ3的間隔較長，所以時序控制㈣便可 經由適當調整以使時間T1至時間Τ3之㈣應較㈣_ 以便順利地驅動像素達騎需灰階值，目崎算放大器62 便亦可於時間Τ3至時間丁2的間隔中中斷其操作電壓以達 到省電的目的。由上述敘述可知’同—本發明時序控制器 9〇可應用於各種具有不同電路負載的液晶顯示裝置，且輸 出訊號1G4之波形係為可調整的，以便符合每—液晶齡 裝置之特定驅動需求來達到最佳的省電能力（ power saving capacity )。圖四至圖六所示之開關$μ的 操作程序類似於圖三所示之開關62,於時間π至時間丁3， 開關Si被啟動以使運算放大器72、73、74、75可驅_ 對應像素，於時間T3時，開關S1被關閉，並且若運算放 大器於時間T3之前預定以同一輸入電壓驅動相鄰像:至 1254899 同一灰階值，則對應該的相鄰像素之開關S2亦會同時啟 動，因此驅動相鄰像素之電壓便會於時間T3至T2被平均 而均對應於》平均電壓。同樣地，運算放大器72、73、74、 75於時間Τ3後亦不再用來驅動像素。本實施例中，輸入 運异放大$ 72、73、74、75的操作電壓（例如偏屡）會中 斷輸入以Pf低功率消耗，此外，亦可切斷使用於第二電源 供應裝置22及分壓電路17的電力供應以大幅降低功率消 耗，並且可依據液晶顯示|置的電路負載來適度調整時間 T!至T3的時段，以及透過時序控制器9〇中除數m，計 數值N2，Μ及比杈值奶的適當設定來使液晶顯示裝置可 以節省最多的電力。 相較於！知技術，本發明驅動方法使用開關來連接輸, 緩衝㈣輸出端’所以電源供應裝置可輸出—目把電壓: 位來驅動同-行上的複數個像素趨近㈣目標電^位 雖然不同驅動元件之輸出端的電壓值因為 之輸出電壓偏移量影響而不—致，然而當輪^ = 出端經由開關輔助而互相電連接時，原先各驅術时之4 出端的不同電壓值會朝該不同電壓值之平均電严70件之專 然該平均電壓可能並非精確地等於該目標電壓=驅動’ ' 經由本發明驅動方法可使位於同—行且 位’但j 罕月同—目標1 1254899 二=!最後均對應同，_，所以，本發明 階rV致Γ ·列輸出電壓偏移量所帶來的灰 、目關輸出緩衝器（例如運算放大器）於平均電 私中不再需要用來驅動像素，所以，本發明驅 平均電壓的操作啟動後便切斷該輸出緩衝器的操 座例如驅動該輪出緩衝器的偏壓）以降低功率消耗 再者’本發_動方法使用—時序控制器來決定平均電壓 :、:的啟始時間’ m《始時間可經由控制輸人該時序控 、丨》。之》又定值來進一步地調整，以便符合不同電路負载之 液晶顯示裝置的需求。經由適當啟始時間的調整，相對應 液晶顯示裝置便可具有最大的省電能力。 、 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明專利之涵 盖範圍。 【圖式簡單說明】 圖一為習知薄膜電晶體液晶顯示裝置的示意圖。 圖二為圖一所示之第一驅動電路的示意圖。 圖二為本發明第一種運算放大電路的示意圖。 36 1254899 圖四為本發明第二種運算放大電路的示意圖 圖五為本發明第三種運算放大電路的示意圖。 圖六為圖五所示之放A與像素之_連接示意圖。 圖七為本發明時序控制器的功能方塊圖 圖八為圖七所示之時序控制器的運作時序圖。 【主要元件符號說明】 10 液晶顯不裝置 12 液晶面板 14 控制電路 16 第一驅動電路 17 分壓電路 18 第二驅動電路 20 第一電源供應裝置 22 第二電源供應震置 24 資料傳輸線 26 閘極控制線 28、38 、39、40、41、42、43 薄膜電晶體 30、50 、51、52、53、54、55 電容 32 水平同步訊號 34 垂直同步訊號 36 顯示驅動資料 37、60 、70、80 運算放大電路 44、45 、46、47、48、49、62、 72、73 、74、75運算放大器 56 電壓選擇電路 64 開關 66 金屬導線 82 像素 90 時序控制器 1254899 92 除頻器 94 計數器 96 比較器 98 邏輯控制器 38Cl, C2, η. Then, the comparator 96 originally outputs a logic value of "1", and after the round-out signal 102 bursts the counter 94 to reach the predetermined count value Ν2, the counter 94 then outputs the corresponding values respectively, 1, 1, , ,, 0,,,,, 1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The output data transmitted by C3 (,, 1〇1〇,,) is equal to the comparison value N3 (,, (7)(7),,). When the comparator 96 will make its original output logic value, it will be converted into a logic value. By selecting the control signal EN, the logic controller 98 can select to use the output signal 1〇4 generated by the comparator 96 or the clock signal CLK2 generated by an external clock generator, as described above. The output signal 104 is generated by the frequency divider 92, the counter 94, and the comparator 96 in the timing controller 90. However, the output signal 1〇4 (for example, the clock signal CLK2) can also be generated by the external clock. The controller directly outputs the output timing controller 90, wherein the clock signal CLK2 and the output signal 104 output by the comparator 96 correspond to the same waveform. Therefore, according to the setting of the selection control signal EN, the logic controller 98 can decide to use the timing control. 9q 29 1254899 The internally generated output signal 104 or the externally generated clock signal CLK2 of the timing controller 9 . For example, when the selected control signal εν has a binary value "1", the timing controller 90 is The generated output signal 1〇4 will be selected. Conversely, when the control signal 选取 has a binary value “””, the clock signal CLK2 generated by the timing controller 90 will be selected. Please note that the above selection The value of the control signal EN and the corresponding selection result are adjustable, that is, when the control signal EN is selected to have a binary value "〇", the output signal 1〇4 generated by the timing controller 90 is selected and the output logic is output. The controller 98, conversely, when the control signal EN is selected to have the binary value "1", the clock signal CLK2 generated by the timing controller 90 is selected and output to the logic controller 98, which are all exemplary mouthpieces of the present invention. . In summary, the user control logic controller 98 can use the output signal HM generated by the timing controller 9 or the clock signal (10) generated externally by the timing controller (10) to be suitable for various liquid crystal display devices corresponding to different driving requirements. Comparing the output signal 1〇4 output by g 96 or the clock signal CLK2 generated by the timing controller 9〇 can be controlled by the logic controller, the switch 64 shown in the control control diagram 2, and the switch S1 of FIG. 4 to FIG. The knowledge of S2 is that when the voltage of the output signal 104 or the voltage of the rxinhu CLK2 is changed from the voltage level to the other voltage level, the average driving voltage is such that the final pixel corresponds to the ratio. The operation will be started. Nightingale 30 1254899 Please refer to Fig. 8. Fig. 8 is a timing chart showing the operation of the timing controller 9g shown in Fig. 7, and five waveforms are displayed from top to bottom. The first waveform represents a horizontal sync signal 32 as shown in the figure for determining the start of a gate control line %. It is known that each gate control line 26 is triggered by a horizontal sync 32 and is controlled at the gate. After line 26 is activated, it begins to drive the pixels on the same-gate junction line 26. In addition, in this embodiment, the falling edge of the horizontal sync signal=32 corresponds to a gate control line, for example, the gate control line 26 will be activated by the second driving circuit 18, and A drive circuit 16 begins to drive the pixels located on the gate control line % to approach the corresponding gray scale values, respectively. Each gate control line % is sequentially and repeatedly enabled, i.e., a gate control line 26 is periodically activated by the horizontal sync signal 32 to continuously drive the pixels located thereon. As shown in FIG. 8, a gate control line is activated for a driving period at time T1 and another gate control line is activated for another driving time at time T2, wherein time T2 is between time T1. The interval is the driving time at which the horizontal synchronizing signal 32 drives a gate control line 26. The second band represents the clock signal CLK1, and the third waveform represents the output signal 102 of the frequency divider 92 shown in FIG. 7. Obviously, the frequency of the wheel signal 1〇2 is the clock signal CLK1. Half of the frequency, in other words, the control signal Pd that is turned into the pacer 92 sets the divisor N1 to be two. If the count =, 31 1254899 obtains its desired count value N2 (set to 8), the counter 94 will output the corresponding signals CO, Cl, C2, C3 to the comparator 96, so the control signal Pc is also input to the comparator 96 to set Corresponding to the count value N2, the comparison value N3 of the signals c〇, Cl, C2, C3, as shown in FIG. 8, the fourth waveform represents the output signal 104' and before the counter 94 obtains the value of the count value N2 is 8, the output δίΐ5 tiger 104 will hold (hold) the logical value ', ι '', however, when the counter 94 obtains the value of the count value N2 equal to 8, the output signal 1〇4 is converted to a logical value by the logical value "1" at time T3, 〇", at the same time output signal 1〇4吟Γ曰Ί吟Γ曰Ί 1 j 兴时Γ曰Ί~叫百,不双双铒值” ( ^ ^ 32 when time Τ 2 starts another gate control line, counter 94 and The comparator will reset (reset) and return to its initial state, that is, the counter 94 recounts the number of cycles of the output signal 102, and re-outputs the original initial logic wire (4) on the transmission line. Bit, at time TW, the first drive circuit 16 starts to drive one By an electric voltage to the prime ^ να4 'and the pixel-based exchange (In) to a polarity opposite to the voltage value of the axis to avoid flicker Μ ⑽ plus) problem. The switch 64' switch 64 shown in FIG. 3 is controlled by the logic controller 98 to connect the terminals £1 and Ε2 according to the output signal 104, that is, the a output signal 104 is a logical value, "convert to a logic value". When 1", the device \8 drives the switch 64 to connect the terminals E1 and E2, and the operational amplifier Q presses V254 to drive the corresponding pixel, so the driving voltage of the image that is rushed into the image of 1254899 will approach the voltage V254. The output signal 104 transitions from a logic value of "1" to a logic value of "0" at time Τ3, while the logic controller 98 detects the above logic level transition, so after time Τ3, the logic controller 98 drives the switch 64. Connect endpoints Ε1 and Ε3. As described above, since a plurality of pixels driven by the same voltage V254 are electrically connected to each other via a metal wire that transmits the voltage V254, after the time Τ5, the actual driving voltage of the plurality of pixels is predetermined to be driven toward the predetermined voltage V254. Finally, an average voltage (for example, Va) approaching the predetermined voltage V254 is reached via the averaging process. Compared to the previous driving operation between time T2 and time T1, the pixel is driven by a voltage of opposite polarity in another driving operation after time T2 to avoid the problem of conventional flicker. As described above, the frequency divider 92, the counter 94, and the comparator 96 are used to generate the output signal 104, and the logic controller 98 controls the operation of the switch 64 shown in FIG. 3 according to the output signal 104, and the output signal 104 is The duration in which the time T1 and T3 hold the logical value "1" can be adjusted via the appropriate divisor N count value N2, and the comparison value N3. In addition, in this embodiment, the operational amplifier 62 is no longer used to drive pixels after time T3. Therefore, the present embodiment interrupts the input operation voltage of the operational amplifier 62 between time T3 and time T2, for example, interrupting the operational amplifier 62. The required bias voltage is used to reduce the overall power consumption of the operational amplifier circuit. Since different liquid crystal display devices have their own specific circuit loading, in other words, compared to another liquid crystal 1254899 display device, the liquid crystal display device may reach a pre-discrimination value, _f0lT1 to phase τ=_ drive pixel Corresponding to ~,,, and different amplification states 62 dry MM b W material 液晶 liquid crystal display: = interval between T1 and time τ3 is shorter, because the timing control is 90 can be adjusted to make time to time Between the shorter intervals, the operational amplifier 62 can interrupt its operating voltage in the interval from time T3 to time 以2 to achieve the destination of power saving, and for a liquid crystal display device having a large circuit load, The time required to reach the time Τ3 is longer, so the timing control (4) can be adjusted appropriately so that the time T1 to the time Τ3 (4) should be compared with the (4) _ in order to smoothly drive the pixel to the required gray scale value, and the target amplifier 62 It is also possible to interrupt its operating voltage in the interval of time Τ3 to time □2 to achieve power saving. It can be seen from the above description that the same timing controller 9 can be applied to various liquid crystal display devices having different circuit loads, and the waveform of the output signal 1G4 is adjustable to meet the specific driving requirements of each liquid crystal age device. To achieve the best power saving capacity. The operation procedure of the switch $μ shown in FIG. 4 to FIG. 6 is similar to the switch 62 shown in FIG. 3, and at time π to time D3, the switch Si is activated to make the operational amplifiers 72, 73, 74, 75 driveable. Pixel, at time T3, switch S1 is turned off, and if the operational amplifier is scheduled to drive adjacent images with the same input voltage before time T3: to the same grayscale value of 1254899, then the corresponding adjacent pixel switch S2 will also be Startup, so the voltage driving the adjacent pixels is averaged over time T3 to T2 and both correspond to the "average voltage." Similarly, operational amplifiers 72, 73, 74, 75 are no longer used to drive pixels after time Τ3. In this embodiment, the operating voltages (eg, offsets) of the input differential amplifications of $72, 73, 74, and 75 may interrupt the input with low power consumption of Pf, and may also be cut off for use in the second power supply device 22 and points. The power supply of the voltage circuit 17 is to greatly reduce the power consumption, and the period of time T! to T3 can be moderately adjusted according to the circuit load of the liquid crystal display, and the divisor m, the count value N2, is transmitted through the timing controller 9适当 and the appropriate settings for the value of the milk to make the liquid crystal display device can save the most power. Compared to! Knowing the technology, the driving method of the present invention uses a switch to connect and output, and buffers (four) the output terminal' so that the power supply device can output - the voltage of the target: the bit drives the plurality of pixels on the same line to approach (4) the target electric potential is differently driven The voltage value at the output of the component is not affected by the output voltage offset. However, when the wheel ^ = terminal is electrically connected to each other via the switch assist, the different voltage values at the 4th output of the original drive will face The average voltage of the different voltage values is 70. The average voltage may not be exactly equal to the target voltage = drive ' ' can be located in the same line and bit 'by the same way as the drive method of the present invention - but the target 1 1254899 Second =! Finally, they all correspond to the same, _, so, the invention of the stage rV causes Γ · column output voltage offset caused by the gray, the off output buffer (such as operational amplifier) is no longer needed in the average electric private To drive the pixel, so that the operation of the average voltage of the present invention is turned off, the operation of the output buffer is turned off, for example, the bias of the wheel buffer is driven to reduce the power consumption. Use - to determine the average voltage timing controller:,: the start time 'm "start time can be controlled via the control input of the timing, Shu." It is also fixed to further adjust to meet the needs of liquid crystal display devices with different circuit loads. With the appropriate start time adjustment, the corresponding liquid crystal display device can have the maximum power saving capability. The above description is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the scope of the present invention should be covered by the patent of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a conventional thin film transistor liquid crystal display device. FIG. 2 is a schematic diagram of the first driving circuit shown in FIG. Figure 2 is a schematic diagram of the first operational amplifier circuit of the present invention. 36 1254899 FIG. 4 is a schematic diagram of a second operational amplifier circuit of the present invention. FIG. 5 is a schematic diagram of a third operational amplifier circuit of the present invention. FIG. 6 is a schematic diagram of the connection between the A and the pixel shown in FIG. Figure 7 is a functional block diagram of the timing controller of the present invention. Figure 8 is a timing chart of the operation of the timing controller shown in Figure 7. [Main component symbol description] 10 Liquid crystal display device 12 Liquid crystal panel 14 Control circuit 16 First drive circuit 17 Voltage dividing circuit 18 Second drive circuit 20 First power supply device 22 Second power supply shock 24 Data transmission line 26 Gate Pole control lines 28, 38, 39, 40, 41, 42, 43 Thin film transistors 30, 50, 51, 52, 53, 54, 55 Capacitor 32 Horizontal sync signal 34 Vertical sync signal 36 Display drive data 37, 60, 70 80 operational amplifier circuits 44, 45, 46, 47, 48, 49, 62, 72, 73, 74, 75 operational amplifier 56 voltage selection circuit 64 switch 66 metal wire 82 pixel 90 timing controller 1254899 92 frequency divider 94 counter 96 Comparator 98 Logic Controller 38