JP2000148098A - Peripheral circuit for liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit for a liquid crystal display with less power consumption. SOLUTION: The circuit for the liquid crystal display is provided with at least a first column data driver 550 outputting a first video signal, at least a second column data driver 560 outputting a second video signal, a first switch circuit 510 switching between two adjacent column conductors in response to a control signal and a second switch circuit 520 switching between two adjacent column conductors in response to the control signal. Further, discharge circuits 530, 540 discharging residual charges on two adjacent column conductors are connected between two adjacent column conductors. Further, a display array 500 responding to the first video signal and the second video signal is connected to a row selection driver 570.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display (L).
More specifically, the present invention relates to a peripheral device of a CD, and more particularly to a driving circuit of column data for a liquid crystal display.

[0002]

2. Description of the Related Art Liquid crystal displays (LCDs) are known as space-saving and high-quality displays. In general,
A typical circuit of a liquid crystal display is illustrated in FIG.
A matrix display typically comprises an LCD display array 100, which further comprises a plurality of display elements 50 arranged in a row and column matrix. A switching device is connected to the display element 50 and controls the application of a video signal to the display element. Each display element 50 operates as a switching device including the pixel capacitor 10 driven by the transistor 20. One electrode of the pixel capacitor 10 is on one side of the matrix display, and the other electrode of the pixel capacitor 10 is formed on the other side of the matrix display. Transistor 20
It is a thin film transistor (TFT) usually formed on a transparent material such as glass. The switching transistor 20 has a source electrode which connects to a capacitor electrode formed on glass on the same side of the display matrix as the switching transistor. The drain electrodes of all the switching transistors 20 in a column are connected to a column data driver (D1, or D2, D3 ...) through the same column conductor to which the video signal is applied. The gate electrodes of all the switching transistors 20 in a row are connected to a row selection driver 60 through a common column line, and a row selection signal is applied using the row selection driver 60, and all the switching transistors 20 in the selected row are connected.
Turn on. The row conductors are scanned, all the switching transistors 20 of a row are turned on according to the row selection signal, and all the rows are continuously selected. At the same time, video signals are applied to the column conductors in synchronization with the selected row. When the switching transistor 20 of a certain row is selected by the row selection signal, the video signal supplied to the switching transistor 20 charges the pixel capacitor 10 to a voltage value corresponding to the video signal of the column conductor. Thus, each pixel capacitor 10 having an electrode on the opposite side of the matrix display acts as a capacitor. When the signal of the selected row is removed, the charge on the pixel capacitor 10 is stored there until the next iteration, and at the next iteration the row selection signal selects the row again and the new voltage is stored there . Therefore, an image is displayed on the matrix display by the electric charge stored in the pixel capacitor 10.

FIG. 2 shows a column data driver (D1, D2, D3...)
Shows the waveform of the video signal supplied to the switching transistor 20. Since the data driving circuit is usually driven by an AC signal, the polarity of the operation waveform changes alternately. Therefore,
As shown in FIG. 2, the operating range of the column data drivers (D1, D2, D3,...) Is twice as large as when a unipolar DC power supply is used. The voltage level of the column data driver (D1, D2, D3 ...) switches between + Vn and -Vn, but switches between + Vn and V0 for DC power. For example, in the case of a 256-level color liquid crystal display, in order to supply a sufficient operating voltage level to the column data drivers (D1, D2, D3...) Under an operating voltage supplied by an AC power source, a column data driver ( D1, D2, D
The operation of 3 ...) is not from V255 to V0 but from V255 to -V255
Need to be extended to

Referring to FIGS. 3A and 3B, the polarity of the column video signal applied to the display element 50 for the LCD display array 100 of FIG. 1 is shown. In each column data driver (D1, D2, D3 ...), the polarity of the column video signal generated by the column data driver (D1, D2, D3 ...) is between the positive and negative polarities because of the AC signal described above. Can be switched alternately. (A) and (B) of FIG.
A polarity 70 of two consecutively input video signals applied to the display element 50 is shown, a positive polarity of the input video signal is represented by “+”, and a negative is represented by “−”. The polarities of both the odd-numbered video signal and the even-numbered video signal are the same positive as shown in (A), and the video signal in the next order is negative as shown in (B). 4 (A) and 4 (B), other operating conditions of the polarity of the odd-numbered video signal and the even-numbered video signal applied to the display element 50 are shown. As shown in (A), the polarity of the odd-numbered video signal is positive, and the polarity of the even-numbered video signal is negative. Next, the polarity of the video signal of the odd column and the even column is exchanged as shown in (B), that is, the polarity of the video signal of the odd column is negative and the polarity of the video signal of the even column is positive. . Generally, in order to apply the voltage to a liquid crystal display for industrial production, the latter polarity change shown in FIGS. 4A and 4B is preferable. This is because if the video signals in the adjacent odd-numbered columns and the video signals in the even-numbered columns are alternately changed, it looks comfortable.

[0005]

SUMMARY OF THE INVENTION It is therefore a first object of the present invention to provide a circuit for a liquid crystal display with reduced power consumption. By switching the video signals received by the display elements of each column using the switching circuit, the DC bias of the column data driver can be reduced by half. Second, the circuit of the present invention also discharges residual charges in the column conductors by a discharge circuit connected between two adjacent column conductors before a continuous video signal is transferred to the display array.

[0006]

A liquid crystal display circuit according to the present invention comprises at least one first column data driver for outputting a first video signal and at least one second column data driver for outputting a second video signal. A first switching circuit for switching between two adjacent column conductors in response to a control signal, and a second switching circuit for switching between two adjacent column conductors in response to a control signal. Furthermore, a discharge circuit is connected between the two adjacent column conductors for discharging the residual charge of the two adjacent column conductors. A display array responsive to the first video signal and the second video signal connects to a row selection driver.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing aspects and many advantages of the present invention will be readily appreciated when the invention is better understood with reference to the following detailed description, taken in conjunction with the drawings, in which: FIG. Would. FIG. 5 is a functional block diagram showing a peripheral circuit for a liquid crystal display (LCD) of the present invention. 5 is basically composed of an LCD display array 500 and a first switching circuit 510.
, A second switching circuit 520, a first discharging circuit 530, a second discharging circuit 540, a first column data driver 550, a second column data driver 560, and a row selecting driver 570. First
First switching circuit 510 connected to column data driver 550
Is connected to the display array 500 through two terminals A and B.
First discharge circuit 530 is arranged between terminals A and B. Also,
Second switching circuit 520 connected to second column data driver 560
Is connected to the display array 500 through two terminals A ′ and B ′. Second discharge circuit 540 is coupled between terminals A 'and B'.
Display array 500 controlled by row selection driver 570
Receives video signals from the first column data driver 550 and the second column data driver 560. The first switching circuit 510 is
In response to the control signal Sc, the video signal driven by the first column data driver 550 is received, and the selected terminal A or B
To transfer the video signal to the display array 500.

Further, the second switching circuit 520 outputs the control signal Sc
Receives the video signal driven by the second column data driver 560 and transfers the video signal to the display array 500 through the selected terminal A ′ or B ′. 1st switching circuit 51
The video signal switched by 0 and transferred to the display array 500 through the terminal A is synchronized with the video signal switched by the second switching circuit 520 and transferred to the display array 500 through the terminal A ′. Subsequently, terminals B and B 'are connected to the first and second terminals, respectively.
It is turned on by the switching circuits 510 and 520, and the video signals in the next order are transferred from the first column data driver 550 and the second column data driver 560. The first discharge circuit 530 and the second discharge circuit 540 responsive to the control signal Sc3 are turned on during a period after a video signal arrives at the display array 500 and before a next sequence of video signals arrives, and a circuit for the display array 500 is provided. To discharge the remaining charge.

FIG. 6 is a detailed diagram of the circuit of FIG. The structure of the row selection driver 570 and the display array 500 is the same as the circuit of FIG.
A plurality of display elements 50 are arranged in a matrix of rows and columns to form a display array 500. Further, a first switching circuit 510 and a second switching circuit 520
Include MOS (metal-oxide-semiconductor) transistors T1 and T2. The MOS transistor T1 turns on in response to the control signal Sc1, and the MOS transistor T2 turns on the control signal S1.
When turned off in response to c2, the first row data driver 5
The video signals driven by 50 and the second column data driver 560 are input to the odd-numbered and even-numbered lines of the display array 500 through the MOS transistor T1.
The odd rows of conductors are connected between terminals A and B ', and the even rows of conductors are connected between terminals B and A'. Next, when the MOS transistor T1 responsive to the control signal Sc1 is turned off, the MOS transistor T2 responsive to the control signal Sc2 is turned on,
The signals in the next order are transferred from the first column data driver 550 and the second column data driver 560 to even-numbered lines and odd-numbered lines, respectively. The first discharge circuit 530 and the second discharge circuit 540 both include a MOS transistor T3, and when the MOS transistors T1 and T2 are simultaneously turned off, the control signal Sc3
The MOS transistor T3, which responds to the ON state, is turned on, and discharges the residual charges remaining in the odd and even lines of the display array 500.

In the first switching circuit 510, the MOS transistor T1 is connected to the odd-numbered column conductor and the first column data driver 550.
And the MOS transistor T2 is connected between the conductors of the even columns and the first column data driver 550. The MOS transistor T3 of the first discharging circuit 530 uses the odd-numbered column conductors and the even-numbered column conductors to form the MOS transistor T1.
And connect with T2. The gates of the MOS transistors T1, T2, T3 are external control means for controlling the state of the MOS transistors.
(Not shown). Similarly, the second switching circuit 5
At 20, the MOS transistor T2 is connected between the odd column conductor and the second column data driver 560, and the MOS transistor T1 is connected between the even column conductor and the second column data driver 560.
Connected between The MOS transistor T3 of the second discharge circuit 540 is connected to the MOS transistors T1 and T2, respectively, using the odd-numbered line conductors and the even-numbered line conductors. The gates of the MOS transistors T1, T2, T3 are controlled by external control means for controlling the states of the MOS transistors.

FIG. 7 is a waveform diagram showing transmission of a video signal of the liquid crystal display of the present invention. Horizontal sync signal (H-Sync)
Is provided by a logic control means (not shown). State 2
, The H-Sync pulse passes, the MOS transistors T1 and T2 are both turned off, the MOS transistor T3 is turned on,
Discharge residual charge remaining in the odd and even rows of conductors. State 1
, The MOS transistor T1 is turned on, during which time M
OS transistors T2 and T3 are turned off. Therefore, the video signal is transferred from the first column data driver 550 to the odd line conductors. Similarly, the video signal of the second column data driver 560 is transferred to the conductors of the even columns. H-Syn in state 2
The c-pulse passes, the MOS transistors T1 and T2 are both turned off, and the MOS transistor T3 is turned on, discharging the residual charges remaining in the odd and even lines. Next, state 3 is set, and the MOS transistor T2 is turned on, during which the MOS transistors T1 and T3 are turned off. Therefore, the video signal is transferred from the first column data driver 550 to the conductors in the even columns. Similarly, the video signal of the second column data driver 560 is transferred to the odd column conductors.

Since the polarities of two adjacent column conductors are opposite to each other, the discharge function discharges the residual charges remaining in the odd and even columns of conductors so that the display array is not latched up and the next image sequence is displayed. The operating voltage level required for the signal can be reduced. By using the circuit of the present invention, the initial DC bias level can be reduced by half. For example, in a circuit with a bias of 0 to 10 volts, the operating waveform of the column data driver needs to be extended from 0 to 10 volts to fit the circuit. But,
In accordance with the present invention, there may be a pair of two-row data drivers with different operating waveforms, for example, one from 0 to 5 volts and the other from 5 to 10 volts. This is because the residual charges are discharged before the next column video signal arrives from the pair of column data drivers. Whenever each column data driver provides the correct sequence of column video signals, the clocks of the video signals of the columns of the first and second column data drivers must be exchanged before the video signal is input to the display array 500. .

Conventionally, if the operating voltage range of the data driver is 0 to 5 volts for the negative polarity portion and 5 to 10 volts for the positive polarity portion, a bias of 0 to 10 volts is applied to each drive circuit. There is a need. This is because each data driver circuit operates in both operating ranges for different periods of time. In the present invention, for example, an odd-numbered row has an operating range of 0 to 5 volts, and an even-numbered row has an operating range of 5 to 10 volts. When the data of the positive polarity is input to the column conductor, the circuit is switched to the data driver circuit of the even-numbered column, and when the data of the negative polarity is input in the next period, the circuit is switched to the circuit of the odd-numbered column. With this switching function, odd columns can always be kept in the range of 0 to 5 volts, and even columns can be kept in the range of 5 to 10 volts. Since the circuit of each data driver operates in a half range of the conventional case, the range of the DC bias of the odd-numbered column and the even-numbered column can be separated to reduce the operating voltage range.

As can be seen from the above description, the present invention has the following advantages. For example, the present invention can reduce power consumption. It uses a switching circuit to switch the video signal received by the display element in each column between the first and second column conductors, thereby reducing the DC bias of the column data driver for the liquid crystal display to the initial voltage level. This is because it is reduced by half. Second, before the next sequence of video signals is transferred to the display array 500, the residual charge in the column conductors is discharged by a discharge circuit connected between two adjacent column conductors. In view of the prior art structure, there is the function of pre-charging the column conductors by the discharge circuit, and the voltage level can be zeroed by the discharge function. Third, by forming MOS transistors on a glass substrate, the circuit of the present invention can be used for TFT-polycrystalline silicon and amorphous silicon.
Can be applied to LCD.

As will be appreciated by those skilled in the art, the preferred embodiments of the present invention are illustrative of the invention rather than limiting the invention. Various modifications and similar structures are included within the spirit and scope of the appended claims, and the claims are to be read most broadly to include all such modifications and similar structures. While the preferred embodiment of the invention has been described, it will be appreciated that various modifications can be made without departing from the spirit and scope of the invention.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a conventional liquid crystal display circuit.

FIG. 2 is a schematic diagram of a video signal applied to a conventional switching transistor.

FIG. 3 is a schematic diagram illustrating a polarity of a column video signal applied to a conventional display element.

FIG. 4 is a schematic diagram showing the polarity of a column video signal applied to a conventional display element.

FIG. 5 is a block diagram of a circuit of the liquid crystal display of the present invention.

FIG. 6 is a detailed diagram of a circuit of the liquid crystal display of the present invention.

FIG. 7 is a waveform diagram showing a MOS device of the circuit of the liquid crystal display of the present invention.

[Explanation of symbols]

 10 Pixel capacitor 20 Switching transistor 50 Display element 60 Row selection driver 70 Polarity 100 Display array 500 Display array 510 First switching circuit 520 Second switching circuit 530 First discharging circuit 540 Second discharging circuit 550 First column data driver 560 Second Column data driver 570 row selection driver

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623B 623W F-term (Reference) 2H089 HA17 KA17 QA16 TA03 TA09 2H092 GA38 GA46 GA58 JA24 JB13 MA58 NA25 NA26 PA06 5C006 AA01 AA16 AC11 AC26 AF41 AF43 AF72 BB16 BC03 BC06 BC13 BC16 BC20 BF11 BF34 FA47 5C080 AA10 BB05 DD26 EE17 FF11 GG08 JJ02 JJ03 JJ04

Claims (20)

[Claims] 1. A circuit for applying a video signal to a liquid crystal display, comprising: switching means for switching between two column conductors; discharging means for connecting between the two column conductors and discharging residual charges in the two column conductors. And a display array for displaying an image in response to a video signal. 2. The circuit according to claim 1, wherein said switching means comprises a first MOS (metal-oxide) having a gate, a first electrode, and a second electrode.
-semiconductor) transistor, wherein the gate of the first MOS transistor switches the state of the first MOS transistor in response to a first control signal,
The first electrode of the transistor is connected to a column data driver, the second electrode of the first MOS transistor is connected to a first column conductor of the two column conductors, and a gate, a first electrode and a second electrode are connected. A second MOS transistor having a gate of the second MOS transistor,
The state of the second MOS transistor is switched in response to a second control signal, the first electrode of the second MOS transistor is connected to the column data driver, and the second electrode of the second MOS transistor is connected to the two electrodes. The circuit that connects to the second column conductor of the column conductor. 3. The circuit according to claim 2, wherein only when the second MOS transistor is off, the first MOS transistor responsive to the first control signal is turned on, and the first MOS transistor is turned off. A circuit that turns on the second MOS transistor only in response to the second control signal. 4. The circuit according to claim 1, wherein said discharging means includes a third MOS transistor having a gate and an electrode, wherein said electrode of said third MOS transistor is connected to said third MOS transistor.
A circuit connected between two column conductors, wherein the gate of the third MOS transistor is responsive to a third control signal. 5. The circuit according to claim 4, wherein the third MOS transistor responds to the third control signal only when both the first MOS transistor and the second MOS transistor are off.
A circuit where transistors are turned on. 6. A liquid crystal display circuit, comprising: at least one first column data driver for outputting a first video signal; at least one second column data driver for outputting a second video signal; First switching means for switching between two column conductors; second switching means for switching between two column conductors in response to a control signal; connecting between the two column conductors and residual charges of the two column conductors And a display array for displaying an image in response to the first video signal and the second video signal. 7. The circuit according to claim 6, wherein said first switching means is connected to said discharging means, and said first switching means is a first MOS transistor having a gate, a first electrode and a second electrode. Wherein the gate of the first MOS transistor comprises:
In response to a first control signal, the state of the first MOS transistor is switched, the first electrode of the first MOS transistor is connected to a first column data driver, and the second electrode of the first MOS transistor is connected to the second electrode. A second MOS transistor having a gate, a first electrode, and a second electrode connected to a first column conductor of the two column conductors, wherein the gate of the second MOS transistor comprises:
A state of the second MOS transistor is switched in response to a second control signal, and the first electrode of the second MOS transistor is connected to the first column data driver, and the second MOS transistor is connected to the second MOS transistor.
The second electrode of the transistor is the second electrode of the two column conductors.
A circuit that connects to two-row conductors. 8. The circuit according to claim 7, wherein only when the second MOS transistor is off, the first MOS transistor responsive to the first control signal is turned on, and the first MOS transistor is turned off. A circuit that turns on the second MOS transistor only in response to the second control signal. 9. The circuit according to claim 7, wherein said discharging means includes a fifth MOS transistor having a gate and an electrode, wherein said electrode of said fifth MOS transistor is connected to said fifth MOS transistor.
A circuit connected between two column conductors, wherein the gate of the fifth MOS transistor is responsive to a third control signal. 10. The circuit according to claim 9, wherein the fifth MOS transistor responds to the third control signal only when both the first MOS transistor and the second MOS transistor are off.
Circuit where the S transistor is turned on. 11. The circuit according to claim 6, wherein said second switching means is connected to said discharging means, and said second switching means is a third MOS transistor having a gate, a first electrode and a second electrode. Wherein the gate of the third MOS transistor comprises:
In response to a first control signal, the state of the third MOS transistor is switched, the first electrode of the third MOS transistor is connected to the second column data driver, and the third MOS transistor
The second electrode of the transistor is the second electrode of the two column conductors.
A fourth MOS transistor having a gate, a first electrode, and a second electrode connected to the two-column conductor, wherein the gate of the fourth MOS transistor includes:
The state of the fourth MOS transistor is switched in response to a second control signal, and the first electrode of the fourth MOS transistor is connected to the second column data driver, and
The second electrode of the transistor is the second electrode of the two column conductors.
A circuit connected to a single-row conductor. 12. The circuit according to claim 11, wherein only when the fourth MOS transistor is off, the third MOS transistor responsive to the first control signal is turned on, and the third MOS transistor is turned off. A circuit that turns on the fourth MOS transistor only in response to the second control signal. 13. The circuit according to claim 11, wherein the discharging means includes a fifth MOS transistor having a gate and an electrode, wherein the electrode of the fifth MOS transistor is connected between the two column conductors. A circuit in which the gate of the fifth MOS transistor is responsive to a third control signal. 14. The circuit according to claim 13, wherein the fifth MOS transistor responds to the third control signal only when both the third MOS transistor and the fourth MOS transistor are off.
Circuit where the S transistor is turned on. 15. The circuit according to claim 6, wherein a clock of the first column data driver and a clock of the second column data driver are output before outputting the first video signal and the second video signal. The circuit to be exchanged. 16. A method of displaying video information on a liquid crystal display, comprising: displaying a first video signal on a first column conductor, displaying a second video signal on a second column conductor, and a voltage level of the first column conductor. And making the voltage level of the second column conductor equal. 17. The method of claim 16, comprising a switching circuit connected to the first and second row conductors and switching between the first and second row conductors. 18. The method according to claim 16, wherein the first video signal is driven by a first column data driver, and the second video signal is driven by a second column data driver. 19. The method according to claim 18, wherein before driving the first video signal and the second video signal,
A circuit for exchanging clocks between the first column data driver and the second column data driver. 20. The method according to claim 16, wherein once the first video signal and the second video signal are displayed,
Switching from the first row conductor to the second row conductor.