KR100947773B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device, comprising: a timing controller including a source output enable signal generator for generating a source output enable signal and a gate output enable signal generator for generating a gate output enable signal; And a pulse width variable circuit including a source variable circuit for varying a pulse width of the source output enable signal, and a gate variable circuit for varying a pulse width of the gate output enable signal. The source variable circuit divides a voltage from an external source to generate a first voltage and a first variable resistor to generate a reference voltage, and a first triangle wave generator to generate a triangular wave in a right triangle shape. A first comparator for generating a switching control signal, and a first switch element for varying the width of the source output enable signal in response to the first switching control signal to switch to the data driver.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}             

1 is a block diagram schematically showing a conventional liquid crystal display device.

FIG. 2 is a block diagram illustrating a timing controller shown in FIG. 1. FIG.

3 is a waveform diagram illustrating a pulse width variation of a source output enable signal according to a state of a source option pin shown in FIG. 2;

4 is a waveform diagram illustrating a pulse width variation of a gate output enable signal according to a state of a gate option pin shown in FIG. 2;

5 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 6 is a block diagram illustrating a timing controller shown in FIG. 5. FIG.

FIG. 7 is a circuit diagram illustrating a source output enable pulse width variable part illustrated in FIG. 6.

FIG. 8 is a waveform diagram illustrating a pulse width variation of a source output enable signal output by the source output enable pulse width variable portion shown in FIG. 6; FIG.

FIG. 9 is a circuit diagram illustrating a gate output enable pulse width variable part illustrated in FIG. 6.                 

FIG. 10 is a waveform diagram illustrating a pulse width variation of a gate output enable signal output by the gate output enable pulse width variable portion shown in FIG. 6; FIG.

<Description of Symbols for Main Parts of Drawings>

2, 102 liquid crystal panel 4, 104 data driver

6, 106: gate driver 8, 108: timing controller

110: pulse width variable unit 118: SOE generation unit

120: SOE variable part 130: GOE variable part

140, 190: comparators 142, 192: triangle wave generator

158: GOE generation unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality.

BACKGROUND ART Liquid crystal displays (hereinafter referred to as "LCDs") are becoming increasingly wider in scope due to their light weight, thinness, and low power consumption. According to this trend, LCDs are used for office automation equipment, audio / video equipment, and the like. On the other hand, the LCD is controlled to display the desired image on the screen by adjusting the transmission amount of the light beam according to the image signal applied to the plurality of control switches arranged in a matrix form.

Referring to FIG. 1, a conventional LCD includes a liquid crystal panel 2 in which liquid crystal cells Clc are arranged in a matrix, and gate lines GL connected to gate lines GL of the liquid crystal panel 2. A gate driver 6 for supplying scan pulses to the data, a data driver 4 for supplying video data to the data lines DL of the liquid crystal panel 2, a gate driver 6 and a data driver 4 Is provided with a timing controller (8).

The liquid crystal panel 2 is provided with a spacer (not shown) for injecting liquid crystal between the upper substrate and the lower substrate and keeping the gap between the upper substrate and the lower substrate constant. On the upper substrate of the liquid crystal panel 2, a color filter, a common electrode, a black matrix, and the like, which are not shown, are formed. In addition, the lower substrate of the liquid crystal panel 2 includes thin film transistors TFT and liquid crystal cells Clc formed at respective regions defined by intersections of the gate lines GL and the data lines DL.

The thin film transistor TFT is turned on when the scan signal from the gate lines GL1 to GLn, that is, the gate high voltage VGH is supplied, thereby converting the pixel signal from the data lines DL1 to DLn to the liquid crystal cell Clc. To feed. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate lines GL1 to GLn to maintain the pixel signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell Clc further includes a storage capacitor Cst so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor Cst is formed between the previous gate line and the pixel electrode. The liquid crystal cell Clc realizes gray by adjusting light transmittance by changing an arrangement state of liquid crystals having dielectric anisotropy according to pixel signals charged through the thin film transistor TFT.

The timing controller 8 rearranges the digital video data supplied from the digital video card (not shown) for each of red (R), green (G), and blue (B). Video data R, G, B rearranged by the timing controller 8 is supplied to the data driver 4. In addition, the timing controller 8 generates a data control signal and a gate control signal using the horizontal / vertical synchronization signals H and V input thereto. The data control signal includes a dot clock Dclk, a source shift clock SSC, a source output enable SOE, a polarity inversion signal POL, and the like, and is supplied to the data driver 4. The gate control signal includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like, and is supplied to each of the gate drivers 6.

The data driver 4 outputs a pixel signal of one line for each horizontal period H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 8. Feed to the field (DL). In particular, the data driver 4 converts and supplies the digital video data R, G, and B from the timing controller 8 into an analog video signal using a gamma voltage from a gamma voltage generator not shown. The data driver 4 is composed of a plurality of data drive ICs for separately driving the data lines DL.

The gate driver 6 sequentially supplies the gate high voltage VGH to the gate lines GL in response to the gate control signals GSP, GSC, and GOE from the timing controller 8. Accordingly, the gate driver 6 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate lines GL1 to GLn. The gate driver 6 supplies the gate low voltage VGL in the remaining period in which the gate high voltage VGH is not supplied to the gate lines GL.

In the conventional liquid crystal display device, the charging characteristics of the liquid crystal cell Clc, which have a great influence on the image and the afterimage displayed on the liquid crystal panel 2, have the structure of the liquid crystal panel 2 and the on time of the thin film transistor TFT. And the application time of the analog video signal supplied to the liquid crystal cell Clc. Accordingly, the on time of the thin film transistor TFT is adjusted according to the pulse width of the gate output enable signal among the gate control signals supplied from the timing controller 8 to the gate driver 6, and the liquid crystal cell Clc. Is applied to the pulse width of the source output enable SOE among the data control signals supplied from the timing controller 8 to the data driver 4. The pulse widths of the gate output enable (GOE) and the source output enable (SOE), respectively, are set according to the state of an option pin provided outside the timing controller 8.

Specifically, the timing controller 8 includes a first source option pin SOE1 and a second source option pin SOE2 for varying the pulse width of the source output enable signal SOE as shown in FIG. A first gate option pin (GOE1) and a second gate option pin (GOE2) are provided to vary the pulse width of the gate output enable (GOE) signal.

Each of the first source option pin SOE1 and the second source option pin SOE2 and the first gate option pin GOE1 and the second gate option pin GOE2 is high due to an externally supplied voltage. Or goes low.

Accordingly, the timing controller 8 according to the state of each of the first source option pin (SOE1) and the second source option pin (SOE2) as shown in Figure 3 the pulse width of the source output enable (SOE) signal ( T1, T2, T3, and T4) are variable. For example, the pulse widths T1, T2, T3, and T4 of the source output enable signal SOE according to the state of each of the first source option pin SOE1 and the second source option pin SOE2 are It is set as shown in Table 1.

SOE1 SOE2 SOE pulse width 0 0 1.0㎲ 0 One 1.5 ㎲ One 0 2.0㎲ One One 3.0㎲

As shown in Table 1, when the first source option pin SOE1 goes high and the second source option pin SOE2 goes low, the pulse width of the source output enable signal SOE ( T4) becomes 2.0 ms.

In addition, the timing controller 8 according to the state of each of the first gate option pin GOE1 and the second gate option pin GOE2, as shown in FIG. 4, the pulse width GT1 of the gate output enable GOE signal. , GT2, GT3, GT4).

As described above, the conventional liquid crystal display device varies the pulse width of each of the source output enable (SOE) signal and the gate output enable (GOE) signal according to the state of the external option pin. The number of outputs of each of the source output enable (SOE) signal and the gate output enable (GOE) signal having a pulse width is limited. Accordingly, when the number of outputs of the source output enable (SOE) signal and the gate output enable (GOE) signal having different pulse widths is increased, the number of external option pins increases, requiring a large number of components. Furthermore, the source output enable (SOE) signal and the gate output enable (GOE) according to the structure of the liquid crystal panel 2 and the on time of the thin film transistor TFT and the application time of the analog video signal supplied to the liquid crystal cell Clc. Since the pulse width of the signal is set to an approximation value, the charging characteristics of the liquid crystal cell Clc cannot be optimized. Therefore, in the conventional liquid crystal display device, the charging characteristics of the liquid crystal cell Clc cannot be optimized under an accurate condition, so that an image and an afterimage displayed on the liquid crystal panel 2 are generated, thereby degrading the image quality.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of improving image quality.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal panel; A data driver for supplying a video signal to the liquid crystal panel in response to a source output enable signal; A gate driver for supplying a scanning signal to the liquid crystal panel in response to a gate output enable signal; A timing controller including a source output enable signal generator for generating the source output enable signal and a gate output enable signal generator for generating the gate output enable signal; And a pulse width variable circuit including a source variable circuit for varying a pulse width of the source output enable signal, and a gate variable circuit for varying a pulse width of the gate output enable signal.
The source variable circuit divides a voltage from an external source to generate a first voltage and a first variable resistor to generate a reference voltage, and a first triangle wave generator to generate a triangular wave in a right triangle shape. A first comparator for generating a switching control signal, and a first switch element for varying the width of the source output enable signal in response to the first switching control signal to switch to the data driver.

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The pulse width of the source output enable signal supplied to the first switch element in the liquid crystal display is set to the maximum.

In the liquid crystal display, the first comparator varies a pulse width of the first switching control signal according to a voltage level of the reference voltage according to a change in the resistance value of the variable resistor using a pulse width modulation method.
The gate variable circuit may include a second resistor and a second variable resistor for generating a reference voltage by dividing a voltage from an external source, a second triangle wave generator for generating a triangular wave having a right triangle shape, and using the reference voltage and the triangle wave. And a second comparator for generating a second switching control signal, and a second switch element for changing the pulse width of the gate output enable signal to switch to the gate driver in response to the second switching control signal.

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The pulse width of the gate output enable signal supplied to the second switch element in the liquid crystal display device is set to a maximum.

In the liquid crystal display, the second comparator varies a pulse width of the second switching control signal according to a voltage level of the reference voltage according to a change in the resistance value of the variable resistor using a pulse width modulation method.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 10.

Referring to FIG. 5, a liquid crystal display according to an exemplary embodiment of the present invention is connected to a liquid crystal panel 102 in which liquid crystal cells Clc are arranged in a matrix, and connected to gate lines GL of the liquid crystal panel 102. The gate driver 106 for supplying scan pulses to the gate lines GL, the data driver 104 for supplying video data to the data lines DL of the liquid crystal panel 102, and the gate driver ( 106 and a timing controller 108 for controlling the data driver 4.

The liquid crystal panel 102 includes a spacer (not shown) for injecting liquid crystal between the upper substrate and the lower substrate and maintaining a constant gap between the upper substrate and the lower substrate. The upper substrate of the liquid crystal panel 102 is formed with a color filter, a common electrode, a black matrix, and the like, which are not shown. In addition, the lower substrate of the liquid crystal panel 102 includes thin film transistors TFT and liquid crystal cells Clc formed at respective regions defined by intersections of the gate lines GL and the data lines DL.

The thin film transistor TFT is turned on when the scan signal from the gate lines GL1 to GLn, that is, the gate high voltage VGH is supplied, thereby converting the pixel signal from the data lines DL1 to DLn to the liquid crystal cell Clc. To feed. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate lines GL1 to GLn to maintain the pixel signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell Clc further includes a storage capacitor Cst so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor Cst is formed between the previous gate line and the pixel electrode. The liquid crystal cell Clc realizes gray by adjusting light transmittance by changing an arrangement state of liquid crystals having dielectric anisotropy according to pixel signals charged through the thin film transistor TFT.

The timing controller 108 rearranges the digital video data supplied from the digital video card (not shown) by red (R), green (G), and blue (B). Video data R, G, B rearranged by the timing controller 108 is supplied to the data driver 104. In addition, the timing controller 108 generates a data control signal and a gate control signal using the horizontal / vertical synchronization signals H and V input thereto. The data control signal includes a dot clock Dclk, a source shift clock SSC, a source output enable SOE, a polarity inversion signal POL, and the like, and is supplied to the data driver 104. The gate control signal includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like, and is supplied to each of the gate drivers 106.

The data driver 104 outputs one pixel signal for one line per horizontal period H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 108. Feed to the field (DL). In particular, the data driver 104 converts and supplies the digital video data R, G, and B from the timing controller 108 into an analog video signal using a gamma voltage from a gamma voltage generator not shown. The data driver 104 is composed of a plurality of data drive ICs for separately driving the data lines DL.

The gate driver 106 sequentially supplies the gate high voltage VGH to the gate lines GL in response to the gate control signals GSP, GSC, and GOE from the timing controller 108. Accordingly, the gate driver 106 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate lines GL1 to GLn. The gate driver 106 supplies the gate low voltage VGL in the remaining periods during which the gate high voltage VGH is not supplied to the gate lines GL.

As described above, in the liquid crystal display according to the exemplary embodiment of the present invention, the charging characteristics of the liquid crystal cell Clc having a large influence on the image and the residual image displayed on the liquid crystal panel 102 are determined by the structure of the liquid crystal panel 102 and the thin film transistor ( There is a close relationship between the ON time of the TFT and the application time of the analog video signal supplied to the liquid crystal cell Clc. Accordingly, the on time of the thin film transistor TFT is adjusted according to the pulse width of the gate output enable signal among the gate control signals supplied from the timing controller 108 to the gate driver 106, and the liquid crystal cell Clc. ) Is applied according to the pulse width of the source output enable (SOE) signal among the data control signals supplied from the timing controller 108 to the data driver 104.

To this end, the timing controller 108 of the liquid crystal display according to the exemplary embodiment of the present invention includes a generator 118 for generating an embedded source output enable (SOE) signal as shown in FIG. 6, and an SOE generator. A SOE pulse width variable unit 120 for varying a pulse width of a source output enable (SOE) signal output from 118, a GOE generation unit 158 for generating a gate output enable (GOE) signal, A GOE pulse width variable unit 130 for varying the pulse width of the gate output enable (GOE) signal from the GOE generation unit 158 is provided.

The SOE generator 118 generates a source output enable signal SOE having a maximum pulse width that can be applied to the liquid crystal panel 102 in one horizontal synchronization period by using the horizontal / vertical synchronization signals H and V. To the SOE pulse width variable part 120.

As illustrated in FIG. 7, the SOE pulse width variable part 120 outputs a source output enable (SOE) signal supplied from the SOE generator 118 in response to the first switching control signal Tout1. A first comparator for generating a first switching control signal Tout1 supplied to the first switch element SW1 using the first switch element SW1 outputted from the first switch element SW1 and the reference voltage REF and the triangular wave TP ( 140 and a first triangle wave generator 142 for supplying the triangle wave TP generated by generating the triangle wave TP to the first comparator 140.

The first triangular wave generator 142 generates a triangular wave of a right triangle shape and supplies it to the first comparator 140. At this time, the start point of the triangular wave (TP) is in the form of a right triangle that rises vertically at any time point and slopes down at the raised point in order to synchronize with the start point of the source output enable (SOE) signal.

The first comparator 140 is a Schmitt trigger, and the first input terminal is supplied with a reference voltage REF obtained by dividing the voltage Vcc supplied from an external voltage source by the resistor R and the variable resistor RB. The triangular wave TP from the first triangular wave generator 142 is supplied to the two input terminals. The first comparator 140 generates the first switching control signal Tout1 pulse-modulated according to the reference voltage REF and the triangular wave TP by using the pulse width modulation method to generate the first switch element SW1. To feed. At this time, the pulse width of the first switching control signal Tout1 is changed by the reference voltage REF. That is, the pulse width of the first switching control signal Tout1 varies depending on the voltage level of the reference voltage REF by the resistance value of the variable resistor RB. In detail, the first comparator 140 gradually increases the pulse width of the first switching control signal Tout1 as the voltage level of the reference voltage REF decreases due to the resistance of the variable resistor RB. As the voltage level of the reference voltage REF becomes higher due to the resistance of RB, the pulse width of the first switching control signal Tout1 is gradually decreased.

Meanwhile, the resistance value of the variable resistor RB depends on the resolution of the liquid crystal panel 102. That is, the resistance value of the variable resistor RB is determined by the liquid crystal cell Clc according to the application time of the analog video signal supplied to the liquid crystal cell Clc according to the structure of the liquid crystal panel 102 and the resolution of the liquid crystal panel 102. The charging characteristic is set to be optimized. Accordingly, the resistance value of the variable resistor RB is set to an optimized value according to the resolution change of the liquid crystal panel 102 of the user.

The first switch element SW1 receives a source output enable signal SOE signal supplied from the SOE generation unit 118 in response to the first switching control signal Tout1 supplied from the first comparator 140. 104). In other words, the first switch element SW1 outputs the source output enable signal SOE only when the first state of the first switching control signal Tout1 is HIGH. In this case, the on time of the first switch element SW1 may vary depending on the pulse width of the first switching control signal Tout1 supplied from the first comparator 140.

Accordingly, the SOE pulse width variable part 120 of the timing controller 108 according to the exemplary embodiment of the present invention may be configured according to the voltage level of the reference voltage REF that varies with the resistance values of the triangular wave TP and the variable resistor RB. By adjusting the on time of the first switch element SW1, the pulse width of the source output enable (SOE) signal as shown in FIG. 8 is any width between the minimum and maximum (SOEmax) (ST1, ST2, ST3) To be variable.

The GOE generation unit 158 generates a gate output enable signal having a maximum pulse width that can be applied to the liquid crystal panel 102 in one horizontal synchronization period by using the horizontal / vertical synchronization signals H and V. To the SOE pulse width variable part 120.

As illustrated in FIG. 9, the GOE pulse width variable unit 130 may output a gate output enable (GOE) signal supplied from the GOE generation unit 158 in response to the second switching control signal Tout2. A second comparator for generating a second switching control signal Tout2 supplied to the second switch element SW2 by using the second switch element SW2 and the reference voltage REF and the triangular wave TP. 190 and a second triangle wave generator 192 for supplying the triangle wave TP generated by generating the triangle wave TP to the second comparator 190.

The second triangular wave generator 192 generates a triangular wave TP having a right triangle shape and supplies it to the second comparator 190. At this time, the start point of the triangular wave TP is in the form of a right triangle that rises vertically at an arbitrary time point and slopes down at the raised point in order to synchronize with the start point of the gate output enable signal.

The second comparator 190 is a Schmitt trigger, and the first input terminal is supplied with a reference voltage REF in which a voltage Vcc supplied from an external voltage source is divided by a resistor R and a variable resistor RB. The triangular wave TP from the triangular wave generator 192 is supplied to the two input terminals. The second comparator 190 generates a second switching control signal Tout2 according to the reference voltage REF and the triangular wave TP by using a pulse width modulation method, and supplies it to the second switch element SW2. At this time, the pulse width of the second switching control signal Tout2 is changed by the reference voltage REF. That is, the pulse width of the second switching control signal Tout2 varies depending on the voltage level of the reference voltage REF by the resistance value of the variable resistor RB. In detail, the second comparator 190 gradually increases the pulse width of the second switching control signal Tout2 as the voltage level of the reference voltage REF decreases due to the resistance of the variable resistor RB. As the voltage level of the reference voltage REF becomes higher due to the resistance of RB, the pulse width of the second switching control signal Tout2 is gradually decreased.

Meanwhile, the resistance value of the variable resistor RB depends on the resolution of the liquid crystal panel 102. That is, the resistance value of the variable resistor RB may be optimized so that the charging characteristics of the liquid crystal cell Clc may be optimized according to the structure of the liquid crystal panel 102 and the resolution of the liquid crystal panel 102 according to the on time of the thin film transistor TFT. Is set. Accordingly, the resistance value of the variable resistor RB is set to an optimized value according to the resolution change of the liquid crystal panel 102 of the user.

The second switch element SW2 may output the gate output enable signal GOE supplied from the GOE generation unit 158 in response to the second switching control signal Tout2 supplied from the second comparator 190. ). In other words, the second switch element SW2 outputs the gate output enable signal GOE only when the second switching control signal Tout2 is in the high state HIGH. In this case, the on time of the second switch element SW2 may vary depending on the pulse width of the second switching control signal Tout2 supplied from the second comparator 190.

Accordingly, the GOE pulse width variable part 130 of the timing controller 108 according to an exemplary embodiment of the present invention may be configured according to the voltage level of the reference voltage REF that varies with the resistance values of the triangular wave TP and the variable resistor RB. By adjusting the on time of the second switch element SW2, as shown in FIG. 10, the pulse width of the gate output enable (GOE) signal can be any width between minimum and maximum (GOEmax) (GT1, GT2, GT3). To be variable.

In the liquid crystal display according to the exemplary embodiment of the present invention, the pulse width of each of the source output enable (SOE) signal and the gate output enable (GOE) signal is changed between the minimum width and the maximum width using the variable resistor RB. Can be varied to any width. Accordingly, in the liquid crystal display according to the exemplary embodiment, the pulse width of each of the source output enable (SOE) signal and the gate output enable (GOE) signal is determined by the charging characteristics of the liquid crystal cell Clc. The image quality can be improved by optimizing according to the structure and resolution.

As described above, the liquid crystal display according to the embodiment of the present invention generates a switching control signal by adjusting the resistance value of the external variable resistor by using a pulse width modulation method, and the on time of the switch element according to the switch control signal. The pulse width of the source output enable signal or the gate output enable signal having the maximum width is varied by adjusting the control function. Therefore, the present invention can improve the image quality by optimizing the pulse width of the source output enable signal or the gate output enable signal to the charging characteristics of the liquid crystal cell.

In addition, the present invention by varying the pulse width of the source output enable signal or the gate output enable signal in an analog manner by the resistance value of the variable resistor of the source output enable signal or gate output enable signal compared to the conventional digital method The pulse width variable range can be increased than in the prior art.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A liquid crystal panel; A data driver for supplying a video signal to the liquid crystal panel in response to a source output enable signal; A gate driver for supplying a scanning signal to the liquid crystal panel in response to a gate output enable signal; A timing controller including a source output enable signal generator for generating the source output enable signal and a gate output enable signal generator for generating the gate output enable signal; And A pulse width variable circuit including a source variable circuit for varying a pulse width of the source output enable signal, and a gate variable circuit for varying a pulse width of the gate output enable signal, The source variable circuit divides a voltage from an external source to generate a first voltage and a first variable resistor to generate a reference voltage, and a first triangle wave generator to generate a triangular wave in a right triangle shape. A first comparator for generating a switching control signal, and a first switch element for varying a width of the source output enable signal in response to the first switching control signal to switch to the data driver; Device. delete delete delete The method of claim 1, And the pulse width of the source output enable signal supplied to the first switch element is set to a maximum. The method of claim 1, And the first comparator changes a pulse width of the first switching control signal according to a voltage level of the reference voltage according to a change in the resistance value of the variable resistor using a pulse width modulation method. The method of claim 1, The gate variable circuit, A second resistor and a second variable resistor for dividing a voltage from the outside to generate a reference voltage; A second triangle wave generator for generating a triangle wave of a right triangle shape; A second comparator configured to generate a second switching control signal using the reference voltage and the triangle wave; And a second switch element for varying a pulse width of the gate output enable signal in response to the second switching control signal to switch to the gate driver. The method of claim 7, wherein And the pulse width of the gate output enable signal supplied to the second switch element is set to a maximum. The method of claim 7, wherein And the second comparator varies a pulse width of the second switching control signal according to a voltage level of the reference voltage according to a change in the resistance value of the variable resistor using a pulse width modulation method.

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