KR101213858B1 - Driving circuit and driving method - Google Patents

Abstract

Disclosed is a driving circuit capable of implementing both the 1-VGL function and the 2-VGL function.

The present invention generates multiple drive modes by the combination of at least one mode selection signal. One of these multiple drive modes can be selected. According to the selected driving mode, the first to third switches are switched to control the output of the VGL1 voltage, the VGL2 voltage, and the VGH voltage.

Accordingly, the present invention can support both the 1-VGL function and the 2VGL function by controlling the output of each voltage according to a plurality of driving modes.

In addition, the present invention is controlled to output the first VGL1 voltage or VGL2 voltage according to a plurality of driving modes, it is possible to measure the resistance of each switch when outputting each voltage, it is possible to accurately check the driving circuit The reliability of the product can be improved.

Drive circuit, gate, drive mode, switch

Description

Driving circuit and driving method {Driving circuit and driving method}

1 is a block diagram showing a conventional liquid crystal display device.

FIG. 2 is a block diagram illustrating in detail a transmission path of a power supply voltage shown in FIG. 1.

Figure 3a is a voltage output waveform diagram of a conventional 1-VGL method.

Figure 3b is a voltage output waveform diagram of a conventional 2-VGL method.

4 is a diagram illustrating a gate driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

5A is a voltage output waveform diagram in 1-VGL mode according to the present invention.

Figure 5b is a voltage output waveform diagram in the 2-VGL mode according to the present invention.

6 is a diagram illustrating a gate driving circuit of a liquid crystal display according to a second exemplary embodiment of the present invention.

7A through 7C are waveform diagrams of voltage outputs according to a plurality of driving modes.

<Explanation of symbols for the main parts of the drawings>

510, 520, and 530: first to third switches

540: control unit

The present invention relates to a gate driving circuit, and more particularly, to a driving circuit capable of implementing both a 1-VGL function supporting only a single gate low voltage (VGL) and a 2-VGL function supporting a double gate low voltage.

In general, the liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. The liquid crystal display device is implemented in an active matrix type in which switching elements are formed in each cell, and is applied to display devices such as computer monitors, office equipment, and cellular phones. As a switching element used in an active matrix liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used.

FIG. 1 is a schematic view of a conventional liquid crystal display, and FIG. 2 is a block diagram showing a transmission path of a power supply voltage shown in FIG. 1 in detail.

1 and 2, in the conventional LCD, m × n liquid crystal cells Clc are arranged in a matrix type, m data lines D1 to Dm, and n gate lines G1 to A liquid crystal panel 15 having Gn intersecting and a TFT formed at the intersection thereof, a data driving circuit 13 for supplying data to the data lines D1 to Dm of the liquid crystal panel 15, and gate lines. Timing for controlling the data driving circuit 13 and the gate driving circuit 14 by using the gate driving circuit 14 for supplying the scan signal to the G1 to Gn and the synchronization signal from the interface circuit 11. A controller 12 and a DC-DC converter (hereinafter referred to as a "DC-DC converter") 16 for generating voltages supplied to the liquid crystal panel 15 are provided.

The system 10 supplies a vertical / horizontal synchronization signal, a clock signal, and data (RGB) to the interface circuit 11 through a low voltage differential signaling (LVDS) transmitter of a graphic controller, and supplies a 3.3 V VCC voltage generated from a power supply. The power supply voltage is supplied to the digital circuit elements 11, 12, 13, 14 and the DC-DC converter 16.

In the liquid crystal panel 15, liquid crystal is injected between two glass substrates. The data lines D1 to Dm and the gate lines G1 to Gn formed on the lower glass substrate of the liquid crystal panel 15 are perpendicular to each other. The TFTs formed at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn display liquid crystal data on the data lines D1 to Dn in response to scan signals from the gate lines G1 to Gn. It is supplied to the cell Clc. To this end, the gate electrode of the TFT is connected to the corresponding gate line (G1 to Gn), and the source electrode is connected to the corresponding data line (D1 to Dm). The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. A black matrix, a color filter, and a common electrode (not shown) are formed on the upper glass substrate of the liquid crystal panel 15. On the upper glass substrate and the lower glass substrate of the liquid crystal panel 15, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment film for setting the pretilt angle of the liquid crystal is formed on the inner side of the liquid crystal panel 15 in contact with the liquid crystal. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc of the liquid crystal panel 15.

The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line (SOG) or between the pixel electrode of the liquid crystal cell Clc and the common electrode line (not shown) (SOC). : Storage On Common) to maintain a constant voltage of the liquid crystal cell (Clc).

The data driving circuit 13 converts the digital video data RGB into an analog gamma voltage corresponding to the gray scale value in response to the data control signal DDC from the timing controller 12 and converts the analog gamma voltage into the data lines D1 to Dm). The data drive integrated circuit in which the data drive circuit 13 is integrated is supplied with a VCC voltage of 3.3 V as a power supply voltage.

The gate driving circuit 14 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the gate control signal GDC from the timing controller 12 to supply horizontal data to the liquid crystal panel 15. Select a line. The gate drive integrated circuit in which the gate drive circuit 14 is integrated is supplied with a VCC voltage of 3.3 V as a power supply voltage.

The timing controller 12 controls a gate control signal (GDC) for controlling the gate driving circuit 14 by using a vertical / horizontal synchronization signal and a clock signal input from the graphic controller of the system 10 via the interface circuit 11. ) And a data control signal DDC for controlling the data driving circuit 13. The gate control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like. The data control signal (DDC) includes a source start pulse (SSP), a source shift clock (SSC), a source output signal (SOC), and a polarity signal (POL). do. The timing controller 12 rearranges the digital video data RGB inputted from the graphic controller of the system 10 via the interface circuit 11 and supplies the rearranged digital video data RGB to the data driving circuit 13. The power supply voltage for driving the timing controller 12 is a VCC voltage of 3.3 V input from the power supply of the system 10. In addition, the VCC voltage is supplied to a power supply voltage of a phase locked loop (PLL) installed in the timing controller 12. The phase locked loop PLL samples the digital video data RGB by comparing the clock signal input to the timing controller 12 with a reference frequency generated from an oscillator (not shown) and adjusting the frequency of the clock signal by the error. Generates a clock signal for

The interface circuit 11 includes a low voltage differential signaling (LVDS) receiver to reduce the voltage level and increase the frequency of signals input from the graphic controller of the system 10 to increase the frequency between the system 10 and the timing controller 12. This reduces the number of signal wires. The power supply voltage for driving this interface circuit 11 is a VCC voltage of 3.3 V input from the power supply of the system 10.

In order to reduce electromagnetic interference (hereinafter referred to as 'EMI') caused by the high frequency component and high voltage of the signal supplied from the interface circuit 11 to the timing controller 12, the timing with the interface circuit 11 is reduced. An EMI filter (not shown) is provided between the controllers 12.

The DC-DC converter 16 boosts or decompresses a VCC voltage of 3.3 V input from the power supply of the system 10 via a connector (not shown) to generate a voltage supplied to the liquid crystal panel 15. To this end, the DC-DC converter 16 outputs an output switch element for switching the output voltage to the output terminal, and a pulse width for boosting or depressing the output voltage by controlling the duty ratio or frequency of the control signal of the output switch element. It includes a modulator (Pulse Width Modulator (PWM)) or a Pulse Frequency Modulator (PFM). The pulse width modulator increases the output signal of the DC-DC converter 16 by increasing the control signal duty ratio of the output switch element, or lowers the output voltage of the DC-DC converter 16 by lowering the control signal duty ratio of the output switch element. . The pulse frequency modulator increases the output signal of the DC-DC converter 16 by raising the control signal frequency of the output switch element, or lowers the output voltage of the DC-DC converter 16 by lowering the frequency of the output switch element. The output voltage of the DC-DC converter 16 is a VDD voltage of 6V or more, a gamma reference voltage (GMA1-10) of less than 10 steps, a VCOM voltage of 2.5-3.3V, a VGH voltage of 15V or more, and a VGL voltage of -4V or less. The gamma reference voltage GMA1-10 is a voltage generated by the partial pressure of the VDD voltage. The VDD voltage and the gamma reference voltage are supplied to the data driving circuit 13 as analog gamma voltages. The VCOM voltage is a voltage supplied to the common electrode formed in the liquid crystal panel 15 via the data driving circuit 13. The VGH voltage is supplied to the gate driving circuit 14 as the high logic voltage of the scan pulse set above the threshold voltage of the TFT and the VGL voltage is supplied to the gate driving circuit 14 as the low logic voltage of the scan pulse set to the OFF voltage of the TFT. do.

The gate driving circuit 14 is a 1-VGL method for outputting only a single VGL voltage on the time axis as shown in FIG. 3A and a 2-VGL method for outputting dual VGL voltages, that is, VGL1 voltage and VGL2 voltage, on the time axis as shown in FIG. 3B. There is this.

The 1-VGL method is a general driving method applied to a gate driving circuit of a liquid crystal display panel having an SOC structure, but Greenish and Crosstalk in a LOG (Line On Glass) structure in which a gate printed circuit board is removed. There was a problem of deterioration of image quality due to the

The 2-VGL method is a driving method applied to a gate driving circuit for a liquid crystal display panel having an SOG structure.

Until now, according to the structure of the liquid crystal display panel, one of the 1-VGL gate driver IC and the 2-VGL gate driver IC has been cumbersome to use separately. In other words, there was no gate driving circuit capable of supporting both 1-VGL and 2-VGL.

An object of the present invention is to provide a gate driving circuit of a liquid crystal display device which supports both the 1-VGL function and the 2-VGL function.

According to a first embodiment of the present invention for achieving the above object, a drive circuit includes a first switch for switching a high level output; A second switch for switching a first low level output; A second switch for switching a second low level output; Means for generating a plurality of drive modes by the combination of the plurality of mode selection signals; And a controller configured to control switching of the first to third switches according to the driving modes.

According to a second embodiment of the present invention, a driving circuit includes: a first switch for switching an output of a gate high voltage; A second switch for switching the output of the first gate low voltage; A second switch for switching the output of the second gate low voltage; Means for generating a plurality of drive modes by the combination of the plurality of mode selection signals; And a controller configured to control switching of the first to third switches according to the driving modes.

According to a third embodiment of the present invention, a driving method includes: first to third switches for switching high level, first and second low level outputs, means for generating the plurality of driving modes and the first A driving circuit comprising a control unit for controlling switching of the third to third switches, the driving circuit comprising: setting one driving mode of the plurality of driving modes; And controlling the output of the high level, the first and second low levels according to the set driving mode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a gate driving circuit of the liquid crystal display according to the first exemplary embodiment of the present invention.

Referring to FIG. 4, the gate driving circuit of the present invention may include a first switch 410 connected between a first voltage supply terminal VGH and an output terminal Out for receiving a VGH voltage to regulate an output of the VGH voltage; A second switch 420 connected between a second voltage supply terminal VGL1 receiving the first VGL voltage and the output terminal Out to intermittently output the first VGL voltage, and a third receiving the second VGL voltage; A third switch 430 connected between the voltage supply terminal VGL2 and the output terminal Out to control the output of the second VGL voltage, and controls the intermittent operation of the first to third switches 410 to 430. It consists of a control unit 440.

The controller 440 controls the first to third switches 410 to 430 to operate in the 1-VGL mode or the 2-VGL mode according to a user's selection from the outside or a preset setting.

In order to set the 1-VGL mode and the 2-VGL mode, a mode selection signal S is supplied to the controller 440. The mode selection signal S may be selected to be either high or low. For example, when the mode selection signal S is high, the controller 440 controls the first to third switches 410-430 to be driven by the 1-VGL driving method, and the mode selection signal ( When S) is low, the controller 440 controls the first to third switches 410 to 430 to be driven by the 2-VGL driving method.

When the mode selection signal S is set to high and is driven in the 1-VGL mode, the controller 440 may have the VGL1 voltage in the first section I and the second section as shown in FIG. 5A. The first to third switches 410 to 430 are controlled to output the VGH voltage in (II) and the VGL1 voltage in the third section III through the output terminal Out.

When the mode selection signal S is set to low and driven in the 2-VGL mode, the controller 440 may have the VGL1 voltage in the first section I and the second section as shown in FIG. 5B. The first to third switches 410 to 430 are controlled to output the VGH voltage in (II) and the VGL2 voltage in the third section III through the output terminal Out.

The first to third switches 410 to 430 are formed of a thin film transistor.

The first switch 410 has a PMOS transistor having a gate connected to the controller 440, a source connected to the first voltage supply terminal VGH, and a drain connected to the output terminal Out.

The second switch 420 has an NMOS transistor having a gate connected to the controller 440, a source connected to the output terminal Out, and a drain connected to the second voltage supply terminal VGL1.

The third switch 430 has an NMOS transistor having a gate connected to the controller 440, a source connected to the output terminal Out, and a drain connected to the third voltage supply terminal VGL.

Referring to the gate driving circuit configured as described above, first, when the 1-VGL mode is selected by the mode selection signal S (S = high), the controller 440 performs the first section I on the time axis. The first and third switches 410 and 430 are turned off, and the second switch 420 is turned on to output the VGL1 voltage, and the second and second switches 410 and 430 are turned on. At the same time, the second and third switches 420 and 430 are turned off at the same time, and the first switch 410 is turned on to output the VGH voltage. The third switches 410-430 are operated in the same manner as in the first section so that the VGL1 voltage is output. As a result, in the gate driving circuit of the present invention, when the 1-VGL mode is selected, the VGL1 voltage is output before and after the VGH voltage in time.

Next, when the 2-VGL mode is selected by the mode selection signal S (S = low), the controller 440 performs the first and third switches 410, during the first period I on the time axis. 430 is turned off and the second switch 420 is turned on to output the VGL1 voltage, and the second and third switches 420 and 430 are simultaneously turned on during the second section II. In addition to turning OFF, the first switch 410 is turned ON to output the VGH voltage, and the first and second switches 410 and 420 are turned off during the third section III. OFF) and the third switch 430 is turned on to output the VGL2 voltage. As a result, in the gate driving circuit of the present invention, when the 2-VGL mode is selected, the VGL1 voltage and the VGL2 voltage are output before and after the VGH voltage.

As described above, the gate driving circuit of the liquid crystal display according to the first embodiment of the present invention outputs a 1-VGL driving method for outputting a single VGL by mode selection by a user or sequentially outputs two VGL1 and VGL2. Since the 2-VGL driving method can be supported, the utilization efficiency of the gate driving circuit can be improved and the application expandability can be increased.

Since the first to third switches 410 to 430 are semiconductor devices, device characteristics are sensitively changed by process conditions. In particular, the contact resistance generated when connecting metal wires to transistors is very sensitive to process conditions. The contact resistance may vary depending on the material of the device or the contact layout, and the resistance of the device may also change due to the change in the contact resistance.

Such a change in resistance of the device may not uniform the operating characteristics of the device can reduce the reliability of the device. Therefore, when the switches 410 to 430 are disposed as in the gate driving circuit of the present invention, the switches are tested to have an appropriate resistance, which is called a VGL Ron isolation test. By such a test, for example, the VGL1 voltage is output through the second switch 420, and the resistance of the second switch 420 is measured at this time to determine whether the resistance is within the predetermined range.

The gate driving circuit of the liquid crystal display according to the first embodiment of the present invention is output in the order of VGL1 voltage, VGH voltage, VGL1 voltage, or in the order of VGL1 voltage, VGH voltage, VGL2 voltage according to the mode selection signal setting. Can be output as

In this case, the resistance of the second switch 420 may be tested while the VGL1 voltage is output, and the resistance of the first switch 410 may be tested while the VGH voltage is output. However, since the VGL2 voltage is output after the VGH voltage, the resistance of the third switch 430 when the VGL2 voltage is output cannot be tested. That is, when the resistance of the third switch 430 is tested while the VGL2 voltage is output, the resistance of the third switch 430 cannot be accurately measured because the VGH previously outputted is affected.

As a result, in the gate driving circuit of the liquid crystal display according to the first embodiment of the present invention, there is a problem that the resistances of all the switches 410 to 430 cannot be tested.

In order to solve this problem, a second embodiment of the present invention has been presented.

6 is a diagram illustrating a gate driving circuit of a liquid crystal display according to a second exemplary embodiment of the present invention.

6 is basically similar to FIG. 5 described in the first embodiment of the present invention. However, in the first embodiment of the present invention, two driving modes (for example, 1-VGL and 2-VGL) are controlled by one mode selection signal S, whereas in the second embodiment of the present invention, Up to four driving schemes may be controlled by the two mode selection signals S1 and S2. That is, the controller 540 may control the driving unit 540 up to four driving methods according to the combination of the two mode selection signals S1 and S2. Therefore, for convenience of description, a function overlapping with that of the first embodiment of the present invention is omitted in the second embodiment of the present invention.

Two mode selection signals S1 and S2 are supplied to the control unit 540. The two mode selection signals S1 and S2 may be set by a user, and up to four modes may be selected by the combination of the mode selection signals S1 and S2. In the present invention, VGL1 + VGH + The first 1-VGL mode driven in the order of VGL1, the second 1-VGL mode driven in the order of VGL2 + VGH + VGL2, and the 2-VGL mode driven in the order of VGL1 + VGH + VGL2 are described. If necessary, a mode driven in the order of VGL2 + VGH + VGL1 may be added.

The controller 540 controls the gate output signal according to a combination of the two mode selection signals S1 and S2.

Three switches 510-530 are connected to the controller 540. The first switch 510 has a gate connected to the controller 540, a source connected to a first voltage supply terminal VGH, and a drain connected to an output terminal Out. The second switch 520 has a gate connected to the control unit 540, a source thereof connected to an output terminal Out, and a drain thereof to a second voltage supply terminal VGL1. The third switch 530 has a gate connected to the controller 540, a source connected to an output terminal Out, and a drain connected to a third voltage supply terminal VGL2.

The switches 510-530 are formed of a thin film transistor.

The two mode selection signals S1 and S2 may be configured in the following combination.

1) First 1-VGL mode (S1 = high, S2 = high)

2) second 1-VGL mode (S1 = low, S2 low)

3) 2-VGL mode (S1 = high, S2 low)

When driven in the first 1-VGL mode (S1 = high, S2 = high) as in 1), the controller 540 controls the first and third switches during the first period I on the time axis. 510 and 530 are turned off, and the second switch 520 is turned on to output the VGL1 voltage, and the second and third switches 520, At the same time, the 530 is simultaneously turned off and the first switch 510 is turned on to output the VGH voltage. The first to third switches 510- 530 is operated in the same manner as in the first section so that the VGL1 voltage is output. As a result, the gate driving circuit of the present invention outputs the VGL1 voltage before and after the VGH voltage in time when the first 1-VGL mode is selected.

When driven in the second 1-VGL mode (S1 = low, S2 low) as in 2), the control unit 540 performs the first and second switches 510 during the first period I on the time axis. , 520 is turned off, and the third switch 530 is turned on to output the VGL2 voltage, and the second and third switches 520 and 530 are continued during the second section II. ) And simultaneously turn off the first switch 510 to output the VGH voltage, and the first to third switches 510- 530 is operated in the same manner as in the first period so that the VGL2 voltage is output. As a result, in the gate driving circuit of the present invention, when the first 1-VGL mode is selected, the VGL2 voltage is output before and after the VGH voltage in time.

When driven in the 2-VGL mode (S1 = high, S2 low) as in 3), the controller 540 is configured to operate the first and third switches 510 and 530 during the first period I on the time axis. ) Is turned off and the second switch 520 is turned on to output the VGL1 voltage, and the second and third switches 520 and 530 are simultaneously turned off during the subsequent second section II. In addition, the first switch 510 is turned ON to output the VGH voltage, and the first and second switches 510 and 520 are turned off during the third section III. In addition, the third switch 530 is turned on to output the VGL2 voltage. As a result, in the gate driving circuit of the present invention, when the 2-VGL mode is selected, the VGL1 voltage and the VGL2 voltage are output before and after the VGH voltage.

As described above, in the gate driving circuit of the liquid crystal display according to the second embodiment of the present invention, up to four driving modes may be selected by a combination of two mode selection signals, and according to the selection of the four modes. The switching of the first to third switches 510 to 530 is controlled by the controller 540 to be driven in a desired driving mode.

In particular, the gate driving circuit of the liquid crystal display according to the second exemplary embodiment of the present invention enlarges the width of the selection mode and thus controls not only VGL1 but also VGL2 to be output in the first section, thereby switching each switch during the VGL Ron separation test. You can accurately measure the resistance of the (510-530). Accordingly, it is possible to easily determine whether the gate driving circuit is defective. As mentioned above, for the VGL Ron isolation test, not only the VGL1 voltage but also the VGL2 voltage must be output in time before the VGH voltage. In the first embodiment of the present invention, the VGL2 voltage is temporal than the VGH voltage due to the limitation of mode selection. Because it cannot be controlled to be output first, the VGL Ron isolation test could not be performed and the quality of the gate drive circuit could not be accurately checked.

On the contrary, in the second embodiment of the present invention, since the number of mode selections is increased by using two mode selection signals, not only the VGL1 voltage but also the VGL2 voltage can be controlled to be output in time before the VGH voltage. In addition, the VGL2 voltage can also make the VGL Ron isolation test accurate and easy. Accordingly, the reliability of the gate driving circuit can be increased.

As described above, according to the present invention, by supporting both the 1-VGL function and the 2-VGL function as a single unit, a desired function can be selected and used, regardless of the structure of the liquid crystal display panel (for example, SOC and SOG). Can be used.

In addition, according to the present invention, by controlling the number of mode selection cases by combining at least one mode selection signal so that not only the VGL1 voltage but also the VGL2 voltage is output in time before the VGH voltage, not only the VGL1 voltage but also the VGL2 voltage is also VGL. Ron separation test can be done accurately and easily.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (12)

A first switch for switching a high level output; A second switch for switching a first low level output; A third switch for switching a second low level output; A control unit connected to the first to third switches for switching control of the first to third switches according to a driving mode determined by a combination of a plurality of mode selection signals, The first to third switches include first to third thin film transistors each including a gate, a source, and a drain, Gates of the first to third thin film transistors are commonly connected to the control unit, and the gates of the first to third thin film transistors are controlled by switching control signals of the first to third thin film transistors, which are output at a time difference from the control unit according to a driving mode of the control unit. The first to third thin film transistors are individually switched controlled, A first gate voltage configured with the first low level, the high level, and the first low level, a second gate voltage configured with the second low level, the high level, and the second low level according to the driving mode; , A third gate voltage configured as the first low level, the high level, and the second low level, and a fourth gate voltage configured as the second low level, the high level, and the first low level. A drive circuit, characterized in that output. The driving circuit of claim 1, wherein the plurality of mode selection signals are configured in at least two. delete delete The method of claim 1, The second switch is turned on to output the first low level during the first period by the first driving mode, and the first switch is turned on to output the high level during the second period, and during the third period. And the second switch is turned on to output the first low level. The method of claim 1, The second switch is turned on to output the first low level during a first period by a second driving mode, the first switch is turned on to output the high level during a second period, and during the third period. The third switch is turned on to output the second low level. The method of claim 1, The third switch is turned on to output the second low level during the first period by the third driving mode, and the first switch is turned on to output the high level during the second period, and during the third period. The third switch is turned on to output the second low level. The method of claim 1, The third switch is turned on to output the second low level during the first period by the fourth driving mode, and the first switch is turned on to output the high level during the second period, and during the third period. And the second switch is turned on to output the first low level. The method of claim 1, And the thin film transistors of the liquid crystal cells of the liquid crystal display are turned on and off by the high level and the first and second low levels. 10. The method of claim 9, Wherein the high level is a gate high voltage and the first and second low levels are gate low voltages. delete The method of claim 1, The first to third switches are connected to an output terminal in common.

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