CN100416606C - 射频识别标签、模块组件及射频识别标签的制造方法 - Google Patents
射频识别标签、模块组件及射频识别标签的制造方法 Download PDFInfo
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Abstract
本发明提供了一种射频识别标签,包括:第一部件,该第一部件包含第一基体和利用混合有金属添加剂的树脂材料胶体在该第一基体上形成的通信天线;及,第二部件,该第二部件设置在该第一部件上,该第二部件包含第二基体、设置在该第二基体上与该第一部件上的天线电连接的金属片、和位于该金属片的上方并通过凸块与该金属片相连接的电路芯片,由此该凸块夹在该电路芯片与该金属片之间,该电路芯片通过该天线执行无线电通信。
Description
技术领域
本发明涉及一种与外部设备以非接触方式进行信息交换的RFID(射频识别)标签、用于制造该射频识别标签的电子元件及制造该射频识别标签的射频识别标签制造方法。应该指出的是,在本发明的技术领域内的技术人员中,本说明书中所使用的“射频识别标签”有时被称作“射频识别标签的嵌体(inlay)”,其指的是用于“射频识别标签”的内部组成构件(嵌体)。或者,该“射频识别标签”有时也被称为“无线IC标签”。该“射频识别标签”也包括非接触IC卡。
背景技术
近些年,已经提出了各式各样类型的射频识别标签,这些射频识别标签通过无线电波与以读取器/记录器为代表的外部设备以非接触方式进行信息交换。作为该射频识别标签的一种类型,已经提出了一种射频识别标签,该射频识别标签包含用于无线电通信的天线模式(antenna pattern)和在由塑料、纸张或其他类似物制成的基片上安装的IC芯片。已设计出这种类型射频识别标签的应用,其中,将射频识别标签连接到物品上,来与外部设备交换关于该物品的信息,从而识别该物品。
图1是显示射频识别标签的示例的主视图(A)和侧视图(B)。
参照图1,射频识别标签1包括天线12,该天线12设置在由片状PET薄膜或类似物制成的基体13上;IC芯片11,该IC芯片11通过凸块(bump)16连接到天线12上;和盖片14,用粘合剂15将盖片14连接到基体13上,以覆盖天线12和IC芯片11。
构成射频识别标签1的IC芯片11通过天线12能与外部设备进行无线电通信来交换信息。
对于该射频识别标签,已经设计出包括前述的一个应用在内的大范围应用。但是,在该射频识别标签的各式各样应用中,制造成本是主要问题之一。因此,已经做了各种尝试来降低其制造成本。
作为降低制造成本的一种尝试,已经开发出如下技术:即通过使用混合有金属添加剂(典型地,银)的诸如环氧树脂之类的树脂材料胶体,利用印刷技术来形成天线,以便该天线具有导电性(例如,参照日本特开平2000-311226(第[0066]段)、2000-200332(第[0027]段和第[0028]段)及2001-351082(第[0021]段))。传统地,作为制造天线的材料,可采用诸如铜、铝、金或类似的薄金属材料。如果使用形成天线的上述胶体材料,那么就能大幅度降低射频识别标签的制造成本。
图1是显示射频识别标签的示例的典型构造的俯视图(A)和侧视图(B)。在俯视图中,省略了一部分组成元件;在侧视图中,给出了从射频识别标签侧面观看的内部结构。在下文中,在本说明书中被称为俯视图和侧视图的所有示意图都与上述示意图相类似。
具有典型结构的射频识别标签1包括天线模式12,该天线模式12设置在由PET材料或其他类似物制成的基片13上;IC芯片11,该IC芯片11通过凸块16(金属凸起)连接到天线模式12上;和盖片14,用粘合剂15将盖片14连接到基片13上,以便覆盖天线模式12和IC芯片11。
在制造图1所示的射频识别标签1的过程中,IC芯片11通过形成在IC芯片11上的凸块16与形成在基片13表面上的天线模式12相连接。当由印刷胶体材料来形成天线模式12时,在进行连接的过程中可能产生下面的问题。
图2是解释在胶体用作天线材料时所产生的问题的概略示意图。
为了制造射频识别标签,首先,通过印刷技术将胶体材料制成的天线模式12形成在PET材料的基片13上((A)部分)。然后,将带有在电极111上形成的凸块16的IC芯片11设置在已在其上形成天线模式12的基片13上,同时凸块16被朝向基片13侧的方向定向((B)部分)。随后,当IC芯片11从图中的上方被夹具(未示出)挤压时,凸块16给天线模式12施加挤压力,由此将IC芯片11连接到天线模式12上。
此时,通过由凸块16给天线模式12施加的挤压力,使得在凸块16周围形成了构成天线模式12的胶体材料凸起12a。于是,就不能保证IC芯片11和天线模式12之间所要求的绝缘距离。所以,在制造多个射频识别标签时,由射频识别标签获得的诸如无线电通信性能之类的性能(下文中,称为“标签性能”)将改变,导致所看到的标签性能发生变化。
除了射频识别标签以外,一般惯例是将各种类型的IC芯片安装在电路板上。在这种情况下,由于在IC芯片上形成了多个凸块,即使胶体材料用作电路板上的布线材料,每个凸块的挤压力也是小的,所以胶体材料的凸起几乎不会造成任何问题。
相反,对于射频识别标签,用于将IC芯片连接到天线模式上的凸块数量大约为每IC芯片上2-4个,因此每个凸块的挤压力是相当大的,从而引起了如上所述的胶体材料凸起的问题。为了降低该挤压力,相对于将其上形成有多个凸块的普通IC芯片设置在基体上的情况而言,用于将IC芯片设置在基体上的设备所施加的挤压力必须被显著降低。然而,对于基体和IC芯片之间夹入粘合剂而言,难以实现快速、高可靠性连接并同时显著降低挤压力。
为了解决上述问题,本发明提供了一种射频识别标签、用于该射频识别标签的模块组件及制造该射频识别标签的制造方法,在该射频识别标签中,胶体用作天线材料,且同时避免了上述凸起所引起的标签性能变化的问题。
发明内容
鉴于上述情况作出了本发明,并提供一种射频识别标签、模块组件及射频识别标签的制造方法。
根据本发明的射频识别标签包括:第一部件,该第一部件包含第一基体和利用混合有金属添加剂的树脂材料胶体在该第一基体上形成的通信天线;及,第二部件,该第二部件设置在该第一部件上,该第二部件包含第二基体、设置在该第二基体上与第一部件上的天线电连接的金属片(metallic patch)和电路芯片,其位于该金属片的上方并通过凸块与该金属片相连接,由此该凸块夹在该电路芯片与该金属片之间,该电路芯片通过该天线执行无线电通信。
关于依据本发明的射频识别标签,该电路芯片连接到该第二部件的金属片上;该金属片电连接到胶体制成的该天线上。因此,通过两个步骤将该电路芯片连接到该天线上,这样该凸块朝向该金属片而不是朝向该天线挤压。因此,能避免上述胶体材料的凸起,由此也可避免该标签性能变化的问题。另外,因为该金属片设置在该第二部件内,所以在与制造该第一部件的过程相独立的过程中,通过单独制造该第二部件,能有效地执行刻蚀等过程,从而有助于降低成本。
关于依据本发明的射频识别标签,在该第二部件中,优选地,通过混合有金属添加剂的树脂材料胶体将该金属片连接到该第一部件的天线上。
将该金属片和该天线电连接的不同技术是可行的,所以可以容易地且低成本地制造通过与该天线本身相类似的胶体连接的结构。
依据本发明的模块组件,该模块组件构成射频识别,该模块组件被安装在天线组件上,该天线组件包含第一基体和利用混合有金属添加剂的树脂材料胶体在该第一基体上形成的通信天线。该模块组件包括第二基体、设置在该第二基体上与该天线组件上的天线电连接的金属片、和位于该金属片的上方并通过凸块与该金属片相连接电路芯片,由此该凸块夹在该电路芯片与该金属片之间,该电路芯片通过该天线执行无线电通信。
本发明的模块组件对应于本发明的射频识别标签的第二部件。在采用本发明的该模块组件时,随后甚至胶体被用作天线材料时,也可以避免胶体材料的上述凸起;从而也可避免该标签性能变化的问题。此外,在与上述该第一部件相对应的该天线组件的过程相独立的过程中,单独制造本发明的该模块组件,能有效地执行刻蚀等过程,从而有助于降低成本。
依据本发明的射频识别标签的制造方法,制造包括通信天线和通过天线执行无线电通信的电路芯片在内的射频识别标签。根据本发明的射频识别标签的制造方法包括步骤:利用混合有金属添加剂的树脂材料胶体,通过在第一基体上设置该天线,从而形成第一部件;将金属片设置在第二基体上,并且该电路芯片位于该金属片的上方并通过凸块将该电路芯片连接到该金属片上由此该凸块夹在该电路芯片与该金属片之间,从而形成第二部件;将该第二部件设置在该第一部件上,使得该第二部件上的金属片与该第一部件的天线电连接。
采用本发明的该射频识别标签的制造方法,能避免胶体材料的上述凸起,从而也可避免该标签性能变化的问题。另外,采用该射频识别标签的制造方法,在与设置有金属片的该第二部件的过程相独立的过程中,形成设置有胶体制成的该天线的第一部件。因此,能高效率地形成每一该第一部件及该第二部件,从而有助于降低射频识别标签的成本。
在依据本发明的射频识别标签的制造方法的形成该第二部件上述步骤中,优选通过如下方式形成该第二部件:将多个金属片置于基体材料上,该基体材料具有与多个该第二部件相对应的宽度,所述电路芯片位于所述多个金属片的上方并通过多个凸块将多个电路芯片相应地连接到所述多个金属片上由此所述凸块夹在所述电路芯片与所述金属片之间,随后将该基体材料切割成多个第二基体。
采用包含形成该第二部件的这个步骤在内的该射频识别标签的制造方法,可高效率地形成该第二部件,从而有助于进一步降低射频识别标签的成本。
如上所述,采用本发明,同时胶体用作该天线材料,可以避免由胶体材料凸起所引起的标签性能变化的问题。
附图说明
根据下列附图,将详细说明本发明的优选实施例,其中:
图1是显示射频识别标签的示例的典型构造的主视图(A)和侧视图(B);
图2是解释在胶体用作天线材料时所产生的问题的概略示意图;
图3是显示本发明的实施例的侧视图(A)和俯视图(B);
图4是说明形成带有凸块的IC芯片的步骤的视图;
图5的说明形成金属片的步骤的视图,从上方观察每个步骤;
图6是说明形成金属片的步骤的视图,从侧面观察每个步骤;
图7是说明将IC芯片安装到金属片上的步骤的视图;
图8是显示切割第二部件的过程的视图;
图9是说明形成第一部件并组装射频识别标签的步骤的视图;
图10是显示与印刷天线模式相关的细节的视图;
图11是显示与安装该模块组件有关的细节的视图。
具体实施方式
下面参考附图说明本发明的实施例。
图3是显示本发明实施例的侧视图(A)和俯视图(B)。
依据本实施例所述的射频识别标签10的基本结构与图1所示示例的典型结构类似,仅是IC芯片的外围结构与示例性结构不同。因此,图3仅显示IC芯片的外围结构。同时,下面的说明将重点放在IC芯片的外围结构上。
本实施例的射频识别标签10包括第一部件和第二部件。第一部件具有PET材料的基片13和用胶体形成的天线模式12;第二部件具有PET材料的子基片17、金属片18及通过设置在电极111上的凸块16连接到金属片18上的IC芯片11。
在此,构成射频识别标签10的第一部件及第二部件分别与依据本发明的第一部件(天线组件)及第二部件(模块组件)的示例相对应。基片13、天线模式12、子基片17、金属片18和IC芯片11分别与本发明的第一基体、天线、第二基体、金属片和电路芯片的示例相对应。
对于本实施例,利用混合有银添加剂的诸如环氧树脂之类的树脂材料胶体,来形成天线模式12。金属片18由铜薄膜构成。第一部件的天线模式12和第二部件的金属片18通过导线19相互电连接,该导线19由类似于构成天线模式12的胶体制成。
下面说明该射频识别标签的制造步骤。
在射频识别标签10的制造过程中,首先形成带有凸块16的IC芯片11。
图4是说明形成带有凸块的IC芯片的步骤的视图。
首先,如步骤(A)所示,从带有窗口(window)的夹具20的末端伸出将要制成凸块的细金属线30,并在该细金属线30和放电电极40之间发生放电。结果,如步骤(B)所示,放电能量将该细金属线30的末端熔化,形成金属球31。
如步骤(C)所示,准备已在其内形成电极111的IC芯片11。随后,如步骤(D)所示,在朝向IC芯片11的电极111挤压金属球31的同时,超声波通过夹具20施加到金属球31上。结果,通过超声波将金属球31连接到IC芯片11的电极111上。一旦去除夹具20,金属球31就与细金属导线30的端部分离,从而在IC芯片11的电极111上就形成了凸块的基础模式,如步骤(E)所示。
以这样的方式在电极111上形成凸块的基础模式之后,执行步骤(F)所示的压平过程。在该步骤中,朝向玻璃50的平面挤压凸块的基础模式。结果,如步骤(G)所示,在IC芯片11的电极111上形成具有统一高度的凸块16。
一旦以这样的方式形成了带有凸块16的IC芯片11,制造过程就将进行第二部件的金属片的形成过程。
图5和图6是说明形成金属片的步骤的视图,在图5中从上方观察每个步骤;在图6中从侧面观察每个步骤。
在形成金属片的过程中,首先,如步骤(A)所示,准备PET材料,该PET材料要被加工成第二部件的子基片。接着,如步骤(B)所示,将铜薄膜61连接到PET片60的整个表面上。然后,如图5和图6的步骤(C)所示,在铜薄膜61上形成抗蚀剂62,该抗蚀剂62具有与该金属片相同的位置和形状,并且,如步骤(D)所示,通过刻蚀过程将铜薄膜61不需要的部分去掉,来形成金属片18。然后,如步骤(E)所示,去掉抗蚀剂62,从而形成在其上适当的位置设置有金属片18的PET材料60。
这样,能够以成组的方式在PET材料60上形成与一组子基片相对应的金属片18,通过一次刻蚀过程可以有效地形成多个金属片。由于本实施例的射频识别标签由第一部件和第二部件构成,第二部件的形成过程可以独立于第二部件的形成过程,因此这是可行的。
在射频识别标签的制造步骤中,在形成第二部件的金属片之后,将IC芯片安装在金属片上。
图7是说明将IC芯片安装到金属片上的步骤的视图。
在安装IC芯片的过程中,首先,如步骤(A)所示,将其上以预定位置设置金属片18的PET材料60放在工作台70上,并且在金属片18之间涂上粘合剂71。然后,如步骤(B)所示,利用安装头72将带有凸块16的IC芯片11相对于金属片18正确定位,并且,如步骤(C)所示,朝向PET材料60挤压IC芯片11,从而将凸块16连接到金属片18上。在此情况下,金属片18具有足够的强度来承受来自凸块16的压力,从而可以确保IC芯片11和PET材料60之间有着足够的绝缘距离。另外,通过工作台70加热粘合剂71使其硬化。因此,如步骤(D)所示,IC芯片11通过粘合剂71牢固地固定在PET材料60上,从而获得对应于射频识别标签的第二部件的结构。也可使PET材料60穿过高温环境来完成粘合剂71的加热和硬化。
在步骤(D)阶段,PET材料60与彼此连接的多个第二部件相对应。最后,通过切割PET材料60形成单个第二部件。
图8是显示切割第二部件的过程的视图。
如步骤(A)所示,在PET材料60上牢固地连接着多个IC芯片11,一个IC芯片11和两个金属片18的组合对应于射频识别标签的一个第二部件。如步骤(B)所示,将PET材料60切割成子基片17,使每个子基片17含有一个IC芯片11,从而第二部件形成为模块组件65。
图5至图8中所示的形成模块组件65的步骤对应于在依据本发明的射频识别标签的制造方法中形成第二部件的步骤的示例,模块组件65与依据本发明的模块组件的实施例相对应。
在形成模块组件65之后,在射频识别标签的制造步骤中执行第一部件的形成和该射频识别标签的组装。
图9是说明形成第一部件并组装射频识别标签的步骤的视图。
在形成第一部件的过程中,首先,如步骤(A)所示,准备PET材料75,该PET材料75将被加工成该射频识别标签的第一部件的基片;接着,如图(B)所示,PET材料75上印刷并形成天线模式12。该步骤(B)对应于依据本发明的射频识别标签的制造方法中形成第二部件的步骤的示例。
图10是显示与印刷天线模式相关的细节的视图。
在印刷该天线模式的过程中,如步骤(A)所示,将带有孔的印刷母版(printing master)80设置在PET材料75上,该孔位于与天线模式12相对应的部分,并且,用橡皮刮板81印刷胶体83,使得胶体83填充印刷母版80的孔。
随后,如步骤(B)所示,去除印刷母版80并脱水和干燥其他部分,从而在PET材料75上形成天线模式12。
在图9的步骤(B)中形成天线模式12之后,如步骤(C)所示,将模块组件65安装在PET材料75上。该步骤(C)对应于在依据本发明的射频识别标签的制造方法中将第二部件设置在第一部件上使第二部件上的金属片与第一部件上的天线电连接的步骤的示例。
图11是显示与安装该模块组件有关的细节的视图。
在安装该模块组件的过程中,如步骤(A)所示,将粘合剂84涂到其上形成有天线模式12的PET材料75上的安装位置,接着,如步骤(B)所示,将模块组件65定位;随后,如步骤(C)所示,将模块组件65安装在天线模式12上,并且从下方加热粘合剂84使其硬化。结果,将模块组件65牢固地连接在PET材料75上。然后,如步骤(D)所示,在模块组件65上的金属片18和PET材料75上的天线模式12之间利用胶体材料印刷导线19,从而使金属片18与天线模式12电连接。
在以这样的方式图9的步骤(C)中安装模块65之后,涂上盖片并与整个PET材料75相连接(未示出);然后,如步骤(D)所示,通过切割PET材料75形成基片13,从而完成射频识别标签的制造。
在上述说明中,由银胶体制成的该天线模式作为依据本发明的天线的示例。但是,依据本发明的天线可以由混合有除银以外的金属添加剂的胶体制成。
此外,在上述说明中,由铜薄膜制成的该金属片作为依据本发明的金属片的示例。但是,依据本发明的金属片可以由铝、金或类似物制成。
此外,在上述说明中,由PET材料制成的基片作为依据本发明的第一基体和第二基体的示例。但是,依据本发明的第一基体和第二基体可以由除PET以外的材料制成。
Claims (5)
1. 一种射频识别标签,包括:
第一部件,该第一部件包含第一基体和利用混合有金属添加剂的树脂材料胶体在该第一基体上形成的通信天线;及
第二部件,该第二部件设置在该第一部件上,该第二部件包含:第二基体;设置在该第二基体上与该第一部件上的天线电连接的金属片;和电路芯片,其位于该金属片的上方,并通过凸块与该金属片相连接由此该凸块夹在该电路芯片与该金属片之间,该电路芯片通过该天线执行无线电通信。
2. 如权利要求1所述的射频识别标签,其中,在该第二部件中,通过混合有金属添加剂的树脂材料胶体,将该金属片连接到该第一部件的天线上。
3. 一种模块组件,该模块组件构成射频识别,该模块组件安装在天线组件上,该天线组件包含第一基体和利用混合有金属添加剂的树脂材料胶体在该第一基体上形成的通信天线,该模块组件包括:
第二基体;
金属片,该金属片设置在该第二基体上,以与该天线组件上的天线电连接;及
电路芯片,该电路芯片位于该金属片的上方,并通过凸块连接到该金属片上由此该凸块夹在该电路芯片与该金属片之间,该电路芯片通过该天线执行无线电通信。
4. 一种射频识别标签的制造方法,该射频识别标签的制造方法制造包括通信天线和通过该天线执行无线电通信的电路芯片的射频识别标签,该射频识别标签的制造方法包括如下步骤:
利用混合有金属添加剂的树脂材料胶体,通过在该第一基体上设置该天线,从而形成第一部件;
将金属片设置在第二基体上,并且该电路芯片位于该金属片的上方并通过凸块将该电路芯片连接到该金属片上由此该凸块夹在该电路芯片与该金属片之间,从而形成第二部件;及
将该第二部件设置在该第一部件上,使得该第二部件上的金属片与该第一部件的天线电连接。
5. 如权利要求4所述的射频识别标签的制造方法,其中,在形成该第二部件步骤中,将多个金属片置于基体材料上,该基体材料具有与多个该第二部件相对应的宽度;所述电路芯片位于所述多个金属片的上方,并通过多个凸块将多个电路芯片相应地连接到所述多个金属片上由此所述凸块夹在所述电路芯片与所述金属片之间;随后将该基体材料切割成多个该第二基体,从而形成多个第二部件。
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JP2005077108A JP2006260205A (ja) | 2005-03-17 | 2005-03-17 | Rfidタグ、モジュール部品、およびrfidタグ製造方法 |
JP2005077108 | 2005-03-17 |
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US (1) | US7431218B2 (zh) |
EP (1) | EP1703448A3 (zh) |
JP (1) | JP2006260205A (zh) |
KR (1) | KR100746115B1 (zh) |
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JP4768379B2 (ja) * | 2005-09-28 | 2011-09-07 | 富士通株式会社 | Rfidタグ |
US20070131781A1 (en) * | 2005-12-08 | 2007-06-14 | Ncr Corporation | Radio frequency device |
JP2008177351A (ja) | 2007-01-18 | 2008-07-31 | Fujitsu Ltd | 電子装置および電子装置の製造方法 |
US7948384B1 (en) | 2007-08-14 | 2011-05-24 | Mpt, Inc. | Placard having embedded RFID device for tracking objects |
PT2244211E (pt) * | 2008-01-18 | 2015-01-13 | Beijing Golden Spring Internet Of Things Inc | Método de fabrico de um dispositivo de identificação por frequência de rádio |
EP2416355B1 (en) | 2009-04-02 | 2016-12-21 | Murata Manufacturing Co., Ltd. | Circuit board |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1185859A (zh) * | 1995-05-22 | 1998-06-24 | 日立化成工业株式会社 | 具有与布线基板电连接的半导体芯片的半导体器件 |
JP2000311226A (ja) * | 1998-07-28 | 2000-11-07 | Toshiba Corp | 無線icカード及びその製造方法並びに無線icカード読取り書込みシステム |
US6271793B1 (en) * | 1999-11-05 | 2001-08-07 | International Business Machines Corporation | Radio frequency (RF) transponder (Tag) with composite antenna |
US20020115278A1 (en) * | 1999-11-24 | 2002-08-22 | Wakahiro Kawai | Method of mounting a semiconductor chip, circuit board for flip-chip connection and method of manufacturing the same, electromagnetic wave readable data carrier and method of manufacturing the same, and electronic component module for an electromagnetic wave readable data carrier |
US20040212544A1 (en) * | 1999-03-24 | 2004-10-28 | Pennaz Thomas J. | Circuit chip connector and method of connecting a circuit chip |
US6816380B2 (en) * | 2001-05-31 | 2004-11-09 | Alien Technology Corporation | Electronic devices with small functional elements supported on a carrier |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11250214A (ja) * | 1998-03-03 | 1999-09-17 | Matsushita Electron Corp | 部品の実装方法とicカード及びその製造方法 |
JP3502557B2 (ja) * | 1999-01-07 | 2004-03-02 | 松下電器産業株式会社 | 非接触icカードの製造方法 |
JP2000227953A (ja) * | 1999-02-05 | 2000-08-15 | Matsushita Electronics Industry Corp | Icカードとその製造方法 |
EP1039543B1 (en) | 1999-03-24 | 2014-02-26 | Motorola Solutions, Inc. | Circuit chip connector and method of connecting a circuit chip |
JP4620836B2 (ja) * | 2000-06-08 | 2011-01-26 | 大日本印刷株式会社 | ウエハーの製造方法 |
JP2002259923A (ja) * | 2001-03-05 | 2002-09-13 | Tokyo Magnetic Printing Co Ltd | 非接触icカードおよびその製造方法 |
JP2004185229A (ja) * | 2002-12-02 | 2004-07-02 | Sharp Corp | 非接触型icカード及びその製造方法 |
WO2004075337A1 (ja) * | 2003-02-24 | 2004-09-02 | Nec Corporation | 誘電体共振器及び誘電体共振器の周波数調整方法並びに誘電体共振器を有する集積回路 |
-
2005
- 2005-03-17 JP JP2005077108A patent/JP2006260205A/ja active Pending
- 2005-07-14 TW TW094123894A patent/TWI308296B/zh not_active IP Right Cessation
- 2005-07-21 EP EP05254559A patent/EP1703448A3/en not_active Withdrawn
- 2005-07-25 US US11/188,346 patent/US7431218B2/en not_active Expired - Fee Related
- 2005-08-10 KR KR1020050073323A patent/KR100746115B1/ko not_active IP Right Cessation
- 2005-08-11 CN CNB200510091423XA patent/CN100416606C/zh not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1185859A (zh) * | 1995-05-22 | 1998-06-24 | 日立化成工业株式会社 | 具有与布线基板电连接的半导体芯片的半导体器件 |
JP2000311226A (ja) * | 1998-07-28 | 2000-11-07 | Toshiba Corp | 無線icカード及びその製造方法並びに無線icカード読取り書込みシステム |
US20040212544A1 (en) * | 1999-03-24 | 2004-10-28 | Pennaz Thomas J. | Circuit chip connector and method of connecting a circuit chip |
US6271793B1 (en) * | 1999-11-05 | 2001-08-07 | International Business Machines Corporation | Radio frequency (RF) transponder (Tag) with composite antenna |
US20020115278A1 (en) * | 1999-11-24 | 2002-08-22 | Wakahiro Kawai | Method of mounting a semiconductor chip, circuit board for flip-chip connection and method of manufacturing the same, electromagnetic wave readable data carrier and method of manufacturing the same, and electronic component module for an electromagnetic wave readable data carrier |
US6816380B2 (en) * | 2001-05-31 | 2004-11-09 | Alien Technology Corporation | Electronic devices with small functional elements supported on a carrier |
Also Published As
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CN1835001A (zh) | 2006-09-20 |
EP1703448A2 (en) | 2006-09-20 |
KR20060101382A (ko) | 2006-09-22 |
TWI308296B (en) | 2009-04-01 |
KR100746115B1 (ko) | 2007-08-06 |
TW200634646A (en) | 2006-10-01 |
US20060208094A1 (en) | 2006-09-21 |
JP2006260205A (ja) | 2006-09-28 |
US7431218B2 (en) | 2008-10-07 |
EP1703448A3 (en) | 2010-07-28 |
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