CN100373500C - 以连续脉冲模式存取数据的与位置无关的半导体存储器件 - Google Patents

以连续脉冲模式存取数据的与位置无关的半导体存储器件 Download PDF

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Publication number
CN100373500C
CN100373500C CNB2004100374538A CN200410037453A CN100373500C CN 100373500 C CN100373500 C CN 100373500C CN B2004100374538 A CNB2004100374538 A CN B2004100374538A CN 200410037453 A CN200410037453 A CN 200410037453A CN 100373500 C CN100373500 C CN 100373500C
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CN
China
Prior art keywords
data
word line
row address
bank
memory bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CNB2004100374538A
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English (en)
Chinese (zh)
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CN1577613A (zh
Inventor
安进弘
洪祥熏
高在范
金世埈
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SK Hynix Inc
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Hynix Semiconductor Inc
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Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN1577613A publication Critical patent/CN1577613A/zh
Application granted granted Critical
Publication of CN100373500C publication Critical patent/CN100373500C/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
CNB2004100374538A 2003-06-30 2004-04-29 以连续脉冲模式存取数据的与位置无关的半导体存储器件 Expired - Fee Related CN100373500C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030043422A KR100540483B1 (ko) 2003-06-30 2003-06-30 데이터 억세스 위치에 관계없이 연속적인 버스트 모드로 데이터를 억세스할 수 있는 반도체 메모리 장치 및 그의 구동방법
KR1020030043422 2003-06-30

Publications (2)

Publication Number Publication Date
CN1577613A CN1577613A (zh) 2005-02-09
CN100373500C true CN100373500C (zh) 2008-03-05

Family

ID=33536390

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CNB2004100374538A Expired - Fee Related CN100373500C (zh) 2003-06-30 2004-04-29 以连续脉冲模式存取数据的与位置无关的半导体存储器件

Country Status (4)

Country Link
US (1) US6930951B2 (ko)
KR (1) KR100540483B1 (ko)
CN (1) CN100373500C (ko)
TW (1) TWI288413B (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100935602B1 (ko) * 2008-06-24 2010-01-07 주식회사 하이닉스반도체 클럭 드라이버 및 이를 포함하는 반도체 메모리 장치
US8564603B2 (en) * 2010-10-24 2013-10-22 Himax Technologies Limited Apparatus for controlling memory device and related method
US9053776B2 (en) * 2012-11-08 2015-06-09 SK Hynix Inc. Setting information storage circuit and integrated circuit chip including the same
KR20140082173A (ko) * 2012-12-24 2014-07-02 에스케이하이닉스 주식회사 어드레스 카운팅 회로 및 이를 이용한 반도체 장치
KR20140132103A (ko) * 2013-05-07 2014-11-17 에스케이하이닉스 주식회사 메모리 시스템, 반도체 메모리 장치 및 그것들의 동작 방법
JP7235389B2 (ja) * 2019-03-29 2023-03-08 ラピスセミコンダクタ株式会社 半導体記憶装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729504A (en) * 1995-12-14 1998-03-17 Micron Technology, Inc. Continuous burst edo memory device
US20010021136A1 (en) * 2000-02-24 2001-09-13 Bae Yong Cheol Auto precharge control signal generating circuits for semiconductor memory devices and auto precharge control methods
US20020110037A1 (en) * 2001-02-15 2002-08-15 Hiroyuki Fukuyama Dram interface circuit providing continuous access across row boundaries
US6545932B1 (en) * 1998-12-25 2003-04-08 International Business Machines Corporation SDRAM and method for data accesses of SDRAM

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3039585B2 (ja) 1992-09-11 2000-05-08 日本電信電話株式会社 同期語検出回路
US5838661A (en) 1996-03-27 1998-11-17 Cirrus Logic, Inc. Method and arrangement for shutting off a receive channel in a data communications system
US6401186B1 (en) 1996-07-03 2002-06-04 Micron Technology, Inc. Continuous burst memory which anticipates a next requested start address
JPH10124447A (ja) 1996-10-18 1998-05-15 Fujitsu Ltd データ転送制御方法及び装置
KR100283470B1 (ko) 1998-12-09 2001-03-02 윤종용 반도체 메모리 장치의 어드레스 발생회로
CN100570577C (zh) 2001-08-29 2009-12-16 联发科技股份有限公司 高速程序跟踪

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729504A (en) * 1995-12-14 1998-03-17 Micron Technology, Inc. Continuous burst edo memory device
US5946265A (en) * 1995-12-14 1999-08-31 Micron Technology, Inc. Continuous burst EDO memory device
US6545932B1 (en) * 1998-12-25 2003-04-08 International Business Machines Corporation SDRAM and method for data accesses of SDRAM
US20010021136A1 (en) * 2000-02-24 2001-09-13 Bae Yong Cheol Auto precharge control signal generating circuits for semiconductor memory devices and auto precharge control methods
US20020110037A1 (en) * 2001-02-15 2002-08-15 Hiroyuki Fukuyama Dram interface circuit providing continuous access across row boundaries

Also Published As

Publication number Publication date
KR20050002107A (ko) 2005-01-07
US20040264278A1 (en) 2004-12-30
CN1577613A (zh) 2005-02-09
KR100540483B1 (ko) 2006-01-11
US6930951B2 (en) 2005-08-16
TW200501163A (en) 2005-01-01
TWI288413B (en) 2007-10-11

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Granted publication date: 20080305

Termination date: 20130429