CN100364066C - 用于快闪存储晶单元的ono内复晶介电质及制作方法 - Google Patents

用于快闪存储晶单元的ono内复晶介电质及制作方法 Download PDF

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CN100364066C
CN100364066C CNB02155532XA CN02155532A CN100364066C CN 100364066 C CN100364066 C CN 100364066C CN B02155532X A CNB02155532X A CN B02155532XA CN 02155532 A CN02155532 A CN 02155532A CN 100364066 C CN100364066 C CN 100364066C
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谢荣裕
韩宗廷
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Abstract

一种半导体元件的制造方法，包括提供一个晶圆基底，在晶圆基底上形成一层第一氧化硅层；利用低温沉积制作工艺在第一氧化硅层上沉积一层氮化物层；以及在氮化物层上形成一层第二氧化硅层。低温制作工艺可以在约为摄氏700度的温度下形成一层氮化物层，作为氧化物-氮化物-氧化物(ONO)介电质结构的一部份，透过这样的制作工艺，ONO介电质结构可以用低温沉积制作工艺来制作，这可以降低ONO介电质结构的厚度。

Description

用于快闪存储晶单元的ONO内复晶介电质及制作方法
技术领域
本发明是有关于一种半导体元件以及其制作方法，且特别是有关于一种用于快闪存储晶单元的ONO内复晶(interpoly)介电质以及使用一单晶圆低温沉积制作工艺来制作此介电质的方法。
背景技术
半导体元件有一种型态为闪存元件，包括一个浮栅电极可以储存电荷，电荷会由浮栅电极下方的一个信道区域提供，此浮栅一般包括一层可以储存电荷的介电材料，一般用来作为浮栅的介电质结构为一种氧化物-氮化物-氧化物(ONO)的结构。
这类的结构对闪存的操作特性与可靠度扮演了很重要的角色，一个高品质的ONO介电质结构应该可以提供例如低缺陷密度、失效之前的平均时间长、以及高电荷维持能力。
一种制作ONO介电质的方法是使用一种单晶圆热制作工艺，公知的方法需要用约为摄氏800度的高温来沉积这个介电薄膜，因为温度很高这个制作工艺会有一些缺点，比如高温制作工艺会导致介电材料表面不平整、介电质崩溃的时间(TDDB)短、以及低的优良率等。
因此，现在需要的是用低温的制作工艺来沉积ONO介电材料，并减少ONO介电材料表面的不平整。
发明内容
有鉴于此，本发明提供一种半导体元件的制造方法，包括提供一个晶圆基底，在晶圆基底上形成一层第一氧化硅层；利用低温沉积制作工艺以及在约为275Torr的一压力下在第一氧化硅层上沉积一层氮化物层；以及在氮化物层上形成一层第二氧化硅层。在一方面，第一氧化硅层形成于浮栅复晶(poly)上。
本发明的另外目的与优点将在下方做进一步详细的叙述，熟悉此技术者也可以透过本发明公开的技术轻易的达到本发明的目的。
为让本发明的上述目的、特征、和优点能更明显易懂，下文特举一较佳实施例，并配合所附图式，作详细说明。
附图说明
图1与图2绘示为半导体元件的制作流程图；
图3图为显示在摄氏800度与700度下的ONO介电质材料不平坦的程度的一图表；
图4为显示在摄氏800度与700度下的ONO介电质材料累积的失败率的图表；
图5为显示在摄氏800度与700度下的ONO介电质材料的优良率百分比的图表。
标号说明
100基底              120隧穿层
130多晶硅层(浮栅)    140堆栈介电质薄膜
140-1第一氧化物层    140-2氮化物层
140-3第二氧化物层    150控制栅
160金属硅化物层      170间隙壁
180盖层    190扩散区
具体实施方式
以下将配合图标详细说明本发明，其中在不同的图中会使用相同的参考号码还表示相同或相近的元件。
图1与图2绘示为半导体元件的制作流程图。请参照图1，提供一个晶圆基底100用以制作主动元件，在基底100上形成一层隧穿氧化层120，在隧穿氧化层120上形成一层多晶硅层130，此多晶硅层130可以作为一个浮栅130。
接着，在浮栅130上形成一层堆栈介电质薄膜或是材料140，此介电质薄膜140包括一层第一氧化物层140-1、一层氮化物层140-2、以及一层第二氧化物层140-3，此结构可以表示为氧化物-氮化物-氧化物(ONO)介电质结构。在一实施例中，沉积在浮栅130上的第一氧化物层140-1是用一种公知的低压化学气相沉积法(LPCVD)，在约为200Torr的压力下，透过比如让硅烷(SiH4)与氧化氮(N2O)反应来进行。
在第一氧化物层140-1上的氮化物层140-2以低温沉积制作工艺来形成，其中硅烷(SiH4)与氨(NH3)会被导入作为反应气体。在一实施例中，沉积氮化物层140-2的沉积制作工艺会在约为摄氏700度的温度下进行，而其压力约为275Torr。接着，用一个公知的LPCVD制作工艺，在氮化物层140-2上形成或沉积一层第二氧化物层140-3。在一个实施例中，第一氧化物层140-1的厚度约为43埃，氮化物层140-2的厚度约为62埃，而第二氧化物层140-3的厚度约为59埃。
请参照图2，可以用公知的半导体制作工艺来形成一层控制栅150，覆盖在ONO介电质薄膜140的第二氧化物层140-3上，在控制栅150上形成一层金属硅化物层160，在栅极150的垂直侧壁附近会形成间隙壁170，而在金属硅化物层160上会有一层盖层180形成；最后会在基底100内形成扩散区190，用以作为源极与漏极区。
低温沉积制作工艺的结果会使ONO薄膜140在薄膜早期成长阶段具有较高的成核密度，相较于公知高温沉积制作工艺，氮化物层140-2可因此呈现一个较平滑的表面。举例来说，可以明显的察觉在约为摄氏800度的高温下形成的氮化硅层的表面比在摄氏700度下形成的氮化硅层的表面更不平坦，如图3的图表所示。
请参照图4，显然的根据上述方法制作的氮化物层比用公知高温沉积方法制作的薄膜具有更高的介电质崩溃的时间(TDDB)；也就是说，在摄氏700度下形成的氮化物其TDDB会比在摄氏800度下形成的氮化物高出三倍。图5为一图表，显示以上述方法制作的氮化物层比用公知的高温沉积方法形成的氮化物层具有更高的硅优良率。如图所示，把氮化物沉积制作工艺的温度降低到摄氏700度可以把效能增进13％。
虽然本发明已以一较佳实施例公开如上，然其并非用以限定本发明，任何熟悉此技术者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视权利要求书所界定者为准。

Claims (7)

1.一种半导体元件的制造方法，其特征在于：包括：
提供一晶圆基底；
形成一第一氧化硅层于该晶圆基底上；
以低温沉积制作工艺以及在为275 Torr的一压力下形成一氮化物层于该第一氧化硅层上；
形成一第二氧化硅层于该氮化物层上。
2.如权利要求1所述的制造方法，其特征在于：进一步包括形成一浮栅复晶于该晶圆基底上，且其中该第一氧化硅层是形成在该浮栅复晶上。
3.如权利要求1所述的制造方法，其特征在于：形成该氮化物层的步骤包括在为摄氏700度的一温度下沉积该氮化物层。
4.如权利要求1所述的制造方法，其特征在于：形成该第一氧化硅层的步骤包括在为200Torr的一压力下使硅烷与氧化氮反应。
5.如权利要求1所述的制造方法，其特征在于：该第一氧化硅层的厚度为43埃。
6.如权利要求1所述的制造方法，其特征在于：该氮化物层的厚度为62埃。
7.如权利要求1所述的制造方法，其特征在于：该第二氧化硅层的厚度为59埃。
CNB02155532XA 2002-09-10 2002-12-05 用于快闪存储晶单元的ono内复晶介电质及制作方法 Expired - Lifetime CN100364066C (zh)

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7045847B2 (en) * 2003-08-11 2006-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with high-k gate dielectric
KR100642898B1 (ko) 2004-07-21 2006-11-03 에스티마이크로일렉트로닉스 엔.브이. 반도체 장치의 트랜지스터 및 그 제조방법
KR101432766B1 (ko) * 2006-05-26 2014-08-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작방법
US8283224B2 (en) * 2008-12-23 2012-10-09 Texas Instruments Incorporated Ammonia pre-treatment in the fabrication of a memory cell
US8372714B2 (en) 2010-06-28 2013-02-12 Macronix International Co., Ltd. Semiconductor device and method of manufacturing a semiconductor device
KR101175148B1 (ko) * 2010-10-14 2012-08-20 주식회사 유진테크 3차원 구조의 메모리 소자를 제조하는 방법 및 장치
CN103606513B (zh) * 2013-11-08 2016-02-17 溧阳市江大技术转移中心有限公司 一种半导体电容器的制造方法
CN103594354B (zh) * 2013-11-08 2016-07-06 溧阳市江大技术转移中心有限公司 一种电介质层的制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000101038A (ja) * 1998-09-17 2000-04-07 Sony Corp 半導体装置の製造方法
US6177363B1 (en) * 1998-09-29 2001-01-23 Lucent Technologies Inc. Method for forming a nitride layer suitable for use in advanced gate dielectric materials
US6180538B1 (en) * 1999-10-25 2001-01-30 Advanced Micro Devices, Inc. Process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device using rapid-thermal-chemical-vapor-deposition
US6204125B1 (en) * 1999-06-28 2001-03-20 Hyundai Electronics Industries Co., Ltd. Method of forming a gate in a stack gate flash EEPROM cell
US6413820B2 (en) * 1998-10-13 2002-07-02 Advanced Micro Devices, Inc. Method of forming a composite interpoly gate dielectric

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69631879D1 (de) * 1996-04-30 2004-04-22 St Microelectronics Srl Herstellungsverfahren für einen integrierten Dickoxydtransistor
US5925908A (en) * 1997-07-30 1999-07-20 Motorola, Inc. Integrated circuit including a non-volatile memory device and a semiconductor device
US6051467A (en) * 1998-04-02 2000-04-18 Chartered Semiconductor Manufacturing, Ltd. Method to fabricate a large planar area ONO interpoly dielectric in flash device
US6339000B1 (en) * 1998-09-25 2002-01-15 Conexant Systems, Inc. Method for fabricating interpoly dielectrics in non-volatile stacked-gate memory structures
US6248628B1 (en) * 1999-10-25 2001-06-19 Advanced Micro Devices Method of fabricating an ONO dielectric by nitridation for MNOS memory cells
US6576548B1 (en) * 2002-02-22 2003-06-10 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device with reliable contacts/vias

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000101038A (ja) * 1998-09-17 2000-04-07 Sony Corp 半導体装置の製造方法
US6177363B1 (en) * 1998-09-29 2001-01-23 Lucent Technologies Inc. Method for forming a nitride layer suitable for use in advanced gate dielectric materials
US6413820B2 (en) * 1998-10-13 2002-07-02 Advanced Micro Devices, Inc. Method of forming a composite interpoly gate dielectric
US6204125B1 (en) * 1999-06-28 2001-03-20 Hyundai Electronics Industries Co., Ltd. Method of forming a gate in a stack gate flash EEPROM cell
US6180538B1 (en) * 1999-10-25 2001-01-30 Advanced Micro Devices, Inc. Process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device using rapid-thermal-chemical-vapor-deposition

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