CN100353546C - 封装半导体器件 - Google Patents

封装半导体器件 Download PDF

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CN100353546C
CN100353546C CNB2003101013138A CN200310101313A CN100353546C CN 100353546 C CN100353546 C CN 100353546C CN B2003101013138 A CNB2003101013138 A CN B2003101013138A CN 200310101313 A CN200310101313 A CN 200310101313A CN 100353546 C CN100353546 C CN 100353546C
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pad
projection
semiconductor device
lead
chip
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CN1497720A (zh
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西冈圭
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Rohm Co Ltd
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Abstract

一种封装半导体器件，包括集成芯片和非集成芯片。集成芯片具有集成电路和具有窄节距的第一凸起连接垫片。非集成芯片具有第二凸起垫片以和第一凸起垫片相对、形成具有宽节距的引线垫片(以允许导线连接至此)、和将这些垫片电连接在一起的布线导体。两个芯片通过凸起的方式连接在一起，然后使用树脂密封。使用此结构，就有可能实现能够轻易安装到母板上的低成本封装半导体器件。

Description

封装半导体器件
技术领域
本发明涉及表面安装到主板上的封装半导体器件。
背景技术
传统的封装半导体器件包括形成在诸如硅圆片等的半导体基片上的集成电路以实现器件功能、以预定间距(这样以允许连接到引线的导线粘结在那里)形成的引线连接垫片(下文称作垫片)、用于保护集成电路防止静电破坏的保护电路、通过保护电路将垫片电连接到集成电路的导线，以及覆盖除了垫片之外的所有的部件的保护薄膜。所有这些都使用树脂密封(例如参考日本专利申请公开出版物No.2001-217371)。
最有效降低具有上述结构的封装半导体器件成本的方式就是减小半导体基片的尺寸，以增加自单块圆片割离的芯片数目，由此降低单位成本。传统上为实现此目的，极其强烈的开发出基于增加集成电路的集成密度的目的的技术，以使得形成集成电路的工艺更加精细。
在具有上述结构的封装半导体器件中事实是这样的，增加集成电路的集成密度有利于减小半导体基片的尺寸并在一定程度上降低制造成本。
但是，非常不便的是，在上述结构的封装半导体器件中，当集成电路的集成密度达到一定程度后，半导体基片的尺寸很难再减小，这样制造成本由于需要固定在I/O区域中的尺寸(垫片形成的间距和保护电路的深度(自边缘往基片中部方向上的尺寸))而不能够再降低。考虑到现今导线粘结的准确性，垫片需要在至少110至140μm的间距上形成。而且，考虑到保护电路不能直接形成在垫片的正下方的事实，那里在导线接合时施加了高应力，I/O区域至少需要几百个μm深。
如上所述，在具有上述结构的封装半导体器件中，自现有水平的半导体芯片制造技术的发展增加集成电路的集成密度只会导致布线空间的增加而不会导致成本的降低。相反地，非常矛盾的是，更高的集成密度需要更贵的制造装备，这样增加了制造成本，并降低产出率。在一些传统可获得的产品中，增加集成密度所带来的自由空间的增加用于安装存储器阵列或类似器件以实现更高的性能价格比。但是此结构不能有助于对降低基本制造成本，由此也不能达到用户所需的进一步成本降低的需要。
附带地，在母芯片和子芯片构成的封装半导体器件(例如参考日本专利申请公开出版物No.2000-223652)中，所述母芯片和子芯片通过凸起的方式相互连接以形成芯片上芯片(chip-on-chip)结构，子芯片不需要用于导线接合的垫片，其尺寸能够随着集成密度的增加而减小。但是，采用芯片上芯片结构的目的是将由不同工艺制造的许多芯片集成在一起，或者将由于大规模集成电路(通过转变为垂直结构)导致的芯片面积的增加最小化，或者通过互换子芯片增强不同模型的生产率。这样，在具有此结构的封装半导体器件中，大规模集成电路很自然地也形成在母芯片上，由此使用芯片上芯片结构就有可能减小子芯片的成本，但是不能减小母芯片的制造成本。
传统可获得的封装半导体器件采用被称为CSP(芯片级封装)和BGA(球栅阵列)(例如参考日本专利申请公开出版物No.2000-012733)以减小尺寸并由此减小制造成本。但是，为将具有此结构的封装半导体器件直接安装到母板上，就有必要通过使用照相机识别或其类似装置来准确控制其安装位置，引入这样的装备需要投入大量的资金。这对只具有少量资金的用户而言引入具有上述说明结构的封装半导体器件是非常困难的。
发明内容
本发明的目的是提供一种便宜的并容易安装到母板上的封装半导体器件。
为实现上述目的，根据本发明，封装半导体器件具有：至少一个集成芯片，所述芯片具有实现器件功能的集成电路和以预定间距形成的第一凸起连接垫片；非集成芯片，此芯片具有形成的第二凸起连接垫片以面对第一凸起连接垫片，以大于所述预定间距的间距形成的引线连接垫片；用于电连接所述第二凸起连接垫片和引线连接垫片的布线导体。此处，集成和非集成芯片通过凸起的方式连接在一起，然后使用树脂密封。
根据本发明的一方面，提供了一种封装半导体器件，包括：至少一个集成芯片，包括：实现器件功能的集成电路，以预定间距形成的第一凸起连接垫片；非集成芯片，包括：第二凸起连接垫片，所述第二凸起连接垫片被形成与第一凸起连接垫片相面对，以大于所述预定间距的间距形成的引线连接垫片；和布线导体，所述布线导体用于将第二凸起连接垫片和引线连接垫片电连接在一起，其中集成和非集成芯片通过凸起的方式连接在一起，然后使用树脂密封；以及其中所述第二凸起连接垫片每一个具有被升高的中央部分以具有两层，从而从俯视图中观察时，每个第二凸起连接垫片的较高层部分的面积小于每个第二凸起连接垫片的较低层部分的面积。
附图说明
通过优选实施例的下述说明，并参照附图将会清晰理解本发明的此目的和其它目的及特征：
图1A和1B是显示本发明实施例的封装半导体器件的结构轮廓的视图；
图2显示的是垫片21和22以及布线导体23如何集成地集成的示例的透视图；
图3是显示芯片1、2如何通过凸起的方式连接在一起的示例的截面图。
具体实施方式
图1A和1B是显示本发明实施例的封装半导体器件的结构轮廓的视图。图1A是顶视图，图1B是图1A中沿线X-X’所取的截面图。如这些图中所示，此实施例的封装半导体器件具有集成芯片1和非集成芯片2。两个芯片通过凸起的方式连接在一起以形成芯片上芯片结构，然后使用树脂5密封。
在上述说明的封装半导体器件结构中，在由硅圆片及类似器件形成的集成芯片1上，形成集成电路11以实现器件功能、以预定间距形成的第一凸起连接垫片12(自此至后称为第一凸起垫片12)、防止集成电路11的静电破坏的保护电路13、用于通过保护电路13将第一凸起垫片12电连接到集成电路11的布线导体14、以及用于覆盖除了第一凸起垫片12的所有部件的保护薄膜15。
另一方面，非集成芯片2是和集成芯片1具有几乎相同的膨胀系数，但是和集成电路1不同的是，它不受诸如选择杂质扩散的半导体工艺的影响。在非集成电路2的表面，形成有绝缘薄膜20，在此绝缘薄膜20上，形成第二凸起连接垫片21(自此至后称为第二凸起垫片21)以面对第一凸起垫片12，以大于前述的预定间距(以允许连接到引线4的导线3粘合在此处)的间距形成的引线连接垫片22(自此至后称为引线垫片22)、以及用于将第二凸起垫片21和引线垫片22电连接在一起的布线导体23。附带地，在非集成芯片2本身由绝缘材料(玻璃基片或类似材料)形成的情况下不需要形成绝缘薄膜20。
如上所述，此实施例的封装半导体器件被分为集成芯片1和非集成芯片2，在集成芯片1上独立形成集成电路11，其尺寸由于半导体芯片开发技术的发展可进一步减小，在非集成芯片2上，形成引线垫片22，其尺寸因为它们所要形成的间距的原因不能被进一步减小。
此结构允许集成芯片1的尺寸由于集成电路11的集成密度的增加和后面将要说明的目的而减小。这有助于减小集成芯片1的单位成本，并在整体上有助于减小封装半导体器件的制造成本。特别的，连接凸起的工艺和导线粘结工艺相比，不太可能对垫片的周围产生损坏。这允许保护电路13直接形成在凸起垫片之下(在此实施例中，直接位于第一凸起垫片12之上)，并允许垫片的尺寸比导线粘结的尺寸更小。这样，相应地就有可能减小非集成芯片2的尺寸。不仅如此，通过将由许多阵列构成的集成电路分离为许多集成芯片，就有可能防止一种集成芯片的产出率的降低而在整体上严重影响封装半导体器件的产出率。这将有助于从整体上有助于降低封装半导体器件的成本。
不仅如此，在此实施例的封装半导体器件中，正如在具有传统结构的封装半导体器件中，和母板的电连接是通过离开封装一个宽管脚节距的引线4实现的。通过具有此结构的封装半导体器件，就没有必要非常精确地控制其安装位置，由此就有可能使用现有的安装设备将封装半导体器件安装到母板上。这样，和那些采用CSP或者BGA的相比，此封装半导体器件有助于最小化用户需要引进其的资本投资。
不仅如此，在此实施例的封装半导体器件中，非集成芯片2只形成垫片21和22以及布线导体23，没有任何集成电路。使用此结构，就有可能一种便宜且具有最小所需的物理强度的板状部件(诸如伪硅(dummysilicon)或者玻璃基片)来作为非集成芯片2的基片材料，另外几乎可以保持大约100％的产出率。这和集成芯片1相比有助于大大地减小非集成芯片的制造成本，这样，和尺寸变小的集成芯片1组合，有助于整体减小封装半导体器件的成本。附带地，由于不需要考虑形成在非集成芯片2上器件中产生的变形，如果整体上减小封装半导体器件的厚度是重要的话，非集成电路2的厚度可以变薄为其物理强度的极限。
此实施例的封装半导体器件将被进一步说明。如图2所示，在此实施例的封装半导体器件中，第二凸起垫片21和引线垫片22单独和布线导体23集成形成(在此实施例中，首先形成厚度为6μm的导电金属薄膜，然后施加抗饰膜，然后其被蚀刻)。使用此结构，通过导线图像和垫片形成在半导体芯片上而相对内部器件重复执行对齐，和普通的IC相比就有可能简化IC制造工艺。和传统操作中形成在集成芯片1上的导线粘合垫片和保护电路相比，这有助于减小非集成芯片2和集成芯片1的单位制造成本。这有助于从整体上降低封装半导体器件的成本。
不仅如此，在此实施例中的封装半导体器件中，如图2和3所示，每个第二凸起垫片21具有提升的中间部分，这样具有两层(明确地，第一层垫片21a和第二层垫片21b)。使用此结构，即使在围绕第一垫片12的保护薄膜膨胀而留下一个凸起16在边处比中央要高，凸起16和第二凸起垫片21不仅在边处而且在中央处合并。这有助于增加两个芯片1和2件的粘合强度。
如上所述，根据本发明，封装半导体器件包括：至少一个集成芯片，所述芯片具有用于实现器件功能的集成电路和以预定间距形成的第一凸起连接垫片；非集成芯片，此芯片具有形成的第二凸起连接垫片以面对第一凸起连接垫片、以大于所述预定间距的间距形成的引线连接垫片；用于将第二凸起连接垫片和引线连接垫片电连接的布线导体。此处，集成和非集成芯片通过凸起的方式连接在一起，然后使用树脂密封。使用此结构，就有可能实现能够轻易安装到母板上的便宜的封装半导体器件。
在具有上述结构的封装半导体器件中，适当地，至少第二凸起连接垫片和引线连接垫片之一和布线导体集成地形成。使用此结构，就有可能和垫片一起形成布线导体。这有助于降低非集成芯片的单位成本，这样有助于从整体上降低封装半导体器件的成本。
在具有上述结构的封装半导体器件中，适当地，每个第二凸起连接垫片具有升高的中间部分从而具有两层。使用此结构，即使和第一凸起连接垫片相连的凸起在边缘处比中央要高，凸起部件在边处也在中央处结合到第二凸起连接垫片中。这有助于增加集成和非集成芯片间的粘合强度。

Claims (4)

1、一种封装半导体器件，包括：
至少一个集成芯片，包括：
实现器件功能的集成电路，
以预定间距形成的第一凸起连接垫片；
非集成芯片，包括：
第二凸起连接垫片，所述第二凸起连接垫片被形成与第一凸起连接垫片相面对，
以大于所述预定间距的间距形成的引线连接垫片；和
布线导体，所述布线导体用于将第二凸起连接垫片和引线连接垫片电连接在一起，
其中集成和非集成芯片通过凸起的方式连接在一起，然后使用树脂密封；以及
其中所述第二凸起连接垫片每一个具有被升高的中央部分以具有两层，从而每个第二凸起连接垫片的较高层部分的面积小于每个第二凸起连接垫片的较低层部分的面积。
2、根据权利要求1中所述的封装半导体器件，其特征在于至少第二凸起连接垫片或引线连接垫片与布线导体一体地形成。
3、根据权利要求1中所述的封装半导体器件，其特征在于非集成芯片的基片是伪硅基片或者玻璃基片。
4、根据权利要求1中所述的封装半导体器件，其特征在于所述引线连接垫片的形成间距允许连接到引线的导线粘合到所述引线连接垫片。
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