CN100349282C - 形成半导体结构的方法 - Google Patents
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Abstract
本发明提供一种形成半导体结构的方法,具体为在氮气或其它厌氧气体中,对铜晶种层进行表面处理进而改善铜电镀品质的方法。另一种改善方式是利用抛光处理来加强铜晶种层的可镀性。再一种改善方式是将晶种层在高温中退火,或是在室温下作长时间退火。还有一种改善方式是将晶种层暴露于具有表面活性剂与化学成分的溶液中,将污染物溶解。晶种层的沉积可调整成一种更适合电镀的表面型态,而后续对晶种层的表面处理,可改善镀覆其上铜金属层的品质。
Description
技术领域
本发明有关于集成电路(IC),而特别关于在先进IC制程中,改善铜电镀技术的方法。
背景技术
在先进的半导体集成电路制程中,铜制程是较好的选择,因为铜在实用上提供了最低的电阻,最典型就是被应用在镶嵌式制程中。首先在介电层中形成沟槽及介层窗,将金属阻障层沉积在介电质上用来避免铜金属与介电层的交互作用。接着以物理气相沉积(PVD)的方式将铜晶种层沉积在金属阻障层之上。将铜金属层以电镀方式镀覆在铜晶种层上。以抛光方式除去介电层顶部表面的铜金属层与金属阻障层,留下镶嵌在沟槽及介层窗中的铜导线。
然而,电镀于铜晶种层上的铜金属层会出现缺陷,例如:涡漩纹(swirl patterns)及凹孔(pits)为两种主要的缺陷。涡漩纹缺陷为电镀铜金属层中由小空洞(voids)聚集而成的可见曲线,而小空洞就是没有被铜覆盖的小区域。而另一种主要的缺陷凹孔,则有着不同的特征,凹孔单一来说较大,会形成不同外观,如杯锥状。这两种主要的缺陷限制了电镀在铜晶种层上铜金属层的品质,因此降低了IC制造的生产良率。两种缺陷的出现皆会引起一连串的故障,而造成生产良率的降低及增加品质滑落的风险。因此在集成电路的制造过程中所需要的,就是减少电镀铜过程中所产生缺陷,如涡漩纹和凹孔的改善方法。
图1和图2显示在先前的技术中,铜制程于半导体集成电路制程中最常遇到的两种缺陷。当铜电镀于不规则的晶种层表面时,这两种主要缺陷将会特别明显。如图1所示,在圆形半导体晶圆100上产生了涡漩纹缺陷,曲线是由许多没有镀覆铜的小空洞所形成,此涡漩的分布,明显是由于电解液环流所造成。这些小空洞的存在起因于小型的污染物,典型的污染物为有机物。
如图2所示,在圆形半导体晶圆200呈现了凹孔的聚集,这些凹孔从分布及型态上皆有别于小空洞。基本上凹孔是由普遍大于小空洞的物质聚集而成,一般来说其随意分布且突出于晶种层的表面。
发明内容
有鉴于此,本发明提供数种方法,用来降低电镀铜过程中所产生的缺陷。
本发明至少可使两种缺陷,如涡漩纹及凹孔被消除或减少。通过本发明任一种实施方法来改变铜晶种层的表面结构,有助于进行电镀铜制程时消除涡漩纹和有效减少凹孔。
本发明提供了一种铜晶种层的表面处理方法,进而改善电镀在晶种层上铜金属层的品质。其中一种方法是利用厌氧处理,来避免晶种层上的氧化反应或除去晶中层上的有机污染物及氧化物,另一种方法是利用抛光铜晶种层表面来加以改善。还有一种方法是利用退火处理来改善铜晶种层表面的性质。
本发明也提供了调整铜晶种层结构的方法,换言之,就是改善晶种层的表面型态,进而改善电镀在铜晶种层上铜金属层结构。一方面利用改善晶种层的织构(texture)来增加其表面的粗糙度,另一方面降低后续铜金属层的晶粒大小。上述所提及方法,改善了电镀在铜晶种层上铜金属层的品质及生产良率。
本发明是这样实现的:
本发明提供一种形成半导体结构的方法,所述形成半导体结构的方法包括下列步骤:提供一半导体基底,该基底上包含一具有开口的介电层;在该开口中形成一阻障层(barrier layer);在该阻障层上形成一晶种层;以无氧气体对该晶种层进行处理;以及以无氧气体对该晶种层进行处理后,在该晶种层上形成一导电层,该导电层包含了多个晶粒尺寸大抵小于600nm的晶粒。
本发明所述的形成半导体结构的方法,该处理方式包含在氮气气氛下进行。
本发明所述的形成半导体结构的方法,该处理方式包含在氢气、氦气或氩气气氛下进行。
本发明所述的形成半导体结构的方法,该处理过程超过5分钟。
本发明还提供一种形成半导体结构的方法,所述形成半导体结构的方法包括下列步骤:提供一半导体基底,该基底上包含一具有开口的介电层;在该开口中形成一阻障层;在该阻障层上形成一晶种层;抛光该晶种层表面;以及形成一导电层,该导电层包含了多个晶粒尺寸大抵小于600nm的晶粒。
本发明所述的形成半导体结构的方法,该抛光处理包含了一逆电镀步骤。
本发明所述的形成半导体结构的方法,该抛光处理包含了在1至60秒内除去部分该晶种层。
本发明所述的形成半导体结构的方法,该抛光处理包含了一溅射(sputter)蚀刻步骤。
本发明所述的形成半导体结构的方法,该溅射蚀刻步骤在含氮、氢或氩等离子中进行。
本发明另提供一种形成半导体结构的方法,所述形成半导体结构的方法包括下列步骤:提供一半导体基底,该基底上包含一具有开口的介电层;在该开口中形成一阻障层;在该阻障层上形成一晶种层;将该晶种层退火;以及将该晶种层退火后,在该晶种层上形成一导电层且平坦化该导电层,该导电层包含了多个晶粒大小大抵小于600nm的晶粒。
本发明所述的形成半导体结构的方法,该退火处理在室温下进行0.5至100小时。
本发明所述的形成半导体结构的方法,该退火处理包括了在温度范围50℃至300℃中进行。
本发明所述的形成半导体结构的方法,该退火处理包括了在温度范围50℃至150℃至少进行10分钟。
本发明所述的形成半导体结构的方法,该退火处理在无氧环境下进行。
附图说明
图1显示涡漩纹缺陷,其为现有技术中,小空洞在电镀铜内所形成明显的曲线;
图2显示凹孔缺陷,其为现有技术中,随机分布于电镀铜内的凹穴;
图3绘出本发明一较佳实施例用来减少涡漩纹及凹孔缺陷的方法。
具体实施方式
为了让本发明的上述及其它目的、特和优点能更明显易懂,下文特举出较佳实施范例,并配合所附图示,做详细说明如下:
铜晶种层的目的,是为了提供一导电表面,以便于铜电镀其上。铜在进行电镀时必须紧附着晶种层,并且累积成均匀且平顺的铜金属层,因此晶种层的品质相当关键,必须提供一干净、均匀及易反应的表面。
本发明着重在改进铜电镀制程开始前,铜晶种层的表面特性,以改善电镀铜薄膜的性质。利用适当的表面处理,来防止或清除铜晶种层上的污染物,以预防涡漩纹缺陷及凹孔缺陷的产生,或有效减少这两种缺陷。通过增加粗糙度的表面处理,也可改变铜晶种层的表面特性,借此来预防涡漩纹缺陷及凹孔缺陷的产生。接下来的电镀铜金属层会形成在经过表面处理而增加粗糙度的铜晶种层表面。经平坦化过程后,铜金属层多个晶粒的晶粒大小会小于只经过传统制程铜金属层表面的晶粒大小,且多个晶粒大小大抵小于600nm。在经过表面处理的铜晶种层上所形成铜金属层,其涡漩纹缺陷及凹孔缺陷也会减少。事实上,铜晶种层的表面处理可以增加表面粗糙度,进而降低铜金属层的晶粒大小。
铜晶种层可通过多种不同方法形成在半导体基底上,其中包括:物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)或传统的电镀技术。铜晶种层的厚度大约分布在10nm至500nm之间,但在其它实施方法中会有所改变。
本发明的实施方法中提供了多种对于铜晶种层表面的处理方法。如图3所示,先提供一具有介电层4的半导体基底2,在介电4层中形成开口6;于开口6中形成金属阻障层8,接着将铜晶种层10形成在阻障层8之上。介电层4包含了一低介电常数的材料,如含氮、碳或氢的材料,介电常数k值小于3.3。第一种表面处理方法是一种厌氧处理,例如用氮对晶种层表面12进行处理,此处理成功地防止氧化的发生,以及除去铜晶种层表面12的氧化物和有机污染物,进而在电镀制程中产生无涡漩纹缺陷的铜金属层14。氮处理包含了在室温下于充满氮气气氛中,作氮电荷处理或氮等离子处理,商用上有各种方法皆适用于本发明。在本发明的实施方法中,利用至少约600秒的氮电荷处理。厌氧处理可增加铜晶种层的表面粗糙度以防止涡漩纹缺陷的发生及减少凹孔缺陷。在平坦化过程后,铜金属层的多个晶粒的晶粒大小大抵小于600nm。厌氧处理须在无氧的环境下进行,氢、氦、氩及其它非氧化性或还原性媒介皆可择一或额外使用。在铜晶种层上的厌氧处理,可与晶种层沉积步骤在同机台或不同机台中进行。
本发明的第二种表面处理方式是利用抛光处理。抛光处理可以是在铜电镀开始前于铜晶种层表面作短暂的逆电镀(reverseelectroplating)或消除电镀(de-plating),或单纯地移除部分晶种层。消除电镀技术意味着将铜晶种层浸泡在电解液中,不需通电流,轻微地将部分晶种层移除,特别是一些较突出的部分。消除电镀的步骤大约持续1至60秒,可与电镀铜制程于同一机台进行。在本发明的另一种实施方法中,利用溅射蚀刻作抛光处理,只有极少量的晶种层材料在溅射蚀刻中被移除,但是能优先清除表面污染物,使粗糙表面能被优先电镀。移除部分晶种层的溅射蚀刻制程可与晶种层的沉积制程于相同机台中进行。溅射蚀刻后铜晶种层的表面品质改善。溅射蚀刻制程可在一等离子环境,包括含氢、氮或氩的等离子中进行。抛光处理也能增加铜晶种层的表面的粗糙度,以避免涡漩纹缺陷的产生以及减少凹孔。接着在经过表面处理而增加粗糙度的铜晶种层表面电镀铜。平坦化制程后,铜层多个晶粒大小大抵小于600nm。
本发明的第三种表面处理方式是利用退火处理。退火处理是以加热方式或是在室温下放置一段时间,使铜晶种层的晶格结构产生改变。铜晶种层的表面粗糙度在退火的过程中会增加,因此在化学机械研磨(CMP)后,铜晶格的平均晶粒大小会降低。在平坦化制程后,铜金属层多个晶粒尺寸大抵小于600nm。退火条件包括:在氮气气氛下或其它非氧化性气体中,温度保持在50℃至300℃退火1分钟至6小时。在本发明的实施方法中,将铜晶种层和基底置于一惰性气体中,如氮气气氛下,温度范围大约在50℃至150℃退火1分钟至30分钟。在本发明的另一种实施方法中,将铜晶种层和基板置于惰性气体中,如氮气中,温度范围50℃至150℃,至少退火10分钟,然而其它热处理条件可择一使用。可使用一般的退火炉。若要在室温条件下退火,可在后续电镀铜制程开始前让基底在室温下停留0.5至100小时。
铜晶种层沉积与电镀铜两步骤的时间间隔须有所限制,以避免铜晶种层久置而产生氧化,在本发明的实施方法中,电镀铜步骤可在完成晶种层沉积后的72小时内开始。
这些处理方式单独或合并使用,皆有助于避免或减少涡漩纹缺陷或凹孔缺陷的产生。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
Claims (14)
1、一种形成半导体结构的方法,所述形成半导体结构的方法包括下列步骤:
提供一半导体基底,该基底上包含一具有开口的介电层;
在该开口中形成一阻障层;
在该阻障层上形成一晶种层;
以无氧气体对该晶种层进行处理;以及
以无氧气体对该晶种层进行处理后,在该晶种层上形成一导电层,该导电层包含了多个晶粒尺寸小于600nm的晶粒。
2、根据权利要求1所述的形成半导体结构的方法,其特征在于:该处理方式包含在氮气气氛下进行。
3、根据权利要求1所述的形成半导体结构的方法,其特征在于:该处理方式包含在氢气、氦气或氩气气氛下进行。
4、根据权利要求1所述的形成半导体结构的方法,其特征在于:该处理过程超过5分钟。
5、形成半导体结构的方法,所述形成半导体结构的方法包括下列步骤:
提供一半导体基底,该基底上包含一具有开口的介电层;
在该开口中形成一阻障层;
在该阻障层上形成一晶种层;
抛光该晶种层表面;以及
形成一导电层,该导电层包含了多个晶粒尺寸小于600nm的晶粒。
6、根据权利要求5所述的形成半导体结构的方法,其特征在于:该抛光处理包含了一逆电镀步骤。
7、根据权利要求5所述的形成半导体结构的方法,其特征在于:该抛光处理包含了在1至60秒内除去部分该晶种层。
8、根据权利要求5所述的形成半导体结构的方法,其特征在于:该抛光处理包含了一溅射蚀刻步骤。
9、根据权利要求8所述的形成半导体结构的方法,其特征在于:该溅射蚀刻步骤在含氮、氢或氩等离子中进行。
10、形成半导体结构的方法,所述形成半导体结构的方法包括下列步骤:
提供一半导体基底,该基底上包含一具有开口的介电层;
在该开口中形成一阻障层;
在该阻障层上形成一晶种层;
将该晶种层退火;以及
将该晶种层退火后,在该晶种层上形成一导电层且平坦化该导电层,该导电层包含了多个晶粒大小小于600nm的晶粒。
11、根据权利要求10所述的形成半导体结构的方法,其特征在于:该退火处理在室温下进行0.5至100小时。
12、根据权利要求10所述的形成半导体结构的方法,其特征在于:该退火处理包括了在温度范围50℃至300℃中进行。
13、根据权利要求10所述的形成半导体结构的方法,其特征在于:该退火处理包括了在温度范围50℃至150℃至少进行10分钟。
14、根据权利要求10所述的形成半导体结构的方法,其特征在于:该退火处理在无氧环境下进行。
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US10/976,376 US20060094237A1 (en) | 2004-10-29 | 2004-10-29 | Methods to completely eliminate or significantly reduce defects in copper metallization in IC manufacturing |
US10/976,376 | 2004-10-29 |
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US7267861B2 (en) * | 2005-05-31 | 2007-09-11 | Texas Instruments Incorporated | Solder joints for copper metallization having reduced interfacial voids |
JP2007134592A (ja) * | 2005-11-11 | 2007-05-31 | Renesas Technology Corp | Cu配線形成方法 |
KR100720532B1 (ko) * | 2005-12-29 | 2007-05-22 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조방법 |
JP2007305640A (ja) * | 2006-05-09 | 2007-11-22 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
CN101937864B (zh) * | 2009-07-03 | 2012-03-07 | 中芯国际集成电路制造(上海)有限公司 | 接触孔填充方法 |
US8357599B2 (en) * | 2011-02-10 | 2013-01-22 | Applied Materials, Inc. | Seed layer passivation |
TWI653726B (zh) | 2014-03-10 | 2019-03-11 | 聯華電子股份有限公司 | 半導體中間板以及其製法 |
CN109585365A (zh) * | 2018-11-30 | 2019-04-05 | 上海华力微电子有限公司 | 互连结构的制造方法 |
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US6080656A (en) * | 1999-09-01 | 2000-06-27 | Taiwan Semiconductor Manufacturing Company | Method for forming a self-aligned copper structure with improved planarity |
US6402592B1 (en) * | 2001-01-17 | 2002-06-11 | Steag Cutek Systems, Inc. | Electrochemical methods for polishing copper films on semiconductor substrates |
US6716753B1 (en) * | 2002-07-29 | 2004-04-06 | Taiwan Semiconductor Manufacturing Company | Method for forming a self-passivated copper interconnect structure |
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US20080176397A1 (en) | 2008-07-24 |
TW200614381A (en) | 2006-05-01 |
US20060094237A1 (en) | 2006-05-04 |
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