CH715005A2 - Device for converting a DC voltage that varies within wide limits into a multi-phase AC voltage with variable frequency and amplitude. - Google Patents

Abstract

A converter according to the invention for the transmission of electrical energy between a direct current (DC) system and an alternating voltage (AC) system has on the DC side a positive DC input voltage rail (1) and a negative DC input voltage rail (2) and at least two output phase terminals on the AC side (a, b, c). In this case, there is a phase converter for each of the output phase terminals (a, b, c), which on a first side to the positive DC input voltage rail (1) and the negative DC input voltage rail (2) and on a second side to this output phase terminal (a ; b; c) is connected and is designed as a step-up buck converter with a voltage intermediate circuit. The converter has a control which is designed, during operation of the converter, to convert each of the phase converters as a function of a ratio of a DC input voltage to instantaneous values of output phase voltages to be generated at the output phase terminals (a, b, c), either as a pure buck converter or temporarily as a pure boost converter to operate.

Description

Description In drive technology, there is often the task of starting from a DC voltage source (battery storage or fuel cell) to feed a three-phase machine, the three-phase voltage to be applied to the machine having a predetermined amplitude and frequency by means of a higher-level speed or position control. For stationary operation, both amplitude and frequency typically show an approximately proportional dependency on the machine speed, i.e. are variable within wide limits. Furthermore, depending on the state of charge of the battery or due to a voltage drop in the internal resistance of the battery or the fuel cell, the supplying DC voltage can have a relatively wide range of variation.

According to the prior art, the DC voltage source is therefore a DC / DC step-up converter, which generates a constant DC output voltage (intermediate circuit voltage), from which a subsequent three-phase pulse-changing rectifier stage is fed, which generates pulse-width-modulated output voltages, which may be by a subsequent LC low-pass filter to be smoothed into a sinusoidal output voltage curve {see Fig. 1). In principle, the level of the intermediate circuit voltage is in any case higher than the level of the supplying DC voltage and, in addition, chosen so large that the three-phase output voltage can be generated with the required amplitude.

A disadvantage of this solution is that both the DC / DC step-up converter and the three-phase pulse inverter convert the entire power, i.e. There is a two-stage power conversion between the DC voltage source and the machine, which results in correspondingly high control and switching losses or results in a relatively low efficiency of energy conversion.

It should be pointed out that the converter structure described also when the energy direction is reversed, that is to say for applications in which a DC voltage which fluctuates within wide limits must be generated starting from a three-phase mains voltage, as is the case e.g. is the case with the battery charging of electric vehicles. The DC / DC step-up converter then works as a DC / DC step-down converter from the DC link voltage due to the reversed energy direction and regulates the power or current flow from the DC link to the battery. In this case, the three-phase AC / DC converter acts as an active rectifier and ensures a sinusoidal profile of the currents drawn from the network and a constant value of the intermediate circuit voltage.

The object of the invention is therefore to provide a device with an associated modulation and control method which, with an overlapping input and output voltage range, converts the power offered by a DC voltage source into a three-phase AC voltage with a predeterminable frequency and amplitude, but with lower conductance and Switching losses or with increased energy conversion efficiency.

This object is achieved by a converter for the transmission of electrical energy between a DC and an AC system according to the patent claims. A high-frequency clocking for forming takes place in only one stage.

The converter for power electronic energy conversion is to be designed in a phase-modular manner and each phase module has two stages, i.e. with an input-side DC / DC step-up converter (phase step-up converter) and an output-side DC / DC step-down converter (phase step-down converter). The phase step-up converter then generates, based on the DC input voltage, a phase DC link voltage supported by a phase DC link capacitor whose negative terminal is connected to the negative input voltage terminal. From this phase intermediate circuit voltage, a phase terminal voltage, which is again related to the negative input DC voltage rail and is applied to the associated phase terminal of the three-phase machine, is generated by the phase step-down converter. Since, due to the typically isolated or free star point of the three-phase machine fed, only the differences in the phase terminal voltages or only the zero-size or common-mode components, i.e. Only the push-pull components of the phase terminal voltages (machine phase voltages) determine the machine phase current profile, so a sinusoidal profile of the machine phase currents can be impressed despite the unipolarity or DC voltage nature of the phase terminal voltages. Alternatively, the positive input voltage rail can also be used as a reference potential for the phase intermediate circuit voltage and the phase terminal voltage, the positive terminal of the phase intermediate circuit capacitor then being connected to the positive input voltage rail.

Although the circuit described above has two conversion stages in each phase, i.e. a step-up / step-down converter structure, however, in contrast to the conventional system, the separation into phase modules allows each phase link voltage to be selected independently of the other phase link voltages and depending on the phase terminal voltage to be generated, i.e. the intermediate circuit voltage level is not the same for all phases and is also not determined by the phase with the highest voltage requirement. The respective phase link voltage is now advantageously carried out in such a way that only one of the two stages, i.e. either only the phase step-up converter or only the phase step-down converter is clocked and the other stage remains switched through, i.e. Switching losses therefore only occur for one of the two switching stages of a phase module or, in this sense, there is a single-stage high-frequency voltage conversion. The switching losses of the phase modules thus advantageously have a minimum, i.e. a lower value than for a realization according to the prior art.

CH 715 005 A2 The converter thus has a control which is designed to operate each of the phase converters, at times as pure, depending on a ratio of a DC input voltage to instantaneous values of output phase voltages to be generated at the output phase connections, during operation of the converter Step-down converter or to operate as a pure step-up converter. The phase converters are therefore designed as multi-loop regulated high-step-down DC / DC converters, the setpoints of the phase converter output voltages being specified such that, on the one hand, a minimum maximum value of the output voltages is required and, on the other hand, a minimal fluctuation in the currents results in the inductances of the phase converters. This means that small inductance values can be selected for the implementation of the converter at a given switching frequency and small switching frequencies can be selected for given inductance values, or small switching losses can occur.

In embodiments, the control is designed to temporarily limit a clocking of switches of the phase converter to an input-side step-up converter part or bridge branch or to an output-side step-down converter part or bridge branch of the phase converter in the operation of the converter in each of the phase converters.

In embodiments, the control is designed to carry out the clocking of all phase converters during operation of the converter in such a way that the same clock frequency is present for all phase converters and synchronization of the clocking of the converters minimizes a push-pull voltage component contained in the output phase voltages.

In embodiments, the control is designed to carry out the clocking of all phase converters during operation of the converter such that the same clock frequency is present for all phase converters and synchronization of the clocking of the converters minimizes a common-mode voltage component contained in the output phase voltages.

In embodiments, the control system is designed to specify an offset for the formation of output phase voltage setpoints from load phase voltage setpoints during operation of the converter, such that an output phase voltage setpoint equal to zero results in each time period for the phase converter whose associated load phase voltage setpoint has the highest negative value , with which this phase converter does not have to be clocked and its output phase connection can remain clamped to a reference voltage rail, and the course of the output phase voltage setpoints of non-clamped phase converters that are to be generated in relation to the clamped output phase connection and that are defined by subtracting two load phase voltage setpoint setpoint values from this load segment in this time period , so that there is again a sinusoidal curve of all load line voltages.

In embodiments, the phase converters are each designed as a cascaded step-down converter (boost-buck converter).

In embodiments, the control is designed to choose a constant offset of the output phase voltages so large during operation of the converter with relatively small amplitudes of the output phase voltages that, on the one hand, a fluctuation in the output phase voltages caused by load phase voltages to be generated symmetrically about a level of the DC Input voltage comes to lie, and on the other hand a double maximum amplitude of load phase voltages is not exceeded, this being achieved by lowering the offset at high amplitudes of the load phase voltages.

[0016] In embodiments, one or more of the following features are implemented:

The control is designed to add an offset signal which has a value which varies with three times the output frequency, i.e. an offset with a 3rd harmonic, with an amplitude and phase position such that a larger output voltage amplitude can be achieved.

- There is no output filter, i.e. the switching point (s) are connected directly to the motor terminals.

- A third bridge arm is arranged on the phase link capacitor and thus a double output voltage amplitude is possible without increasing the intermediate circuit voltage and reverse voltage capability of the semiconductors.

- A third and fourth bridge branch are arranged on the phase output capacitor and thus a double output voltage amplitude is possible without increasing the intermediate circuit voltage and reverse voltage capability of the semiconductors, and in addition a sinusoidal common mode voltage is generated at the output, which has a better EMC behavior.

In the following the subject matter of the invention is explained in more detail using preferred exemplary embodiments which are illustrated in the accompanying drawings. Each shows schematically:

Fig. 1: A converter system according to the prior art, which has a DC / DC step-up converter stage on the input side and thus forms a DC link voltage based on the negative input voltage rail, supported by an intermediate circuit capacitor, from which a subsequent three-phase pulse inverter stage is fed, and further an output low-pass filter is provided for smoothing the pulse-width-modulated output voltages of the pulse inverter stage, so that the machine terminal voltages show an approximately sinusoidal curve.

CH 715 005 A2 Fig. 2: Circuit structure of a phase-modular DC / AC converter with step-up converter function. The low-pass filtered voltages generated at the phase outputs are related to the negative input voltage rail 2. The arrangement requires an isolated machine star point.

Fig. 3: Time course of the phase converter output voltages to be generated when supplying a three-phase machine for (Fig. 3.1) constant offset offset uOff of the load phase voltage system actually to be generated in the amount of the amplitude of the load phase voltage; (Fig. 3.2) with constant offset shift and additional superimposition of an alternating component of the offset signal with triple output frequency and a phase position such that the maximum value of the phase converter output voltages is minimized; (Fig. 3.3) in the event of an offset shift of the load phase voltage system to be generated in such a way that a setpoint value equal to zero is present for a phase converter output over a third of the output period, and this converter can therefore remain in the clamped state, ie is not clocked.

Fig. 4: Time course of the setpoints of the phase converter output voltages u _an , u _bn and u _cn for the converter circuits according to Fig. 2, which can be used in comparison to the DC input voltage U _{in a} small amplitude U _Mp k of the setpoints of the load phase voltages, in order to minimize the switching frequency fluctuation of the current in the phase converter inductances L _A and L _B.

Fig. 5: Device for regulating the output voltages of the phase converter to set a predetermined course Uam * of the load phase voltages u _am , as is required for UPS systems or for the supply of variable-speed three-phase machines. The regulation has the same structure for each phase and is only shown for one phase for reasons of clarity.

Fig. 6: Modification of part of the control devices according to Fig. 5, d. H. the device for regulating the output voltages is expanded by an intermediate circuit voltage and input current regulator in order to achieve higher control dynamics and to actively dampen any vibrations in the system.

Fig. 7: Alternative designs of the power section when using a three-phase machine with an open winding, ie with accessibility of the beginnings and ends of each machine phase winding, the circuit of a phase module according to FIG. 2 around a third bridge branch B _c with switching point C, in parallel the two bridge branches B _A and B _b .

8: (a) Time course of the phase converter output voltages u _aC , u _b c and u _cC for the converter circuits according to FIG. 7, (b) the voltage at the switching point C of the bridge arm B _c and the phase link capacitor voltage u _CA , (c ) of the two duty cycles d _A and de, and (d) the switching states of the individual bridge branches over an output period, the shaded area representing the high-frequency switching of the corresponding bridge branch.

Fig. 9: Alternative designs of the power section when using a three-phase machine with an open winding, ie with accessibility of the beginning and end of each machine phase winding, the circuit of a phase module according to FIG. 2 with a third and fourth bridge branch B _D and B _E with the switching points D and E is expanded.

10: (a) Time course of the phase _{converter output voltages} u _aE , u _bE and u _c e for the converter circuits according to FIG. 9, (b) the voltage at the switching points D and E and the phase link capacitor voltage u _CA , (c) of the two duty cycles d _A and d _B and (d) the switching states of the individual bridge branches over an output period, the hatched area representing the high-frequency switching of the corresponding bridge branch.

2, each phase converter of the system on the input side has a first inductor L _A , the first connection of which is connected to the positive DC input voltage rail 1 and the second connection of which to the switching point A of a first bridge arm B _A , that is to say the common one Connection point of the lower emitter or source connection of an upper switch Τ _Ί and the upper collector or drain connection of a lower switch T ₂ , is performed. Furthermore, the outer connections of the first bridge branch Sa are connected to a phase link capacitor C _A , ie the collector or drain connection of the upper switch Τ _Ί is connected to the positive terminal of the phase link capacitor C _A and the emitter or source connection of the lower switch T ₂ to led negative terminal of the phase link capacitor, which in turn is connected to the negative DC input voltage rail 2. The phase link capacitor C _A thus supports the generated phase link voltage u _CA against the negative input voltage rail 2. A bridge branch is generally realized with power transistors, a free-wheeling diode being connected in anti-parallel with both transistors. Likewise, a second bridge arm B _b with an upper switch T ₃ and a lower switch T ₄ , parallel to the first bridge arm B _A , is connected between the positive and negative terminals of the phase link capacitor C _A , the switching point B of which is connected to a first connection of a second inductance L. _B is connected and whose second terminal is led to the positive terminal of a b for smoothing the output voltage u _C necessary phase output capacitor C _B to which the associated output terminal phase a, b or c branches. The negative terminal of a phase output capacitor C _B is connected to the negative input voltage rail 2, ie the reference voltage rail n, and thus supports the generated phase terminal voltage u _an , u _bn or u _cn . Each phase converter thus has the structure of a step-down converter DC / DC converter relative to the common reference voltage rail n

CH 715 005 A2 sen phase link voltage Uca depending on the ratio of input voltage Um and assigned phase output voltage u _an , u _bn or u _cn , but independently of the other phases.

A three-phase load is connected with its phase terminals to the output phase terminals a, b and c of the three phase converters and has a free star point m, so that only the phase converter output voltages connected together (load line conductor voltages), defined as the difference of two phase converter output voltages or one Load phase clamp against a load star point measured load phase voltage u _am , U _bm and u _{cm determine} the formation of the load phase currents.

The phase converter output voltages u _an , u _bn and u _cn are generated, for example, in such a way that the nominal values of the load phase voltages u _am , u _bm and u _cm, which typically run sinusoidally with the output frequency and form a symmetrical three-phase system, by means of an offset u which is constant over time in the simplest case _o h are shifted to positive values such that each phase output voltage shows a unipolar curve, ie only positive values or minimally the value zero (see Fig. 3.1). As mentioned above, this offset is not effective in the load line voltages and therefore has no influence on the current generation of the load. In embodiments, a further offset with triple output frequency and an amplitude and phase can be added to this constant offset in such a way that the unipolarity of the output phase voltages is ensured with a minimum value of the constant offset, with which the voltage loading of the transistors of both bridge branches _BA and _{BB of} the phase converter can be minimized with a defined load phase voltage amplitude to be generated (see Fig. 3.2).

With regard to the timing of the input and output-side bridge branches B _A and B _b , the phase converter should be noted that in areas in which a phase converter output voltage above the DC input voltage has to be generated, the upper switch or power transistor T _{3 of} the output side Bridge arm B _{b of} a phase converter can remain switched through and only the input-side bridge arm B _{Ä is} clocked. The voltage translation of the converter then corresponds to that of a step-up converter for power flow from the DC input voltage to the phase converter output voltage, the input-side phase converter inductance L _A as step-up converter inductance, the lower power transistor T _{2 of} the input-side bridge arm B _A as step-up converter transistor and the upper power transistor, T of the parallel diode acts as a step-up converter freewheeling diode, the upper power transistor T- also always being switched through in embodiments, ie the power transistors of the input-side bridge branch Sa are operated in push-pull mode. Since anti-parallel diodes are arranged to all power transistors, a power flow can then also take place from the phase converter output voltage to the DC input voltage, the function of the phase converter in this case corresponding to that of a step-down converter located between the phase converter output voltage and the DC input voltage.

In areas in which a phase converter output voltage lying below the DC input voltage must be generated, the upper power transistor Τ _{Ί of} the input-side bridge _arm B _{a of} the phase _{converter remains switched through} in embodiments, and the clocking is limited to the output-side bridge arm B _b . The voltage translation of the converter then corresponds to that of a step-down converter for power flow from the DC input voltage to the phase converter output voltage, the output-side phase converter inductance U as a step-down converter inductance, the upper power transistor T _{3 of} the output-side bridge branch B _b as a step-down converter transistor and the diode ₄ lying opposite to the lower power transistor Step-down converter freewheeling diode acts, the lower power transistor Ta also always being switched through in embodiments, ie the power transistors of the output-side bridge arm B _{b are operated} in push-pull mode. Since anti-parallel diodes are arranged to all power transistors, a power flow can then also take place from the phase converter output voltage to the DC input voltage, the function of the phase converter in this case corresponding to that of a step-up converter located between the phase converter output voltage and the DC input voltage.

With regard to the clocking of all phase converters, it should be pointed out that in embodiments, the same clock frequency can be selected for all phase converters and the clocking of the converters can be synchronized in such a way that the push-pull voltage component contained in the phase converter output voltages, which leads to switching-frequency currents and thus possibly High frequency losses in the connected three-phase load leads, is minimized, ie switching frequency changes in the phase converter output voltages are formed primarily as common mode components, which bring about a similar voltage shift with respect to the reference voltage rail for all phase outputs.

For consumers who are particularly sensitive to high-frequency common-mode shifts, on the other hand, the phase converter, which in this case also works with the same clock frequency, can be synchronized in such a way that the switching-frequency common-mode voltage components are minimized, but then a higher push-pull component of the phase converter output voltages is purchased take is.

An alternative to FIGS. 3.1 and 3.2, the course of the offset is defined in such a way that an output phase voltage setpoint equal to zero results for that phase converter whose assigned load phase voltage has the highest negative value (see FIG. 3.3), with which this phase converter does not must be clocked, or the associated output phase terminal can remain clamped to the reference voltage rail, which for the phase converter topology described above (see FIG. 2) can be achieved simply by switching through the lower power transistor T _{4 of} the output branch bridge B _b . The course of the output voltage setpoints of the other two

CH 715 005 A2

Phase converter is then defined directly by the sections of the setpoint values of the load line conductor voltages to be generated with respect to the clamped phase and to be formed by subtracting two load phase voltage setpoints, so that a sinusoidal course of all three load line voltages is again achieved. Since the clamping takes place cyclically between in one phase after the other, each phase remains clamped for a third of the load phase voltage period when a sinusoidal symmetrical load phase voltage system is generated and thus without switching losses, thus increasing the efficiency of the energy transmission.

For use of the system for feeding a three-phase machine (load) located at the output phase terminals, different amplitudes of the load phase voltage or different amplitudes of the associated phase converter output voltages are to be generated depending on the speed of the machine, typically at highest speed, the highest amplitude values occur for which power semiconductors of both bridge branches are to be designed.

At low speeds or relatively small amplitudes of the phase converter output voltages, the constant offset can advantageously be chosen so large that on the one hand the fluctuation in the phase converter output voltages caused by the load phase voltages to be generated comes to lie symmetrically around the level of the DC input voltage and on the other hand, the double maximum amplitude of the load phase voltage assigned to the maximum speed is not exceeded, this being achieved by correspondingly lowering the offset at high amplitudes of the load phase voltages. As shown in FIG. 4, the setpoint values of the phase converter output voltages then typically have minimum values significantly greater than zero and the currents in the phase converter inductances show a relatively low ripple, since the bridge arm on the input and output sides then alternate with duty cycles close to one (i.e. the the upper power transistors are almost constantly switched through), which is known to result in a low switching frequency fluctuation in the current in the phase converter inductances, which in turn is expressed in low high-frequency losses. Even taking into account the higher switching losses in both bridge branches due to the higher switched phase converter output voltage, the efficiency of the energy transmission can be improved.

With regard to the implementation of the phase converter, it should be noted that in addition to the embodiment described above, there are a number of advantageous modifications:

In embodiments, the bridge branch on the input and / or output side can advantageously have a multilevel structure, e.g. are designed as a flying capacitor multilevel branch, which means that a higher number of voltage levels is available for setting the voltage conversion between the DC input voltage and the phase converter output voltage, which means that there is a lower switching-frequency ripple in the currents in the phase inductors.

In addition, in embodiments, the phase converters can be implemented by a plurality of parallel, phase-shifted systems, so that the current fed into the output capacitance and the current drawn from the DC input voltage advantageously have a higher effective frequency and a smaller fluctuation compared to a single system.

Analogously to the system according to the prior art, in the simplest case the LC output filter of the phase converter, consisting of the phase converter inductor L _B on the output side and the phase output capacitor C _B , can be omitted, ie the switching point B of the second bridge branch 6b directly forms the phase output a, b or c and thus the three-phase pulse width modulated voltage system is connected directly to the motor terminals.

A possible embodiment of a cascaded control of the phase-modular converter system is shown in FIG. 5. The control circuit is identical for each phase and, for the sake of clarity, only shown for one phase. As entered, voltages are measured against the reference voltage rail n or the negative DC input voltage rail 2.

The setpoint of a phase converter output voltage u _an * is obtained by adding the typically sinusoidal setpoint u _am * of the associated load phase voltage u _on a three-phase load (for example an electrical machine M) and the setpoint u _o h * of the offset u which is the same for all phases _o tf is formed, which is typically produced by adding a component u _O ff, Dc * which is constant over the output period and a component u _O ff, Ac * which fluctuates with three times the output frequency. The time course of u _O ff * is chosen so advantageous that u u _in * for a given to generating load phase voltage system _at * is limited to the lowest possible value, whereby the blocking voltage stresses and switching losses are minimized in the two bridge branches of the phase converter. This includes a specification of u _o h * such that a phase converter remains in the clamped state over a third of the initial period, ie u _an * has correspondingly wide intervals with u _an * = 0. The phase converter output voltage setpoint u _an * is compared with the measured actual value u _at the phase converter output voltage and the control deviation Au _at * is fed to a phase converter output voltage regulator Ru _an , at whose output the output capacitor current setpoint iC _B * required to correct Au _an * is formed, which is formed by a pre

CH 715 005 A2

Control of the measured associated load phase current i _a , which determines the reference current I _L b * in the output-side phase converter inductance L _b . By comparing I _L b * with the measured actual value I _L b, the control deviation Ai _{LB of} the current in L _{B is then} formed and fed to a phase inductance current controller Ri _LB , which has at its output the setpoint u _L b * required to correct the control deviation Ai _LB the voltage to be applied to L _B. Adding the phase converter output voltage setpoint u _an * to the controller output setpoint u _L b * results in the voltage u _B * to be applied to switching point B on average over a switching period. If this voltage setpoint d _B d _B * is below the input voltage U, _n , then in the sense of a step-down converter function the duty cycle d _B , ie the relative duty cycle of the upper transistor T ₃ of B _b , is obtained by dividing the voltage setpoint u _B * by the actual value of DC input voltage U _{in is} calculated, ie d _B <1 and thus the output-side bridge arm B _b is clocked at high frequency in accordance with the pulse width modulation. The pulse duty factor d _A , ie the relative duty cycle of the upper transistor T-ι of B _a , is calculated in reverse by dividing the actual value of the DC input voltage U _in by the voltage setpoint u _B *, but previously the voltage setpoint u _B * .auf a minimum value equal to the actual value of the DC input voltage U, _{n is} limited and in this case leads to a duty cycle d _A = 1 with u _B * <U, _n , ie corresponds to a constant switching on of the upper transistor Τ _{Ί of} the input-side bridge _branch 6a , whereby the phase link voltage u _{CA is} clamped to the input voltage U _in .

If this voltage setpoint u _B * lies above the input voltage U, _n , then in the sense of a step-up converter function, the pulse duty factor d _A <1, ie the bridge branch B _{A on} the input side is clocked at high frequency. The duty cycle d _B, however, due to the limitation of the voltage command value u _B * to a maximum value equal to the actual value of the DC input voltage U _in this case is equal to one, ie, the upper transistor T ₃ of the output bridge arm B _a is connected through constant and the phase of the intermediate circuit voltage u _CA is carried out in accordance with the voltage setpoint u _B *, which, apart from the inductance voltage drop u _L ß, corresponds to the phase converter output voltage u _an *. The limitation of the voltage setpoint Ub * above U, _n for the calculation of d _A and below U, _n for the calculation of dß, i.e. the limitation of the duty cycles d _A and dß to values between zero and one, thus concludes a simultaneous high-frequency switching of both Bridge branches, which is characterized by a higher efficiency compared to the prior art.

It should be noted that in the embodiment of the control mentioned, the voltage at the phase link capacitor and the current in the input inductor are not controlled and the control structure is thus characterized by its simplicity and small number of measurement variables. In applications with high demands on the control dynamics and the possibility of actively dampening any vibrations that occur in the input-side inductance current or the phase link voltage, the control structure mentioned can be expanded by a phase link voltage regulator and an input-side inductance current controller, whereby only the two additional controllers are only used for the calculation during the step-up converter operation of the duty cycle d _A can be used, but the calculation of the duty cycle dß remains unchanged (see Fig. 6). The voltage setpoint ub *, which corresponds to the phase link voltage setpoint uc _A * in step-up converter operation, is compared with the measured value of the phase link voltage uc _A and the control deviation Auc _{A is} fed to a phase converter intermediate circuit voltage controller Ru _ca. The phase intermediate circuit capacitor current setpoint i _CA * required for the correction of Au _ca is then formed at its output, to which the reference current i _LB * of the output-side phase converter inductance Zb converted to the intermediate circuit with the pulse duty factor d _{B is added} by pilot control and thus the required average current through the upper switch Τ _{Ί of} the first bridge _branch Sa results. This current value multiplied by the reference intermediate circuit voltage Uc _A * corresponds to the power to be supplied by the step-up converter, which determines the reference current i _LA * in the input-side phase converter inductance L _A by division by the input voltage value U, _n . By comparing i _LA * with the measured actual value i _LA , the control deviation AI _{la of} the current in L _{A is then} formed and fed to a phase inductance current controller Ri _LA , which has at its output the setpoint u _LA * required for correcting the control deviation AI _{la A} forms the voltage to be applied. Adding the input voltage value U, _n to the controller output setpoint Ui_ _A * results in the voltage u _A * to be applied to switching point A on average over a switching period. The duty cycle d _A is now determined by dividing the voltage u _A * by the phase link voltage setpoint Uc _A *.

In applications with electrochemical storage, fuel cells (drive technology or UPS) or solar cells (photovoltaics), the input DC voltage level has a strongly fluctuating terminal voltage due to the state of charge or the temperature dependence of the characteristic curve, which typically decreases continuously with higher power output. In contrast, in many drive applications the speed and thus the motor voltage typically increase with increasing output power. As a result of this opposite tendency of the falling input voltage and rising output voltage, the converter must be operated for longer and longer in step-up converter operation, ie with higher blocking voltages and thus also higher switching losses. In order to restrict the step-up converter operation required, which is rather unfavorable and therefore lossy at high transmission ratios, to a shorter duration, the circuit according to FIG. 2 is expanded by a third bridge branch B _c with switching point C, parallel to the two bridge branches B _A and B _b ( see Fig. 7). Assuming a three-phase machine with an open winding, i.e. accessibility of the beginnings and ends of each machine phase winding, the beginning of each machine phase winding is still routed to the associated phase output terminal a, b or c, but the end of the corresponding machine phase winding is connected to switching point C of the respective phase module. Advantageously, compared to the phase output voltages u _an , Ubn and u _cn compared to the reference potential n, it is now possible

CH 715 005 A2 see phase output terminals a, b and c and switching point C a sinusoidal output voltage with double voltage amplitude is generated, i.e. with regard to switching point C positive and negative phase output voltages u _aC , Ubc and u _cC can be generated without the voltage load and thus To increase switching losses of the bridge branches, ie a machine with double motor voltage can be used without changing the required degree of modulation of the step-up and step-down converter.

In contrast, in the circuit of Fig. 2, using the same motor, the phase link voltage would have to be increased by twice what power transistors with double reverse voltage capability, i.e. Switch technology with poorer properties and thus higher switching and control losses. Although the use of a full-bridge circuit in combination with a machine with open windings is known in the literature, in contrast to the prior art, due to the phase modularity, the phase link voltage of each phase converter can be carried out independently of the other phase converters, i.e. in the step-up and step-down mode, only one of the three bridge branches is clocked at high frequency, the other bridge branches being switched through depending on the voltage conditions.

With regard to the timing of the bridge branch B _c after it should be noted that in areas in which a positive load phase voltages u _am * must be generated, the lower switch T _{6 of} the bridge branch B _c is switched on and in areas in which a negative load phase voltages u _am * must be generated, the upper switch T _{5 of} the bridge branch B _{c is switched} through, ie the bridge branch B _c is only switched over at the output frequency, that is to say at the fundamental frequency, depending on the polarity of the load phase voltage (see FIG. 8). In order to achieve a sinusoidal curve of the load phase voltage u _am *, the mean voltage at the switching point B of the bridge arm B _b must also be sinusoidal compared to the voltage at the switching point C of the bridge arm B _c .

In areas in which a positive load phase voltages u _am * is generated and the phase converter output voltage to be generated is below the DC input voltage, the upper switch of the bridge arm B _{A on} the input side is switched through and only the bridge arm B _{b on} the output side is clocked at high frequency and in areas , in which a positive load phase voltage u _am * is also generated and the phase converter output voltage to be generated is above the DC input voltage, on the other hand, the upper switch of the output-side bridge arm B _{b is switched} through and only the input-side bridge arm B _{A is} clocked at high frequency and thus in this case the phase converter intermediate circuit voltage Uca varies. In both cases, however, the high-frequency clocking bridge branch is pulse-width-modulated such that the phase converter output voltage has a sinusoidal shape compared to the switching point C clamped to the reference potential n.

In areas in which a negative load phase voltages u _am * must be generated, the switching point C is clamped to the phase converter intermediate circuit voltage uca. If the phase converter output voltage to be generated is above the negative DC input voltage, the upper switch of the input-side bridge branch 6a is switched through and only the output-side bridge branch B _{b is} clocked at high frequency and is pulse-width modulated such that the phase converter output voltage has a switching point Uca which is connected to the phase converter DC-link circuit voltage Cca having. However, if the phase converter output voltage to be generated is below the negative DC input voltage, the lower switch of the output-side bridge arm B _{b is turned on} and only the input-side bridge arm Sa is clocked at high frequency, ie the phase converter intermediate circuit voltage u _C a varies. In both cases, however, the high-frequency clocking bridge branch is pulse-width-modulated such that the phase converter output voltage has a sinusoidal curve compared to the switching point C clamped on the phase converter intermediate circuit voltage Uca.

It should be noted that at the zero crossing of the load phase voltage u _am *, ie the change from a positive to a negative or vice versa a positive to a negative load phase voltage, the switching point C from the reference potential n to the phase converter intermediate circuit voltage u _C a or vice versa from the phase converter intermediate circuit voltage Uca is switched to the reference potential n and, accordingly, in order to achieve a sinusoidal shape of the load phase voltage u _am , the phase converter output voltage with the switching point C must also be switched from the reference potential n to the phase converter intermediate circuit voltage Uca or vice versa from the phase converter intermediate circuit voltage uca to the reference potential n, ie the phase output capacitor C _B must be quickly recharged. In addition to possible distortions in the course of the load phase voltage, this switchover of both bridge branches at the output results in a common mode deflection and thus in common mode disturbances on the machine or load. With regard to the implementation of the phase converter, it should therefore be noted that in addition to the embodiment described above in embodiments, • both bridge branch outputs, ie the switching point B of the bridge branch B _b and the

Switching point C of the bridge branch B _c , are filtered or, in the simplest case, no output is filtered, ie the load is hung directly between the switching points B and C.

• Furthermore, there is the possibility of clocking the base frequency clocking bridge branch B _c around the zero crossing of the load phase voltage u _am , also at high frequency, and instead of switching directly between reference potential n and phase converter intermediate circuit voltage u _C a, continuously switching the voltage at switching point C over a switching period to change. The course of the averaged over a switching period

CH 715 005 A2

The voltage at switching point B must be changed in such a way that a sinusoidal curve of the load phase voltage u _{am is also} achieved.

Instead of the extension with a third bridge branch B _c , the circuit according to FIG. 2 can also be extended with two bridge branches B _d and B _e , both of which are connected as a full bridge between the positive and negative terminals of the phase output capacitor Cb (see FIG . 9). Again, starting from a three-phase machine with an open winding, the beginnings and ends of each machine phase winding are now connected to the switching points D and E of the two additional bridge branches B _D and B _E , unless a further output filter is provided, that is, the switching point D is provided one missing output filter to the associated phase output terminal a, b or c and connected to the respective start of the machine phase winding and the end of the corresponding machine phase winding connected to the switching point E of the respective phase module. A sinusoidal output voltage with twice the voltage amplitude can now advantageously be generated again, that is, with respect to the switching point E, positive and negative phase output voltages u _a E, U _bB and U _c e can be generated without increasing the voltage load and thus the switching losses of the bridge branches, ie it a machine with double motor voltage can be used without changing the required degree of modulation of the step-up and step-down converter. Furthermore, the circuit with two additional bridge branches B _D and B _E (see FIG. 9), compared to the circuit with an additional bridge branch B _c (see FIG. 7), has the advantage of a sinusoidal common-mode voltage curve which, on the one hand, involves switching the bridge branches B _D and B _E and the course of the phase output capacitor voltage ucb simplified and, on the other hand, thus reducing the common mode interference emission.

With regard to the timing of the bridge branches B _D and B _E , it should be noted that in areas in which a positive load phase voltage u _am * must be generated, the upper switch T7 of the bridge branch B _D and the lower switch T-iodes bridge branch B _E are switched through and in areas in which a negative load phase voltage u _am * must be generated, the lower switch T _{8 of} the bridge branch B _D and the upper switch T _{9 of} the bridge branch B _{E are switched} through, that is to say the bridge branches B _D and B _E in turn only with the output frequency, i.e. fundamental frequency, depending on the polarity of the load phase voltage (see Fig. 10). In order to achieve a sinusoidal profile of the load phase voltage u _am *, the profile of the phase output capacitor voltage u _{cb is} sine-shaped to the load phase voltage u _am *, u _cb = I u _am * I. Analogous to the clocking of the circuit according to FIG. 2, in areas in which the phase output capacitor voltage Ucb to be generated is below the DC input voltage, the upper switch of the bridge arm B _{A on} the input side is switched through and only the bridge arm B _{b on} the output side is clocked at high frequency and in areas that phase output capacitor voltage to be generated u _C b is above the DC input voltage, the upper switch of the output-side bridge arm B _{b is switched} through and only the input-side bridge arm B _{A is} clocked at high frequency. At any point in time, due to the phase modularity, only one bridge branch needs to be clocked at high frequency, which leads to reduced switching losses and thus higher efficiency compared to the prior art.

With regard to the implementation of the phase converter, it should also be noted that in addition to the embodiment described above in embodiments, • both bridge branch outputs, ie the switching point D of the bridge branch B _D and the

Switching point E of the bridge branch B _E , can also be filtered.

• Furthermore, there is also the possibility of clocking the fundamental frequency clocking bridge branches B _D and B _E by the zero crossing of the load phase voltage u _am , also at high frequency, so that the profile of the phase output capacitor voltage Ucb can deviate from the sinusoidal load phase voltage profile and thus a simpler regulation of the phase output capacitor voltage u _C b can be achieved. Overall, however, the course of the load phase voltage u _am remains sinusoidal.

In general, it should be noted that all circuit variants also as three-phase rectifiers, i.e. with reverse power flow, can be used.

Claims (10)

claims 1.Converter for the transmission of electrical energy between a direct voltage (DC) system and an alternating voltage (AC) system, comprising a positive DC input voltage rail (1) and a negative DC input voltage rail (2) and at least two on the DC voltage side Output phase connections (a, b, c), wherein for each of the output phase connections (a, b, c) there is a phase converter which is connected on a first side to the positive DC input voltage rail (1) and the negative DC input voltage rail (2) and a second side is connected to this output phase connection (a; b; c) and is designed as a step-up / step-down converter with a voltage intermediate circuit, the converter having a controller which is designed to operate each of the phase converters as a function of a ratio during operation of the converter a DC input voltage for instantaneous values of at the output phase connections (a, b, c) CH 715 005 A2 output phase voltages to be generated, temporarily operated either as a pure step-down converter or as a pure step-up converter. 2. Converter according to claim 1, wherein the control is designed to temporarily limit the clocking of switches of the phase converter to an input-side step-up converter part or bridge branch or to an output-side step-down converter part or bridge branch of the phase converter in the operation of the converter in each of the phase converters. 3. Converter according to claim 1 or 2, wherein the control is designed to carry out the clocking of all phase converters during operation of the converter such that the same clock frequency is present for all phase converters and synchronization of the clocking of the converters minimizes a push-pull voltage component contained in the output phase voltages. 4. Converter according to claim 1 or 2, wherein the control is designed to carry out the clocking of all phase converters during operation of the converter such that the same clock frequency is present for all phase converters and synchronization of the clocking of the converters minimizes a common-mode voltage component contained in the output phase voltages. 5. Converter according to one of the preceding claims, wherein the control is designed to specify an offset during operation of the converter to form output phase voltage setpoints from load phase voltage setpoints, such that in each case in a time period for the phase converter whose assigned load phase voltage setpoint has the highest negative value, this results in an output phase voltage setpoint equal to zero, with which this phase converter does not have to be clocked and its output phase connection (a; b; c) can remain clamped to a reference voltage rail (s), and the course of the output phase voltage setpoints of non-clamped phase converters due to the clamped output and phase connection by subtracting two load phase voltage setpoints in this time period, setpoint values of load outer conductor voltages are defined, so that overall a sinusoidal profile of all the loads external conductor voltages are present. 6. Converter according to one of claims 1 to 4, wherein the control is designed to choose a constant offset of the output phase voltages so large in the operation of the converter with relatively small amplitudes of the output phase voltages that, on the one hand, a fluctuation in the output phase voltages caused by load phase voltages to be generated comes symmetrically to a level of the DC input voltage, and on the other hand does not exceed twice the maximum amplitude of load phase voltages, this being achieved by lowering the offset at high amplitudes of the load phase voltages. 7. Converter according to claim 6, wherein the control is designed to add in addition to the constant offset a further offset signal, which has an amplitude that varies with three times the output frequency, and thus to superimpose a third harmonic on the output phase voltages. 8. Converter according to one of the preceding claims, wherein the phase converters are each designed as a cascaded up-down converter (boost-buck converter). 9. Converter according to claim 8, in which the phase converters each have two step-down converters connected on the output side to the same voltage intermediate circuit. 10. Converter according to claim 8, in which the phase converters each have two bridge branches with separate switching points (D, E) connected to a voltage intermediate circuit fed by the respective down converter. CH 715 005 A2