CH715005B1 - Device for converting a DC voltage that varies within wide limits into a multi-phase AC voltage with variable frequency and amplitude. - Google Patents

Abstract

A converter according to the invention for the transmission of electrical energy between a direct voltage (DC) system and an alternating voltage (AC) system has a positive DC input voltage rail (1) and a negative DC input voltage rail (2) on the DC voltage side and at least two output phase connections on the AC voltage side (a, b, c). There is a phase converter for each of the output phase connections (a, b, c), which is connected on a first side to the positive DC input voltage rail (1) and the negative DC input voltage rail (2) and on a second side to this output phase connection (a ; b; c) is connected and is designed as a step-up / step-down converter with a voltage intermediate circuit. The converter has a control system which is designed to switch each of the phase converters during operation of the converter as a function of a ratio of a DC input voltage to instantaneous values of output phase voltages to be generated at the output phase connections (a, b, c), temporarily either as a pure step-down converter or to operate as a pure step-up converter.

Description

In drive technology there is often the task of feeding a three-phase machine starting from a DC voltage source (battery storage or fuel cell), the three-phase voltage to be applied to the machine having a predetermined amplitude and frequency through a higher-level speed or position control. For stationary operation, both amplitude and frequency typically show an approximately proportional dependence on the machine speed, i.e. they are variable within wide limits. Furthermore, the feeding direct voltage can have a relatively wide range of variation depending on the state of charge of the battery or due to a voltage drop across the internal resistance of the battery or the fuel cell.

According to the state of the art, the DC voltage source is therefore followed by a DC / DC step-up converter, which generates a constant DC output voltage (intermediate circuit voltage) from which a subsequent three-phase pulse inverter stage is fed, which generates pulse-width-modulated output voltages, which may be passed through a subsequent LC low-pass filter can be smoothed to a sinusoidal output voltage curve (see Fig. 1). The level of the intermediate circuit voltage is in principle always above the level of the supplying direct voltage and is selected so large that the three-phase output voltage can be generated with the required amplitude.

A disadvantage of this solution is that both the DC / DC step-up converter and the three-phase pulse inverter convert the entire power, ie there is a two-stage power conversion between the DC voltage source and the machine, which means that correspondingly high control and switching losses occur or a relatively low one Efficiency of energy conversion results.

It should be noted that the converter structure described is also used when reversing the direction of energy, i.e. for applications in which, starting from a three-phase network voltage, a DC voltage that fluctuates over a wide range must be generated, as is the case, for example, when charging electric vehicles can. The DC / DC step-up converter then works as a DC / DC step-down converter due to the reversed direction of energy when viewed from the intermediate circuit voltage and regulates the power or current flow from the intermediate circuit into the battery. In this case, the three-phase AC / DC converter acts as an active rectifier and ensures a sinusoidal curve for the currents drawn from the network and a constant value of the intermediate circuit voltage.

The object of the invention is therefore to create a device with an associated modulation and control method which, with an overlapping input and output voltage range, converts the power offered by a DC voltage source into a three-phase AC voltage with a predetermined frequency and amplitude, but with lower conduction and switching losses or with increased efficiency of energy conversion.

This object is achieved by a converter for the transmission of electrical energy between a DC and an AC system according to the claims. In it, a high-frequency clock for forming takes place in only one stage.

The converter for power electronic energy conversion is to be designed in a phase-modular manner and each phase module is designed in two stages, i.e. with an input-side DC / DC boost converter (phase boost converter) and an output-side DC / DC buck converter (phase buck converter). Starting from the input DC voltage, the phase step-up converter then generates a phase intermediate circuit voltage supported by a phase intermediate circuit capacitor, the negative terminal of which is connected to the negative input voltage terminal. From this phase intermediate circuit voltage, the phase step-down converter generates a phase terminal voltage that is again related to the negative input DC voltage rail and is applied to the associated phase terminal of the three-phase machine. Since, due to the typically isolated or free star point of the fed three-phase machine, only the differences in the phase terminal voltages or only the zero-magnitude or common-mode components, i.e. only the push-pull components of the phase terminal voltages (machine phase voltages) determine the machine phase current curve, the phase terminals can thus despite unipolarity or DC nature a sinusoidal course of the machine phase currents can be impressed. Alternatively, the positive input voltage rail can also be used as a reference potential for the phase intermediate circuit voltage and the phase terminal voltage, the positive terminal of the phase intermediate circuit capacitor then being connected to the positive input voltage rail.

Although the circuit described above has two conversion stages in each phase, ie a step-up / step-down converter structure, in contrast to the conventional system, due to the separation into phase modules, each phase intermediate circuit voltage can be independent of the other phase intermediate circuit voltages and depending on the phase terminal voltage to be generated can be selected, ie the intermediate circuit voltage level is not the same for all phases and is also not determined by the phase with the highest voltage requirement. The respective phase intermediate circuit voltage is now advantageously managed in such a way that only one of the two stages, i.e. either only the phase boost converter or only the phase buck converter, is clocked and the other stage remains switched on during this time, i.e. only one of the two switching stages of a phase module occurs Switching losses or, in this sense, there is a single-stage high-frequency voltage conversion. The switching losses of the phase modules thus advantageously have a minimal value, i.e. a lower value than for an implementation according to the prior art, in the ideal case.

The converter thus has a control which is designed to temporarily either as a pure buck converter or as a pure boost converter to each of the phase converters when the converter is in operation, depending on a ratio of a DC input voltage to instantaneous values of output phase voltages to be generated at the output phase connections operate. The phase converters are therefore designed as multi-loop regulated step-down DC / DC converters, the setpoints of the phase converter output voltages being specified in such a way that, on the one hand, a minimum maximum value of the output voltages is required and, on the other hand, a minimal fluctuation of the currents in the inductances of the phase converters results. In this way, with a given switching frequency, small inductance values can be selected for the implementation of the converter and with given inductance values, small switching frequencies can be selected, or low switching losses can occur.

In embodiments, the control is designed to temporarily limit the clocking of switches of the phase converter to an input-side step-up converter part or bridge branch or to an output-side step-down converter part or bridge branch of the phase converter during operation of the converter in each of the phase converters.

In embodiments, the control is designed to make the clocking of all phase converters during operation of the converter in such a way that the same clock frequency is present for all phase converters and a synchronization of the clocking of the converter minimizes a push-pull voltage component contained in the output phase voltages.

In embodiments, the control is designed to make the clocking of all phase converters during operation of the converter in such a way that the same clock frequency is present for all phase converters and a synchronization of the clocking of the converter minimizes a common-mode voltage component contained in the output phase voltages.

In embodiments, the control is designed to specify an offset for the formation of output phase voltage setpoints from load phase voltage setpoints when the converter is in operation, so that in each case in a time segment for that phase converter whose assigned load phase voltage setpoint has the highest negative value, an output phase voltage setpoint results equal to zero this phase converter does not have to be clocked and its output phase connection can remain clamped to a reference voltage rail, and the course of the output phase voltage setpoints of non-clamped phase converters is defined by load output values to be generated in relation to the clamped output phase connection and by subtraction of two load phase voltage setpoints in this time segment overall there is again a sinusoidal curve for all load line voltages.

In embodiments, the phase converters are each designed as cascaded up / down converters (boost buck converters).

In embodiments, the control is designed to select a constant offset of the output phase voltages so large in an operating mode of the converter which is suitable for relatively small amplitudes of the output phase voltages that, on the one hand, a fluctuation in the output phase voltages caused by the load phase voltages to be generated symmetrically around a Level of the DC input voltage comes to lie, and on the other hand, a double maximum amplitude of load phase voltages is not exceeded, this being achieved by lowering the offset at high amplitudes of the load phase voltages.

In embodiments, one or more of the following features are implemented: The control is designed to add an offset signal which has a value that varies with three times the output frequency, i.e. an offset with a 3rd harmonic, with an amplitude and phase position such that a larger output voltage amplitude can be achieved. No output filter is provided, i.e. the connection point (s) are directly connected to the motor terminals. A third branch of the bridge is arranged on the phase intermediate circuit capacitor and thus a double output voltage amplitude is made possible without increasing the intermediate circuit voltage and blocking voltage capability of the semiconductors. A third and fourth bridge arm are arranged on the phase output capacitor and thus a double output voltage amplitude is possible without increasing the intermediate circuit voltage and blocking voltage capability of the semiconductors, and in addition a sinusoidal common-mode voltage is generated at the output, which has a better EMC behavior.

In the following, the subject matter of the invention is explained in more detail on the basis of preferred exemplary embodiments which are illustrated in the accompanying drawings. They show schematically in each case: Furthermore, an output low-pass filter is provided for smoothing the pulse-width-modulated output voltages of the pulse-controlled inverter stage, with the result that the machine terminal voltages show an approximately sinusoidal curve. Fig. 2: Circuit structure of a phase-modular DC / AC converter with step-up / step-down function. The low-pass filtered voltages generated at the phase outputs are related to the negative input voltage rail 2. The arrangement requires an isolated machine star point. Fig.3: Time curve of the phase converter output voltages to be generated when a three-phase machine is supplied for (Fig.3.1) temporally constant offset shift uoff of the load phase voltage system actually to be generated in the amount of the amplitude of the load phase voltage; (Fig.3.2) with constant offset shift and additional superimposition of an alternating component of the offset signal three times the output frequency and a phase position such that the maximum value of the phase converter output voltages is minimized; (Fig. 3.3) with offset shifting of the load phase voltage system to be generated in such a way that a setpoint value equal to zero is present for a phase converter output over a third of the output period, and this converter therefore remains in the clamped state can, so is not clocked. Fig. 4: Time curve of the setpoints of the phase converter output voltages uan, ubn and ucn for the converter circuits according to Fig. 2, which can be used when the setpoints of the load phase voltages are small compared to the DC input voltage Uin, in order to minimize the switching frequency fluctuations of the current LA in the phase converter inductances . Fig. 5: Device for regulating the output voltages of the phase converters in order to set a predetermined curve, etc. * of the load phase voltages, as is required for UPS systems or when supplying variable-speed three-phase machines. The regulation has the same structure for each phase and is only shown for one phase for reasons of clarity. Fig. 6: Modification of part of the control devices according to Fig. 5, d. H. The device for regulating the output voltages is expanded to include an intermediate circuit voltage and input current regulator in order to achieve higher control dynamics and to actively dampen any oscillations in the system. Fig. 7: Alternative versions of the power section when using a three-phase machine with open winding, i.e. with access to the beginnings and ends of each machine phase winding, the circuit of a phase module according to Fig. 2 being extended by a third bridge branch BC with switching point C, parallel to the two bridge branches BA and BB. Fig. 8: (a) Time curve of the phase converter output voltages uaC, ubC and ucC for the converter circuits according to Fig. 7, (b) the voltage at node C of the bridge arm BC and the phase intermediate circuit capacitor voltage UCA, (c) the two duty cycles dA and dB and (d) the switching states of the individual Bridge branches over an output period, the hatched area representing the high-frequency switching of the corresponding bridge branch. Fig. 9: Alternative versions of the power section when using a three-phase machine with open winding, i.e. with access to the beginnings and ends of each machine phase winding, whereby the circuit of a phase module according to Fig. 2 is extended by a third and fourth bridge branch BD and BE with the connection points D and E. Fig. 10: (a) Time curve of the phase converter output voltages UaE, ubE and ucE for the converter circuits according to Fig. 9, (b) the voltage at the circuit points D and E as well as the phase intermediate circuit capacitor voltage uCA, (c) the two duty cycles dA and dB and (d) the switching states of the individual bridge branches over an output period, whereby the hatched area represents the high-frequency switching of the corresponding bridge branch.

According to Fig.2, each phase converter of the system input side has a first inductance LAauf, the first connection of which is connected to the positive DC input voltage rail 1 and the second connection to the node A of a first bridge arm BA, ie to the common connection point of the lower emitter or source connection an upper switch T1 and the upper collector or drain connection of a lower switch T2. Furthermore, the outer connections of the first bridge arm BA are connected to a phase intermediate circuit capacitor CA, ie the collector or drain connection of the upper switch T1 is connected to the positive terminal of the phase intermediate circuit capacitor CA and the emitter or source connection of the lower switch T2 to the negative terminal of the phase intermediate circuit capacitor the negative DC input voltage rail 2 is connected. The phase intermediate circuit capacitor C thus supports the generated phase intermediate circuit voltage uCA against the negative input voltage rail 2. A bridge branch is generally implemented with power transistors, a freewheeling diode being connected in antiparallel to both transistors. Likewise, a second bridge arm BB with an upper switch T3 and a lower switch T4, parallel to the first bridge arm BA, is connected between the positive and negative terminal of the phase intermediate circuit capacitor CA, whose circuit point B is connected to a first connection of a second inductance LB and whose second connection is connected to the positive one Terminal of a phase output capacitor CB necessary for smoothing the output voltage uCB, to which the assigned output phase terminal a, b or c also branches off. The negative terminal of a phase output capacitor CB is connected to the negative input voltage rail 2, i.e. the reference voltage rail n, and thus supports the generated phase terminal voltage uan, ubn or ucnab. In relation to the common reference voltage rail n, each phase converter has the structure of a step-up converter DC / DC converter whose phase intermediate circuit voltage uCA can be routed depending on the ratio of input voltage Uin and the assigned phase output voltage uan, ubn or ucn, but independently of the other phases.

A three-phase load is switched with its phase terminals to the output phase terminals a, b and c of the three phase converters and has a free star point m, so that only the chained phase converter output voltages (load outer conductor voltages), defined as the difference between two phase converter output voltages or that of a load output terminal in opposite directions a load star point measured load phase voltage etc., ubmund ucm determine the formation of the load phase currents.

The phase converter output voltagesuan, ubn and ucn are generated, for example, in such a way that the setpoint values of the load phase voltages, etc., which are typically sinusoidal with an output frequency and form a symmetrical three-phase system, ub and ucm by means of an in the simplest case time-constant offset suoffderart a unipolar curve to positive values, that is, shifted each phase output only shows positive values or minimally the value zero (see Fig. 3.1). As mentioned above, this offset is not effective in the load line voltages and therefore has no influence on the current generation of the load. In embodiments, a further offset with three times the output frequency and an amplitude and phase can be added to this constant offset in such a way that the unipolarity of the output phase voltages is ensured with a minimum value of the constant offset, whereby the voltage load on the transistors of both bridge branches BA and BB of the phase converter with a defined load phase voltage amplitude to be generated is minimized can be (see Fig. 3.2).

With regard to the clocking of the input and output-side bridge arms BA and BB of the phase converters, it should be noted that in areas in which a phase converter output voltage above the DC input voltage must be generated, the upper switch or power transistor T3 of the output-side bridge arm B, and only the remaining phase converter can be switched through Bridge branch BA is clocked. For power flow from the DC input voltage to the phase converter output voltage, the voltage translation of the converter then corresponds to that of a step-up converter, with the input-side phase converter inductance LA as step-up converter inductance, the lower power transistor T2 of the input-side bridge arm BA as a step-up converter transistor, with the anti-parallel diode of the high-voltage converter always acting as a step-up transistor the upper power transistor T1 is switched through, ie the power transistors of the input-side bridge arm BA are operated in push-pull mode. Since diodes are arranged in anti-parallel to all power transistors, power can then flow from the phase converter output voltage to the DC input voltage, the function of the phase converter in this case corresponding to that of a step-down converter located between the phase converter output voltage and the DC input voltage.

In areas in which a phase converter output voltage lying below the DC input voltage must be generated, in embodiments the upper power transistor T1 of the input-side bridge arm BAd of the phase converter remains switched on, and the clocking is limited to the output-side bridge arm BB. For power flow from the DC input voltage to the phase converter output voltage, the voltage translation of the converter then corresponds to that of a buck converter, the output-side phase converter inductance LB as the buck converter inductance, the upper power transistor T3 of the output-side bridge arm BB as a buck converter transistor and the diode connected to the lower power converter transistor the lower power transistor T4 is also switched through, ie the power transistors of the output-side bridge arm BB are operated in push-pull mode. Since diodes are arranged in anti-parallel to all power transistors, a power flow can then also take place from the phase converter output voltage into the DC input voltage, the function of the phase converter in this case corresponding to that of a step-up converter located between the phase converter output voltage and the DC input voltage.

With regard to the clocking of all phase converters, it should be noted that, in embodiments, the same clock frequency can be selected for all phase converters and the clocking of the converter can be synchronized in such a way that the counter-clock voltage component contained in the phase converter output voltages, which is to switch-frequency currents and thus possibly to high-frequency losses in the connected three-phase load, is minimized, ie switching frequency changes in the phase converter output voltages are mainly formed as common-mode components, which cause a voltage shift of the same type relative to the reference voltage rail for all phase outputs.

For consumers who are particularly sensitive to high-frequency common-mode shifts, on the other hand, the phase converters, which in this case also operate with the same clock frequency, can be synchronized in such a way that the switching-frequency common-mode voltage components are minimized, although a higher differential-mode component of the phase converter output voltages must then be accepted .

An alternative course of the offset in Fig.3.1 and Fig.3.2 is defined in such a way that an output phase voltage setpoint equal to zero results for that phase converter whose assigned load phase voltage has the highest negative value (see Fig.3.3), with which this phase converter does not have to be clocked, or the associated output phase terminal can remain clamped to the reference voltage rail, which can be achieved for the phase converter topology described above (see Fig. 2) simply by switching through the lower power transistor T4 of the output-side bridge arm BB. The course of the output voltage setpoints of the two other phase converters is then defined directly by the sections of the setpoints of the load external conductor voltages to be generated with respect to the clamped phase and to be formed by subtracting two load phase voltage setpoints each, so that overall a sinusoidal profile of all three load external conductor voltages is achieved again. Since the clamping takes place cyclically between one phase after the other, each phase remains clamped for a third of the load phase voltage system when generating a sinusoidal symmetrical load phase voltage system and thus without switching losses, which increases the efficiency of the energy transmission.

For use of the system for supplying a three-phase machine (load) lying at the output phase terminals, different amplitudes of the load phase voltage or different amplitudes of the assigned phase converter output voltages are to be generated depending on the speed of the machine, with the highest amplitude values typically occurring at the highest speed for which the power semiconductors of both bridge branches are to be designed.

Advantageously, at low speeds or relatively small amplitudes of the phase converter output voltages, the constant offset can be chosen so large that on the one hand the fluctuation of the phase converter output voltages caused by the load phase voltages to be generated comes to lie symmetrically around the level of the DC input voltage and on the other hand that of the maximum Speed associated with twice the maximum amplitude of the load phase voltage is not exceeded, this being achieved by a corresponding lowering of the offset at high amplitudes of the load phase voltages. As shown in Fig. 4, the nominal values of the phase converter output voltages then typically have minimum values that are significantly greater than zero and the currents in the phase converter inductances show a relatively low ripple, since the input and output bridge branches then alternately work with duty cycles close to one (i.e. the respective upper power transistors are switched through almost constantly) which is known to result in a low switching frequency fluctuation of the current in the phase converter inductances, which in turn is expressed in low high-frequency losses. Even taking into account the higher switching losses in both bridge branches due to the higher switched phase converter output voltage, the efficiency of the energy transmission can be improved.

With regard to the implementation of the phase converter, it should be noted that in addition to the embodiment described above, there are a number of advantageous modifications: In embodiments, the input and / or output-side bridge branch can advantageously be implemented in a multilevel structure, so for example as a flying capacitor multilevel bridge branch, which is used for setting the Voltage translation between the DC input voltage and the phase converter output voltage, a higher number of voltage levels is available, which means that there is less switching frequency ripple of the currents in the phase inductances. • Furthermore, in embodiments, the phase converters can be implemented by several parallel, phase-shifted clocked systems, so that the current fed into the output capacitance and the current drawn from the DC input voltage advantageously has a higher effective frequency and a smaller fluctuation compared to a single system. • Analogous to the system according to the state of the art, in the simplest case the LC output filter of the phase converter, consisting of the output phase converter inductance LB and the phase output capacitor CB, can be omitted, ie the circuit point B of the second bridge arm BB directly forms the phase output a, b or c and thus the three-phase pulse width modulated voltage system is applied directly to the motor terminals.

A possible embodiment of a cascaded regulation of the phase modular converter system is shown in FIG. The control circuit is of the same type for each phase and, for the sake of clarity, is only shown for one phase. As entered, voltages are measured with respect to the reference voltage rail n or the negative DC input voltage rail 2.

The setpoint of a phase converter output voltage uan * is formed by adding the typically sinusoidal setpoint uam * the associated load phase voltage uamein fed three-phase load (e.g. an electrical machine M) and the setpoint uoff * of the offset uoff, which is the same for all phases, which is typically formed by adding a over the output period constant component uoff, DC * and a component uoff, AC * fluctuating at three times the output frequency. Advantageously, the time curve of uoff * is chosen in such a way that uan * for a given load phase voltage system uam * remains limited to the lowest possible values, which also minimizes the blocking voltage stress and the switching losses in both bridge branches of the phase converters. This includes a specification of uoff * such that a phase converter remains in the clamped state for a third of the output period, i.e. uan * has correspondingly wide intervals with uan * = 0. The phase converter output voltage setpoint uan * is compared with the measured actual value uan the phase converter output voltage and the control deviation Δuan * is fed to a phase converter output voltage regulator Ruan, at whose output the output capacitor current setpoint iCB * required to correct Δuan *, the reference phase current iCB * measured, which is formed by a precontrol of the measured load current iCB * * determined in the phase converter inductance LB on the output side. By comparing iLB * with the measured actual value iLB, the system deviation ΔiLB of the current in LB is then formed and fed to a phase inductance current controller RiLB, which at its output forms the setpoint uLB * of the voltage to be applied to LB, which is required to correct the system deviation ΔiLB. By adding the phase converter output voltage setpoint uan * to the controller output setpoint uLB *, the average voltage uB * to be applied to circuit point B over a switching period results. If this voltage setpoint uB * is below the input voltage Uin, the duty cycle dB, i.e. the relative switch-on time of the upper transistor T3 of BB, is calculated in the sense of a buck converter function by dividing the voltage setpoint uB * by the actual value of the DC input voltage Uin, i.e. dB <1 and thus the output-side bridge arm BB is clocked at high frequency in accordance with the pulse width modulation. The duty cycle dA, i.e. the relative switch-on duration of the upper transistor T1 of BA, is calculated in reverse by dividing the actual value of the DC input voltage Uind by the voltage setpoint uB *, with the voltage setpoint uB * beforehand. is limited to a minimum value equal to the actual value of the DC input voltage Uin and in this case leads to a pulse duty factor dA = 1 with uB * <Uin, i.e. corresponding to constant switching of the upper transistor T1 of the input-side bridge arm BA, whereby the phase intermediate circuit voltage uCA is clamped to the input voltage U.

If this voltage setpoint uB * is above the input voltage Uin, the pulse duty factor dA <1 in the sense of a step-up converter function, i.e. the bridge arm BA on the input side is clocked at high frequency. However, due to the limitation of the voltage setpoint uB * to a maximum value equal to the actual value of the DC input voltage Uin, the pulse duty factor dB is in this case equal to one, i.e. the upper transistor T3 of the output-side bridge arm BA is constantly switched on and the phase intermediate circuit voltage uCA is guided according to the voltage setpoint uB * apart from the inductance voltage drop uLB corresponds to the phase converter output voltage uan *. The limitation of the voltage setpoint uB * above Uin for the calculation of dA and below Uin for the calculation of dB, i.e. the limitation of the duty cycle dA and dB to values between zero and one, thus excludes simultaneous high-frequency switching of both bridge branches, which is different compared to the prior art in a higher efficiency.

It should be noted that in the mentioned embodiment of the control, the voltage at the phase link capacitor and the current in the input inductance are not controlled and thus the control structure is characterized by its simplicity and low number of measured variables. In applications with high demands on the control dynamics as well as the possibility to actively dampen any oscillations in the input-side inductance current or the phase intermediate circuit voltage, the control structure mentioned can be extended by a phase intermediate circuit voltage regulator and an input-side inductive current regulator, whereby only the two additional regulators are only used during the step-up converter operation of the duty cycle dA can be used, but the calculation of the duty cycle dB remains unchanged (see FIG. 6). The voltage setpoint uB *, which in step-up converter operation corresponds to the phase link voltage setpoint uCA *, is compared with the measured value of the phase link voltage uCA and the control deviation ΔuCA is fed to a phase converter link voltage regulator RuCA. At its output, the phase intermediate circuit capacitor current setpoint iCA * required to correct ΔuCA is then formed, to which the reference current iLB * of the output-side phase converter inductance LB, which is converted with the duty cycle dB to the intermediate circuit, is added through precontrol, thus adding the required average current through the upper switch T1 of the first bridge branch . This current value multiplied by the reference intermediate circuit voltage uCA * corresponds to the power to be supplied by the step-up converter, which determines the reference current iLA * in the input-side phase converter inductance LA by dividing it by the input voltage value U. By comparing iLA * with the measured actual value iLA, the control deviation ΔiLA of the current in LA is then formed and fed to a phase inductance current controller RiLA, which at its output forms the setpoint uLA * of the voltage to be applied to LA, which is required to correct the control deviation ΔiLA. By adding the input voltage value Uinz to the controller output setpoint uLA *, the average voltage uA * to be applied to switching point A over a switching period results. The pulse duty factor dA is now determined by dividing the voltage uA * by the phase intermediate circuit voltage setpoint uCA *.

In applications with electrochemical storage, fuel cells (drive technology or UPS) or solar cells (photovoltaics), the input DC voltage level has a strongly fluctuating terminal voltage depending on the state of charge or the temperature dependency of the characteristic curve, which typically drops continuously with higher power output. In contrast to this, in many drive applications, the speed and thus the motor voltage typically increase as the output power increases. As a result, due to this opposite direction of the falling input voltage and increasing output voltage, the converter has to be operated longer and longer in step-up converter operation, i.e. at higher blocking voltages and thus also higher switching losses. In order to limit the required step-up converter operation, which is rather unfavorable and therefore lossy at high gear ratios, to a shorter duration, the circuit according to Fig. 2 is expanded to include a third bridge branch BC with switching point C, parallel to the two bridge branches BA and BB (see Fig. 7). Assuming a three-phase machine with an open winding, i.e. access to the beginnings and ends of each machine phase winding, the beginning of each machine phase winding is still connected to the associated phase output terminal a, b or c and the end of the corresponding machine phase winding is connected to circuit point C of the respective phase module. In comparison to the phase output voltages uan, ubn and ucn compared to the reference potential n, a sinusoidal output voltage with double voltage amplitude can now be generated between the phase output terminals a, b and c and the circuit point C, i.e. positive and negative phase output voltages uaC, ubC and ucC can be generated with respect to the circuit point C to increase the voltage load and thus the switching losses of the bridge arms, ie a machine with twice the motor voltage can be used without changing the required degree of modulation of the step-up and step-down converter.

In the circuit according to Fig.2, in contrast, when using the same motor, the phase intermediate circuit voltage would have to be increased by twice the value, which would result in power transistors with double blocking voltage capability, i.e. switch technology with poorer properties, and thus higher switching and conduction losses. In the literature, the use of a full bridge circuit in combination with a machine with open windings is known, but in contrast to the prior art, due to the phase modularity, the phase intermediate circuit voltage of each phase converter can largely be conducted independently of the other phase converters, i.e. it is in step-up and step-down mode only one of the three branches of the bridge is clocked at high frequency, with the other branches of the bridge being constantly switched through depending on the voltage conditions.

With regard to the timing of the bridge branch BCnach, it should be noted that in areas in which a positive load phase voltages etc. must be generated, the lower switch T6 of the bridge branch Bc is switched through and in areas in which a negative load phase voltages etc. must be generated, the upper switch T5 of the bridge branch Bc is switched through, ie the bridge arm Bc is only switched at the output frequency, i.e. at the base frequency, depending on the polarity of the load phase voltage (see Fig. 8). In order to achieve a sinusoidal curve of the load phase voltage etc.

In areas in which a positive load phase voltage, etc. * is generated and the phase converter output voltage to be generated is below the DC input voltage, the upper switch of the input-side bridge arm BA is switched through and only the output-side bridge arm BB is clocked at high frequency and in areas in which a positive load phase voltage * is also generated and the phase converter output voltage to be generated is above the DC input voltage, on the other hand the upper switch of the output-side bridge arm BB is switched through and only the input-side bridge arm BA is clocked at high frequency and thus in this case the phase converter intermediate circuit voltage uCA is varied. In both cases, however, the high-frequency clocked bridge branch is pulse-width-modulated in such a way that the phase converter output voltage has a sinusoidal profile compared to the circuit point C clamped to the reference potential n.

In areas in which a negative load phase voltage uam * must be generated, the circuit point C is clamped to the phase converter intermediate circuit voltage uCA. If the phase converter output voltage to be generated is above the negative DC input voltage, the upper switch of the input-side bridge arm BA is switched through and only the output-side bridge arm BB is clocked at high frequency and pulse-width-modulated in such a way that the phase converter output voltage has a sinusoidal circuit voltage UCA connected to the phase converter intermediate circuit. However, if the phase converter output voltage to be generated is below the negative DC input voltage, the lower switch of the output-side bridge arm BB is switched through and only the input-side bridge arm BA is clocked at high frequency, i.e. the phase converter intermediate circuit voltage uCA is varied. In both cases, however, the high-frequency clocked bridge branch is pulse-width-modulated in such a way that the phase converter output voltage has a sinusoidal profile compared to the circuit point C clamped to the phase converter intermediate circuit voltage uCA.

It should be noted that at the zero crossing of the load phase voltage uam *, ie the change from a positive to a negative or vice versa from a positive to a negative load phase voltage, the circuit point C is switched from the reference potential n to the phase converter intermediate circuit voltage uCA or vice versa from the phase converter intermediate circuit voltage uCA to the reference potential n and accordingly, in order to achieve a sinusoidal curve of the load phase voltage and the like, the phase converter output voltage with circuit point C must be switched from reference potential n to phase converter intermediate circuit voltage UCA or vice versa from phase converter intermediate circuit voltage uCA to reference potential n, i.e. the phase output capacitor CB must be switched over quickly. In addition to possible distortions in the course of the load phase voltage, this switchover of both bridge branches at the output results in a common-mode deflection and thus common-mode interference on the machine or load. With regard to the implementation of the phase converter, it should therefore be noted that in addition to the above-described design in embodiments and C is hung. • Furthermore, there is the possibility of clocking the bridge branch Bc, which clocks at a fundamental frequency, around the zero crossing of the load phase voltage, etc., also at high frequency and, instead of switching directly between reference potential n and phase converter intermediate circuit voltage uCA, to continuously change the voltage at circuit point C averaged over a switching period. The curve of the voltage averaged over a switching period at circuit point B must be changed in such a way that a sinusoidal curve of the load phase voltage uam is still achieved.

Instead of expanding with a third bridge arm BC, the circuit according toFig.2 can also be expanded with two bridge arms BD and BE, both of which are connected as a full bridge between the positive and negative terminals of the phase output capacitor CB (seeFig.9). Again starting from a three-phase machine with an open winding, the beginnings and ends of each machine phase winding are now connected to the circuit points D and E of the two additional bridge branches BD and BE, provided that no further output filter is provided, i.e. the circuit point D is linked to the associated phase output terminal a, b or c out and connected to the respective beginning of the machine phase winding and the end of the corresponding machine phase winding is connected to the circuit point E of the respective phase module. A sinusoidal output voltage with double the voltage amplitude can now advantageously be generated again, i.e. positive and negative phase output voltages uaE, ubE and ucE can be generated with respect to the circuit point E without increasing the voltage load and thus the switching losses of the bridge branches, i.e. a machine with double the motor voltage can be used without the required degree of modulation of the step-up and step-down converter. Furthermore, the circuit with two additional bridge branches BD and BE (see Fig. 9) compared to the circuit with an additional bridge branch BC (see Fig. 7) has the advantage of a sinusoidal common-mode voltage curve, on the one hand the switching of the bridge branches BD and BE and the curve of the phase output capacitor voltage uCB and thus on the other hand the common-mode interference emission is reduced.

With regard to the timing of the bridge branches BD and BE, it should be noted that in areas in which a positive load phase voltage uam * has to be generated, the upper switch T7 of the bridge branch BD and the lower switch T10 of the bridge branch BE are switched through and in areas in which a negative load phase voltage uam * has to be generated The lower switch T8 of the bridge arm BD and the upper switch T9 of the bridge arm BE are switched through, that is, the bridge arms BD and BE are only switched at the output frequency, i.e. at the base frequency, depending on the polarity of the load phase voltage (see Fig. 10). In order to achieve a sinusoidal curve of the load phase voltage uam *, the curve of the phase output capacitor voltage uCB is sine-shaped to the load phase voltage uam *, uCB = | uam * |. Analogous to the clocking of the circuit according to Fig. 2, in areas in which the phase output capacitor voltage uCB to be generated is below the DC input voltage, the upper switch of the input-side bridge arm BA is switched through and only the output-side bridge arm BB is clocked at high frequency and in areas in which the DC input capacitor voltage uCB to be generated is above the , the upper switch of the output-side bridge arm BB is switched through and only the input-side bridge arm BA is clocked at high frequency. At any point in time, due to the phase modularity, only one bridge branch has to be clocked at high frequency, which in comparison to the prior art leads to reduced switching losses and thus higher efficiency.

With regard to the implementation of the phase converter, it should also be noted that in addition to the above-described design in embodiments • both bridge branch outputs, i.e. the node D of the bridge branch BD and the Switching point E of the bridge arm BE, can also be filtered. • Furthermore, there is also the possibility of clocking the bridge arms BD and BE, which are clocked at a fundamental frequency, at high frequencies around the zero crossing of the load phase voltage, etc., so that the curve of the phase output capacitor voltage uCB can deviate from the sine-wave load phase voltage curve and thus a simpler regulation of the phase output capacitor voltage uC can be achieved. Overall, however, the curve of the load phase voltage and so on remains sinusoidal.

In general, it should be noted that all circuit variants can also be used as three-phase rectifiers, i.e. with reversed power flow.

Claims (10)

1. Converter for the transmission of electrical energy between a direct voltage or DC system and an alternating voltage or AC system, having on the DC voltage side a positive DC input voltage rail (1) and a negative DC input voltage rail (2) and on the AC voltage side at least two output phase connections (a, b, c), the converter having a phase converter for each of the output phase connections (a, b, c), which on a first side is connected to the positive DC input voltage rail (1) and the negative DC input voltage rail (2) and on a second side is connected to this output phase connection (a; b; c) and is designed as a step-up / step-down converter with a voltage intermediate circuit, the converter having a control system which is designed to operate each of the phase converters, depending on a ratio of one DC input voltage to instantaneous values of at the output phase terminal connections (a, b, c) to be generated output phase voltages, to operate temporarily either as a pure step-down converter or as a pure step-up converter. 2. Converter according to claim 1, wherein the control is designed to temporarily limit the clocking of switches of the phase converter to an input-side step-up converter part or bridge branch or to an output-side step-down converter part or bridge branch of the phase converter when the converter is in operation. 3. Converter according to claim 1 or 2, wherein the control is designed to clock all phase converters when the converter is in operation so that the same clock frequency is present for all clocked phase converters and synchronization of the converter clocking minimizes a push-pull voltage component contained in the output phase voltages. 4. Converter according to claim 1 or 2, wherein the control is designed to make the clocking of all phase converters during operation of the converter in such a way that the same clock frequency is present for all clocked phase converters and a synchronization of the clocking of the converters minimizes a common-mode voltage component contained in the output phase voltages . 5. Converter according to one of the preceding claims, wherein the control is designed to specify an offset for the formation of output phase voltage setpoints from load phase voltage setpoints during operation of the converter, in such a way that in each case in a time segment for that phase converter whose assigned load phase voltage setpoint has the highest negative value, an output phase voltage setpoint value equal to zero results, which means that this phase converter does not have to be clocked and its output phase connection (a; b; c) can remain clamped to a reference voltage rail (s), and the course of the output phase voltage setpoints of non-clamped phase converters by output phases to be generated opposite the clamped output By subtracting two load phase voltage setpoints in each case, setpoint values of load outer conductor voltages formed in this time segment are defined, so that overall a sinusoidal profile of all load outer conductors there is tension. 6. Converter according to one of claims 1 to 4, wherein the control is designed to select a constant offset of the output phase voltages in one mode of operation of the converter so large that on the one hand a fluctuation in the output phase voltages caused by the load phase voltages to be generated symmetrically about one level the DC input voltage comes to rest, and on the other hand a double maximum amplitude of load phase voltages is not exceeded, this being achieved by lowering the offset at high amplitudes of the load phase voltages. 7. Converter according to claim 6, wherein the control is designed to add, in addition to the constant offset, a further offset signal, which has an amplitude that varies with three times the output frequency, and thus to superimpose a third harmonic on the output phase voltages. 8. Converter according to one of the preceding claims, wherein the phase converters are each designed as a cascaded step-up / step-down converter. 9. Converter according to claim 8, in which the phase converters each have two buck converters connected on the output side to the same voltage intermediate circuit. 10. Converter according to claim 8, in which the phase converters each have two bridge branches with separate circuit points (D, E) connected to a voltage intermediate circuit fed by the respective buck converter.