WO2019057771A1

WO2019057771A1 - Ac/dc converter having step-up/step-down converter phase modules

Info

Publication number: WO2019057771A1
Application number: PCT/EP2018/075349
Authority: WO
Inventors: Michael Georg LEIBL; Lukas Franz Josef SCHRITTWIESER; Johann Walter Kolar; Dominik Bortis; Michail Marios ANTIVACHIS
Original assignee: ETH Zürich
Priority date: 2017-09-20
Filing date: 2018-09-19
Publication date: 2019-03-28
Also published as: CH714180A2; CH714180B1

Abstract

The invention relates to a converter for transmitting electrical energy between a direct current voltage (DC) system and an alternating current voltage system, comprising a positive DC input voltage rail (1) and a negative DC input voltage rail (2) on the DC voltage side and at least two output phase connections (a, b, c) on the AC voltage side. For each of the output phase connections (a, b, c) there is a phase converter (10a, 10b, 10c), which is connected to the positive DC input voltage rail (1) and the negative DC input voltage rail (2) on a first side, and to said out put phase connection (a; b; c) on a second side, and is designed as a step-up/step-down converter. The converter has a controller which is designed such that, during the operation of the converter, said controller operates each of the phase converters (10a, 10b, 10c) periodically either purely as a step-down converter or purely as a step-up converter, according to a relationship of a DC input voltage relative to instantaneous values of output phase voltages to be generated at the output phase connections (a, b, c).

Description

AC / DC CONVERTERS WITH HIGH-RESILIENT PHASE MODULES

The power electronic conversion of a DC voltage into a three-phase

AC system (DC / AC conversion) is found industrially e.g. in drive technology, in uninterruptible power supplies (UPS) and in the feeding of photovoltaic energy into the three-phase network wide application.

The input DC voltage level in this case has due to the typically highly dependent on the state of charge terminal voltage electrochemical storage or

Fuel cells (drive technology or UPS) or due to the temperature dependence of the characteristic of solar cells (photovoltaic) a relatively large variation, so that the power electronic converter typically two-stage, i. with a

Input side DC / DC step-up converter, a voltage intermediate circuit and an output side three-phase DC / AC converter (inverter) is executed (see Fig.l). In this way, the inverter, which in the end acts as a step-down converter in the case of power flow from the DC side to the three-phase AC side, can advantageously be designed for operation with a constant intermediate circuit voltage and thus with minimum construction output. Furthermore, by the DC link voltage level higher than the DC input voltage, it is possible to generate a relatively high output voltage, which can be maintained independently of the battery state of charge, or can operate at the point of maximum power delivery regardless of the irradiation intensity and temperature for photovoltaic systems. In drive technology, the high DC link voltage offers the advantage of mastering a wide speed range of a powered AC machine.

Due to the inverter, the intermediate circuit voltage becomes a three-phase

Pulse width modulated voltage system generates and in the realization of a

Variable speed drive in the simplest case, placed directly on the motor terminals.

However, this results in a significant, according to the steep voltage edges

Insulation load of the stator windings of the motor, furthermore, the stator current typically has a high switching-frequency ripple, which can lead to high rotor losses and thus due to the air gap limited cooling to a significant thermal load of the rotor. Furthermore, caused by the switching frequency common mode component of the machine terminal voltages bearing currents, which can lead to a destruction of the raceways of the bearing, to call disadvantageous. The mentioned disadvantages can be achieved by a three-phase LC output filter of the inverter, which switching frequency harmonics of the pulse width modulated

Inverter output phase voltages suppressed and thus ensures a smooth, typically sinusoidal inverter output voltage waveform can be avoided.

For UPS systems, this LC output filter must always be arranged, since the connected AC consumers i.A. must be supplied with a, deviating only slightly from a purely sinusoidal voltage. The same applies to photovoltaic applications, where the LC output filter is the first stage of an EMC filter intended to suppress the propagation of switching-frequency electromagnetic disturbances (currents) into the three-phase network.

In this context, it should be noted that the previously described

Converter structure even with reversal of the energy direction, so for applications in which, starting from a three-phase network voltage within a wide limits

fluctuating DC voltage must be generated, as e.g. in the battery charge of electric vehicles is the case, can be used. The DC / DC step-up converter then works as a DC / DC step-down converter as a result of the reversed energy direction from the intermediate circuit voltage (it is antiparallel to the step-up converter diode for this purpose)

Power transistor and antiparallel to the boost converter power transistor to provide a diode) and regulates the power flow from the intermediate circuit into the battery. The three-phase AC / DC converter acts as an active rectifier in this case and ensures a sinusoidal profile of the currents absorbed by the grid and a constant value of the DC link voltage.

However, the overall system with the inductance of the DC / DC boost converter, the DC link capacitor and arranged in each of the three output phases of the inverter filter inductance and filter capacitance on the whole a high amount of passive components, resulting in a relatively high volume of construction results or relatively high implementation costs Buy are to take. Furthermore, the two-stage energy transformation with regard to high energy efficiency is disadvantageous.

The literature has therefore proposed single-stage DC / AC converters which are formed from three identical bidirectional DC / DC phase converters having a common negative voltage rail and starting from the same DC Supply voltage three sinusoidally varying, phase-shifted offset, ie always opposite the negative voltage rail positively remaining voltages

(Phase converter output voltages). The unipolarity of

Phase converter output voltages, by shifting a symmetrical phase in-line load voltage system (which ultimately between the assigned

Phase terminal and the free neutral point of the three-phase load to be supplied) formed by a positive offset in the amount of the amplitude of the Phasensinuslastspannungen. At the output of a phase converter voltage values between twice the amplitude of the phase sinus load voltage and zero occur, so it is in each phase in

In general case, the operation with an over the input voltage as well as with a lying below the input voltage output voltage level to master. As a phase converter Cuk converter with or without potential separation for the realization of the DC / DC converter are therefore proposed in corresponding publications.

Since the external load voltages picked up by the load between two positive output terminals of the Cuk DC / DC phase converter correspond to the difference of the two associated phase converter output voltages, the offset offset which is the same for all phases is found in the terminals of the three-phase load

external conductor voltages occurring (consumer external conductor voltages) no expression, the Verbraucheraussenleiterspannungen have accordingly a sinusoidal symmetrical course.

As a variant of the above-described generation of unipolar output voltages by continuous clocking of all three Cuk DC / DC phase converter is also a

Control method is known for which a phase converter output remains clamped in each case for one third of the output voltage period on the negative voltage rail, wherein in each case the phase with the most negative instantaneous value of the associated

Phasensinuslastspannung clamped and only the other two Cuk DC / DC phase converter clocks and generate output voltages such that compared to the clamped phase output sections of the respective outer conductor voltages are generated. Thus, a reduction of the switching losses of the system is possible, further occurs at the output of a phase converter at most the value of the amplitude of the fundamental to be formed Verbraucheraussenleiterspannung and not twice the value of the amplitude of the phase sink voltage. For both control methods, the Verbraucheraussenleiterspannung shows a smooth course due to the arranged at the output of the Cuk DC / DC phase converter smoothing capacitors. One for conventional inverter with pulse width modulated

Output voltage required LC output filter (see above) can thus be omitted.

However, despite this, a high implementation cost of the overall system is given, since instead of a boost converter inductance of the conventional two-stage system described at the beginning (see FIG. 1), three input inductances and instead of the

DC link capacitance three capacitors as core elements of capacitive

Power transfer based Cuk DC / DC phase converter are to be used. Furthermore, at the power semiconductors significantly higher, by the sum of inputs and

Output voltage of a phase converter and not defined either by the input voltage or the output voltage blocking voltage loads and thus ultimately high switching losses. The well-known single-stage Cuk-based DC / AC converter is therefore applicable only to consumers with relatively low effective value of the outer conductor voltage and with relatively low switching frequency feasible, which is the possibility of increasing the

Switching frequency limited to minimize the size of the filter elements.

Furthermore, the control of the phase converter of the single - stage system has been carried out only einschleifig so far, which in view of the high number of energy storage and the high order of the systems, a clear limitation of the dynamics of the control of

Phase converter output voltages or the Verbraucheraussenleiterspannungen results, which are particularly suitable for highly dynamic drives with requirements for a rapid

Speed or voltage increase or reduction is disadvantageous.

The object of the invention is therefore to provide a converter for the transmission of electrical energy between a DC and an AC system, which remedies at least one of the abovementioned disadvantages and has at least one of the following properties: and output voltage range, and produces continuous (filtered) output phase AC voltages, that it has a minimum number of inductive elements, that of lower

Size are one that, preferably by the input or output voltage of the

Phase converter defined blocking voltage load and / or switching losses of

Power semiconductors are low, that he has a multi-loop control of the phase converter has, so that a high dynamics of the control of the phase converter output voltages is given.

This object is achieved by a converter for transmitting electrical energy between a DC and an AC system according to the patent claims.

The converter for transferring electrical energy between a DC system and an AC system has a positive DC input voltage rail on the DC side and a negative DC input voltage rail and at least two output phase terminals on the AC side. In this case, there is a phase converter for each of the output phase terminals, which is connected on a first side to the positive DC input voltage rail and the negative DC input voltage rail and on a second side to this output phase terminal and is designed as a step-up buck converter. The converter has a control, which is designed, in the operation of the converter, each of the

Phase converter, in response to a ratio of a DC input voltage to instantaneous values to be generated at the output phase terminals

Output phase voltages, temporarily operated either as a pure buck converter or as a pure boost converter.

Thus, the phase converters are not embodied as DC / DC Cuk converters but as multi-loop regulated step-down DC / DC converters, the specification of the setpoint values of the phase converter output voltages being such that, on the one hand, a minimum

Maximum value of the output voltages is required and on the other hand results in a minimal fluctuation of the currents in the inductors of the phase converter. Thus, with a given switching frequency small inductance values and given

Inductance small switching frequencies are selected or low switching losses occur.

In embodiments, the control is adapted, in the operation of the converter in each of the phase converter, a timing of switches of the phase converter temporarily to a .

6

Restrict input side buck converter part or bridge branch or on an output side boost converter part or bridge branch of the phase converter.

In embodiments, the regulation is designed to make the clocking of all phase converters in operation of the converter such that the same clock frequency is present for all phase converters and synchronization of the clocking of the converters minimizes a differential voltage component contained in the output phase voltages.

In embodiments, the control is designed to perform the clocking of all phase converters during operation of the converter such that the same clock frequency is present for all phase converters and synchronization of the clocking of the converters minimizes a common-mode voltage component contained in the output phase voltages.

In embodiments, the control is configured to offset the formation of output phase voltage setpoints during operation of the converter

Specify load phase voltage setpoints, so,

in each case in a time interval for the phase converter whose assigned load phase voltage setpoint has the highest negative value

Output phase voltage setpoint equal to zero results, so this phase converter does not need to be clocked and its output phase connection to a

Reference voltage rail may remain clamped, and

the course of the output phase voltage setpoints of unblocked

Phase converters is defined by the setpoint values of load external conductor voltages formed relative to the clamped output phase connection and formed by subtracting in each case two load phase voltage nominal values in this time segment, so that overall there is a sinusoidal profile of all the load external conductor voltages.

In embodiments, the phase converters are each formed as a cascaded buck-boost converter.

In embodiments, the phase converters are each realized by a circuit in which a bridge branch between the positive DC input voltage rail and a associated output phase terminal is arranged, a phase converter inductance between a center of the bridge branch and the negative DC input voltage rail is connected, an output capacitance between the

Output phase terminal and a common reference voltage rail is connected, which is connected to the DC input voltage rail.

In embodiments, in the phase converters, an output diode is connected between the output phase terminal and the reference voltage rail, respectively, which has a positive output phase voltage at the output phase terminal relative to the output phase terminal

Ensures reference voltage rail

In addition to the output diode, a switch can also be connected in parallel, or the output diode can be replaced by a switch with antiparallel output diode. Thus, the phase with the lowest voltage can each be clamped over one third of the period (no switching losses for this phase) and thus the converter efficiency can be increased.

In embodiments, the control is designed to select a constant offset of the output phase voltages so large during operation of the converter at relatively small amplitudes of the output phase voltages, that on the one hand, caused by generated load phase voltages fluctuation of the output phase voltages to lie symmetrically about a level of the DC input voltage On the other hand, a double maximum amplitude of load phase voltages is not exceeded, this being achieved by lowering the offset at high amplitudes of the load phase voltages.

In the following, the subject invention is based on preferred

Embodiments, which are illustrated in the accompanying drawings, explained in more detail. Each show schematically:

Fig. 1: Bidirectional three-phase buck-boost converter DC / AC converter system according to the prior art with input side DC / DC boost converter, DC link capacitor, output side voltage intermediate three-phase inverter and downstream LC output filter for generating a smoothed three-phase AC output voltage. Fig. 2: Converter system with each arrangement of a DC / DC Tiefhochsetzsteilers per output phase, each phase converter has an input side and a

Having output side bridge branch and arranged between the bridge arms, used for buck and boost converter operation phase converter inductance.

Fig. 3: Time course of the supply of a three-phase machine to be generated

Phase converter output voltages for (FIG. 3.1) time-constant offset shift uoff of the load-phase voltage system actually to be generated in the amount of the amplitude of the load-phase voltage; (Fig. 3.2) with constant offset shift and additional

Superimposing an alternating component of the offset signal with three times the output frequency and a phase position such that the maximum value of the phase converter output voltages is minimized; (Fig. 3.3) at offset shift of the to be generated

Load phase voltage system such that for a phase converter output over a third of the output period, a setpoint value is zero, and this converter can therefore remain in the clamped state.

4: execution of the phase converters with virtually minimal complexity, wherein the

Output terminals of the phase converter negative potential show, and further to allow a simple run-up of the system starting from the output terminals of the phase converter diodes are placed against the reference voltage rail. In each case a diode parallel to an output capacitor may have a parallel switch, this analogous to the circuit in Figure 2 allows the clamping of the phase with the lowest voltage over one third of the period and thus reducing the switching / converter losses

5 shows the time curve of the setpoint values uout * of the phase converter output voltages uout (the individual voltages uan, ubn, ucn are designated uout in summary for the converter circuits according to FIG. 2, which have a lower amplitude UMpk of the setpoint values than the DC input voltage Uin the load phase voltages uM * can be used to achieve a minimization of the switching-frequency fluctuation of the current in the phase converter inductance (see Fig. 5.1) .Figure 5.2 shows the time characteristic associated with the converter circuit according to Fig. 4, which is an alternative to Fig. 5.1 can also be used for the converter circuit according to Fig.2. 2uMpk, max denotes the maximum value of the phase converter output voltages uout occurring at maximum load phase voltage amplitude; the associated time sequences of uout are shown in dotted lines.

Fig. 6: Device for controlling the output voltages of the phase converter to set a predetermined curve uM * the load phase voltages uM, as required for UPS systems or in the supply of variable speed three-phase machines. The regulation has the same structure for each phase and is shown for the sake of clarity only for one phase.

Fig. 7: Apparatus for controlling the DC output voltage formed in the interaction of all the phase converter when using the converter system as

Three-phase pulse rectifier circuit, wherein by a subordinate control a sinusoidal course of the network phase currents, each in phase with the associated

Mains phase voltage is ensured. The regulation has the same structure for each phase and is shown for the sake of clarity only for one phase.

8: Modification of a part of the control devices according to FIG. 6 and FIG. 7.

FIG. 9 shows an alternative embodiment of a part of the control circuit according to FIG. 6 to FIG. 8.

Each system phase converter (see FIG. 2) has an input-side bridge branch 3a, 3b, 3c located between the positive DC input voltage rail 1 and the negative DC input voltage rail 2, which is connected in series with an upper, typically collector or drain side, with the positive DC input voltage rail connected and a lower, typically emitter or source side connected to the negative DC input voltage rail switch, generally one

Power transistor is realized, wherein a free-wheeling diode is connected in anti-parallel to both transistors and the two transistors common circuit point (connection of the emitter or source terminal of the upper and the collector or drain terminal of the lower transistor) the bridge branch output 4a, 4b, 4c forms of which branches off a phase converter inductance La, LD, LC, which is connected with its second end to the input 5a, 5b, 5c of another output-side bridge branch 6a, 6b, 6c, wherein the source terminal of the lower switch or transistor of this bridge branch with a reference voltage rail n and the drain terminal of the upper transistor of this bridge branch is connected to the associated output phase terminal a, b, c, wherein to ensure a smooth course of the

Output phase voltage between the output phase terminal and the

Reference voltage rail is a smoothing capacitance Ca, Cb, Cc. The for everyone

Phase converter common reference voltage rail n is finally connected to the negative rail 2 of the DC input voltage, whereby each phase converter advantageously has the structure of a buck-boost DC / DC converter and the entire three-phase DC / AC converter system only three inductors La, Lb, Lc.

A three-phase load is connected with its phase terminals to the output phase terminals a, b, c of the three phase converter and has a free neutral point, so that only the chained phase converter output voltages (load transient voltages), defined as the difference of two phase converter output voltages or a load phase terminal against a Laststernpunkt measured load phase voltage determines the formation of the load phase currents.

The phase converter output voltages are generated in such a way that the nominal values of the load phase voltages u_an, u_bn, u_cn, which typically have an output frequency sinusoidal and form a symmetrical three-phase system, are shifted to positive values (see FIG Phase output voltage a unipolar curve, ie only positive values or minimally shows the value zero. As mentioned above, this offset does not become effective in the load output voltages, and thus does not affect the current generation of the load. In embodiments, another offset of three times the output frequency and an amplitude and phase may be added to this constant offset so as to ensure the unipolarity of the output phase voltages with a minimum value of the constant offset, whereby the voltage loading of the transistors of the output side bridge branches 6a, 6b, 6c the phase converter can be minimized at a defined load phase voltage amplitude to be generated (see FIG. 3.2). With regard to the timing of the input and output side bridge branches 6a, 6b, 6c of the phase converter, it should be noted that in regions in which a phase converter output voltage lying above the DC input voltage has to be generated, the upper switch or power transistor of the input side bridge branch 3a, 3b, 3c a phase converter can remain switched through, and only the output-side bridge branch 6a, 6b, 6c is clocked. The voltage ratio of the converter then corresponds to power flow from the DC input voltage to

Phase converter output voltage that of a boost converter, wherein the

Phase converter inductance La, Lb, Lc as boost converter inductance, the lower

Power transistor of the output side bridge branch 6a, 6b, 6c as

Boost converter transistor and the antiparallel diode of the upper power transistor acts as a boost converter freewheeling diode, wherein in embodiments always the upper power transistor is also turned on, i. the power transistors of the output side bridge branch 6a, 6b, 6c are operated in push-pull. Since all power transistors antiparallel diodes are arranged, then a power flow of the

Phase converter output voltage into the DC input voltage, wherein the function of the phase converter in this case, the one between

Phase converter output voltage and DC input voltage lying buck converter corresponds.

In areas where one is below the DC input voltage

Phase converter output voltage must be generated remains in embodiments of the upper power transistor of the output side bridge branch 6a, 6b, 6c of the

Phase converter switched, and the timing is on the input side

Bridge branch 3a, 3b, 3c limited. The voltage ratio of the converter then corresponds to power flow from the DC input voltage to

Phase converter output voltage that of a buck converter, wherein the

Phase converter inductance as Tiefsetzstellerinduktivität, the upper power transistor of the input side bridge branch 3a, 3b, 3c as a buck converter transistor and anti-parallel to the lower power transistor diode acts as a buck converter freewheeling diode, in embodiments always switched through the lower power transistor, ie the power transistors of the input-side bridge branch 3a, 3b, 3c be operated in push-pull. Since antiparallel diodes are arranged for all power transistors, can then also be a power flow from the phase converter output voltage to the DC input voltage, wherein the function of the phase converter in this case corresponds to a lying between phase converter output voltage and DC input voltage boost converter.

With regard to the timing of all phase converter should be noted that in embodiments for all phase converter, the same clock frequency is selected and a synchronization of the timing of the converter is such that the in the

Phase converter output voltages contained push-pull voltage component, which leads to switching-frequency currents and thus possibly to high-frequency losses in the connected three-phase load is minimized, i. Switching frequency changes of the

Phase converter output voltages are mainly formed as common mode components, which cause a similar voltage shift relative to the reference voltage rail for all phase outputs.

For consumers, in particular to high-frequency

Common mode shifts are sensitive, on the other hand, a synchronization of working again with the same clock frequency phase converter can be made such that the switching frequency common mode voltages are minimized, in which case, however, a higher differential mode component of the phase converter output voltages is to be accepted.

An alternative course to the Fig.3.1 and Fig.3.2 offset is defined such that for the phase converter whose associated load phase voltage has the highest negative value, an output phase voltage setpoint equal to zero results (see Fig.3.3), so this phase converter does not need to be clocked , or the associated

Output phase terminal may remain clamped to the reference voltage rail, which for the above-described phase converter topology (see Figure 2) by simply

simultaneous switching of the upper and the lower power transistor of the output side bridge branch 6a, 6b, 6c can be achieved. Also advantageous is the lower power transistor of the input-side bridge branch 3a, 3b, 3c

turn on. The course of the output voltage setpoints of the other two

Phase converter is then directly by the opposite of the clamped phase to be generated and by subtracting two load phase voltage setpoints to forming sections of the setpoints of the load Aussenleiterspannungen defined so that a total of a sinusoidal waveform of all three load outer conductor voltages is reached again. Since the clamping is passed cyclically between the phases, each phase remains clamped for a third of the load phase voltage period when generating a sinusoidal balanced load phase voltage system and thus without switching losses, thus increasing the efficiency of energy transfer is achieved.

With regard to the realization of the phase converter, it should be noted that in addition to the embodiment described above there are a number of advantageous modifications:

Thus, in embodiments, the input and / or output side bridge branch may advantageously be in multi-level structure, e.g. be performed as Flying Capacitor Multilevelbridge branch, which for setting the voltage ratio between DC input voltage and phase converter output voltage, a higher number of

Voltage levels is available, whereby a lower switching frequency ripple of the currents in the phase inductances occurs.

Further, in embodiments, the phase converters may be implemented by a plurality of parallel out-of-phase clocked systems, whereby the current fed into the output capacitance and from the DC input voltage relative to a single system advantageously has a higher effective frequency and a smaller variation.

A converter system in embodiments with phase converters of relatively low complexity is shown in FIG. 4, where in each phase only one bridge branch is arranged between the positive terminal of the DC input voltage and the associated output or load phase terminal for realizing the bi-directional DC / DC step-down converter is and the associated phase converter inductance is connected from the center of the bridge branch to the reference voltage rail. Functionally, then the

Reference voltage rail positive potential or show the output terminals of the phase converter negative potential, which in the specification of the setpoints of the

Output phase voltages must be taken into account (ie, the voltage is counted from the reference voltage rail against the phase terminals). In order to enable a simple run-up of the system, in embodiments further diodes can be placed against the reference voltage rail starting from the output terminals of the phase converters. According to a clamp circuit is then in the presence of an active three-phase load or when connecting a three-phase network instead of a three-phase load, a polarity reversal of

Inhibit phase converter output voltages and ensured in a wide interval of the output period without clocking the power transistors, a positive output voltage, which can be used for booting the system. In addition to each output diode, a switch can also be connected in parallel in each case, or the output diode can be replaced by a switch with antiparallel output diode. Thus, as for the circuit of FIG. 2, the phase with the lowest voltage can be clamped over one third of the period (no switching losses for this phase) and thus the converter efficiency can be increased.

It should be noted that for phase converters with an input and output side bridge branch (see FIG. 2), the free-wheeling diodes of the output-side bridge branch act as clamping diodes during run-up and therefore no further explicit diodes are to be provided.

For use of the system of FIG. 2 or FIG. 4 for feeding a three-phase machine (load) located at the output phase terminals, different amplitudes of the load phase voltage or different amplitudes of the associated phase converter output voltages are to be generated depending on the speed of the machine, typically at maximum speed the highest amplitude values occur for which the

Power semiconductor of the output side bridge branch are interpreted.

Advantageously, the constant offset can now be selected to be so large for the circuit according to FIG. 2 at low rotational speeds or relatively small amplitudes of the phase converter output voltages that, on the one hand, the fluctuation of the phase converter output voltages caused by the load phase voltages to be generated is symmetrical about the level of the DC input voltage on the other hand, the maximum speed associated twice maximum amplitude of the load phase voltage is not exceeded, this by lowering the offset correspondingly at high Amplitudes of the load phase voltages is achieved. As shown in FIG. 5.1, the setpoint values of the phase converter output voltages then typically have minimum values significantly greater than zero, and the currents in the phase converter inductors exhibit a relatively small ripple, since then the input and output side bridge branches operate alternately with duty ratios close to one (ie each upper

Power transistors are almost constantly turned on) which is known to result in a low switching-frequency fluctuation of the current in the phase converter, which in turn finds expression in low high-frequency losses. Also considering the then switched due to the higher

Phase converter output voltage higher switching losses of the output side

Bridge branches is thus an improvement in the efficiency of energy transfer achievable.

For the circuit of Fig. 4, the phase converter output phase voltages are always as low as possible, in contrast to Fig. 5.1. The constant offset regardless of the amplitude of the load phase voltage or machine speed to keep as small as possible, so only to choose so large that zero occurs as a minimum voltage value (see Fig.5.2). This is because then the upper power transistors of the input side bridge branches of the phase converters have low duty cycles, again resulting in a small variation in the currents in the phase converter inductors.

A cascaded control of the three-phase converter system according to FIG. 2 is shown in FIG. The control circuit is similar for each phase and shown in the interest of clarity only for one phase. Tensions are, as registered against the

Reference voltage rail n or the negative rail DC- the DC input voltage Uin measured.

The nominal value of a phase converter output voltage uout * is obtained by adding the typically sinusoidal setpoint value uM * of the associated

Load phase voltage uM of a fed three-phase load (eg an electric machine M) and the same for all phases setpoint uoff * offset uoff formed, which is typically generated by adding a constant over the output period proportion uoffDC * and a three times the output frequency fluctuating portion uoffAC *. Advantageously, the time course of uoff * is selected such that uout * is limited to the lowest possible values for a given load-phase voltage system uM * to be generated , _r

16

remains, whereby the reverse voltage stress and the switching losses of the output side bridge branches BB of the phase converter can be minimized. This includes a default of uoff * such that one phase converter each remains in the clamped state for one-third of the output period, i. uout * has correspondingly broad intervals with uout * = 0.

The phase converter output voltage reference value uout * is compared with the measured actual value of the phase converter output voltage, and the deviation Deltout is fed to a phase converter output voltage controller Ruout, at the output of which is required to correct deltaoutput

Output capacitor current setpoint iCout * is formed, which by pre-control of the measured associated load phase current iLoad the output current i of the output side bridge branch BB of the phase converter determined by dividing by the duty cycle dB of the upper transistor T3 of this bridge branch in a target value iL * of the current iL in the Phase converter inductance L can be converted. By comparing iL * with the measured actual value iL, the control deviation deltaiL of the current is then formed in L and a

Phase inductance current regulator RiL supplied, which forms at its output the required to correct the deviation DeltaiL setpoint uL * the voltage to be applied to L.

Starting from the assumption of an operation with continuously switched-through upper transistor T3 of the output-side bridge branch BB, which is characterized by the occurrence of uout at the input terminal B of BB and thus also at the output end of L, then the setpoint uA * is the one on the input side End A of L to be placed or to be generated at the output A of the input-side bridge branch BA voltage uA to be generated by adding uL * and uout. The duty cycle dA, i. the relative duty cycle of the upper transistor Tl of BA is then simply obtained in the sense of a step-down function of BB by dividing uA * and the actual value of the DC input voltage Vin.

Since dA is limited to values between zero and one, uA * must be limited upwards by Uin and downwards by the value zero. Advantageously, according to this limitation, the relative duty cycle of the bridge branch BB can be easily generated by subtracting from uA * the measured DC input voltage Uin. The way Difference obtained delta uA * is limited downwards by the value zero and upwards by uout, which corresponds to the physically adjustable limits of uA. If a positive value DeltauA * now occurs, this ultimately means that BB above L for correct

Current regulation to be generated voltage value uL * even at maximum modulation of BA with dA = l or uA = Uin can not generate. Accordingly, then the input B of BB may not continue to have the duty cycle dB = l or T3 may no longer remain permanently in the through-connected state as assumed above. The input B is thus voltage-wise to lower DeltauA *, or ultimately a desired value uB * of the voltage to be generated at B according to a subtraction of the limited value of uA * of uout, the duty cycle dB of BB then with respect to the buck converter function from BB from uout to uB by dividing uB * by uout.

For values of the DC input voltage Uin above uout *, the

Converter system mainly in buck converter mode, i. work with BA timing, BB will remain switched on continuously with dB = 1 or T3. Only with rapid transient changes of uout * or iLoad will a temporary clocking of BB occur.

However, the control circuit according to FIG. 6 also controls the operation for voltages Uin <uout, since the activation of the bridge branches BA and BB is indeed derived directly from the desired value uL * and the actual values uout and Uin. Advantageously, the control circuit is therefore independent of the respective ratio of Uin and uout * and also for both

Power flow directions, i. for supplying a motor M Uin or feedback of braking energy of the motor M can be used in Uin.

The drive signals of the push-pull bridge arms BA and BB are obtained from dA and dB by corresponding pulse width modulation.

As mentioned above, the converter circuit can be used on the one hand to supply an electric machine M, but on the other hand also as a three-phase rectifier system with advantageously sinusoidal mains currents iN and a regulated to a constant value DC output voltage Uout.

As shown in Fig. 7, then, using as much as possible the in

Connection with Fig.6 introduced terms the positive outputs of

Phase converter to connect and to the positive terminal DC + to lay a common output capacitor Cout for all phases, the negative rail DC- with the Reference voltage rail n, against which the input-side bridge arms BA are connected, is connected. Furthermore, the inputs of the bridge branches BA of the phase converters, which are all located at the positive terminal of the DC input voltage for FIG. 6, are now carried out separately and are conducted via phase connection inductances LN to the terminals aN, bN, cN of the three-phase network N. Furthermore, in each phase converter

Filter capacitor Cin parallel to the respective input-side bridge branch BA of the respective input terminal a, b, c against the common for all phase converter

Reference voltage rail n switched.

For the regulation of Vout, the difference between the DC output voltage setpoint Uout * and the measured value uout is formed and the control deviation Deltauout is fed to an output voltage regulator Ruout which is common to all phase converters and which at its output is used for a corresponding charge change of Cout

required current setpoint iCout * forms, to which advantageously the measured value iLoad of the current flowing to a DC consumer RLoad current is added to the setpoint iout * of the output circuit iout to be formed by the parallel connection of the phase converter (sum of the output currents i of the output side bridge branches BB) receive. By multiplying by Uout *, a nominal value pout * of the converter output power is then obtained, assuming a symmetric and sinusoidal characteristic of the mains phase voltages uN by dividing by the threefold square of the amplitude UNpk of a mains phase voltage and dividing by 2, 3/2 UNpk ^A 2, into the Setpoint of a

The equivalent conductance G * of the phase branches of a resistor replacement star connection, which is to be represented by the converter system for the network in order to ensure an ohmic network behavior, is converted. By multiplying G * by the measured value of the assigned mains phase voltage uN, it is then easy to obtain the desired value iN * of the line phase current iN to be obtained from the respective phase converter, from which the measured value iN of the mains phase current is subtracted in order to obtain a system deviation DeltaiN which corresponds to a line current controller RiN is supplied, which generates at its output the setpoint uLN * of the voltage to be generated on the associated Phasenvorschaltinduktivität LN uNN, which is to be subtracted from uN by the setpoint uinY * to be generated at the input of the phase converter relative to the Netzsternpunkt Y.

Phase voltage uinY, to which a setpoint value of an offset that is the same for all phases, uoff, is added by the setpoint value uin * to the reference voltage rail n to receive related phase converter input voltage uin. The offset setpoint value uoff * is typically generated by adding a constant component uoffDC * over the network period and a component uoffAC * fluctuating with three times the network frequency, and is designed so that uin * is limited to the lowest possible values uN for a given network phase voltage system the reverse voltage stress and the switching losses of the input side bridge branches of the phase converter can be minimized. This includes a specification of uoff * such that in each case a phase converter remains in the clamped state for one third of the output period, in which case the associated uin * has correspondingly broad intervals with uout * = 0.

The phase converter input voltage reference uin * is then used with the

measured actual value of the phase converter input voltage uin compared and the

Control deviation delta is fed to a phase converter input voltage controller Ruin, at the output of which is required for the correction of delta time

Input capacitor current setpoint iCin * is formed, which is subtracted from the setpoint value iN * of the associated line phase current to obtain the setpoint value iin * of the input current iin of the input-side bridge branch BA of the phase converter. By dividing iin * by the duty ratio dA of the upper transistor of BA, the setpoint value iL * of the current iL in the phase converter inductance L can then be obtained. The comparison (subtraction) of iL * with the associated measured value iL then leads to the deviation DeltaiL of the current in L which is supplied to a Phaseninduktivitätsstromregler RiL, at its output the setpoint uL * to correct the

Control deviation DeltaiL forms over L to be applied voltage uL. The remaining control circuit between iL * and the relative on durations dA and dB of the bridge branches BA and BB is the same as for the circuit of Figure 6, which is why a description can be omitted here.

The control circuit according to Figure 6 and Figure 7 is based on a buck converter operation of the input side bridge branch BA and a through state of the transistor T3 of the output side bridge branch BB as regular operation, but also the case of a lying above the input voltage output of a phase converter, ie the boost converter operation is mastered. Alternatively, the boost converter operation of the converter, ie, a steady state of Tl and clocking of the bridge branch BB can be considered as a regular operation, which results in the alternative embodiment shown in FIG. 8 of a part of the control circuits of Figure 6 and Figure 7. The remaining parts of the control circuits remain unchanged. The following description is therefore limited to the part of the already described devices to be replaced.

In order to determine the relative switch-on times of the bridge branches BA and BB, the setpoint value uL * is inverted and then physically from the output side to

Input voltage uin the phase converter added to determine the voltage setpoint uB * to be set at input B of BB. After limiting to uout up and zero down - it is only possible to set dB between zero and one - so the duty cycle, i. obtained the duty cycle of the upper transistor T3 of BB.

In order to be able to set the required voltage uL * even if uB * exceeds the value uout, the difference delta uB * of uB * and uout is furthermore determined and subtracted after limitation with uin up and zero down from the input voltage uin. This follows the consideration that to set a desired value uL * which leads to uB * = uout or db = l, the output A of the bridge branch BA must be released from the input voltage and lowered in potential by appropriate timing. The duty cycle dA to be set then can be obtained simply by dividing uA * by uin.

For values of the input voltage u in which are below uout, then the converter system is operated predominantly in boost mode operation, i. work with BB timing, BA will remain switched on with dA = l or Tl continuously. Only in case of rapid transient changes of uin * or iLoad will BA temporarily be clocked. However, the control circuit also controls the operation for voltages uin> uout, since the activation of the bridge branches BB and BA yes directly from the setpoint uL * (and the actual values uin and uout) is derived. Advantageously, the control circuit is therefore independent of the respective ratio of uin and uout and also for both power flow directions, i. for feeding a motor M from uin, or for realization of a photovoltaic inverter for feeding photovoltaic generated power (uin then represents the voltage of the

Solar panels dar) or for the recovery of braking energy of a three-phase motor M in the DC input voltage uin, or for the operation of the device as an active three-phase rectifier system (generating a DC output voltage uout) can be used.

An alternative embodiment of a part of the control circuit of Fig. 6, which for calculating the duty cycles dA and dB, in contrast to the two

Control concepts according to Fig. 6 to Fig. 8, both modes, i. Buck and boost operation, equally favored, is shown in FIG. On the one hand, for the bridge branch BA, a bucking operation is assumed, i. it is assumed that the bridge branch BA is clocked and, on the other hand, a bridge operation is assumed for the bridge branch BB, i. it is assumed that the bridge branch BB is clocked. In order to obtain the setpoint voltage uA * of the bridge branch BA, the setpoint value uL * is added to the output voltage uout and limited up to uin and down to zero. Conversely, for the calculation of the setpoint voltage uB * of the bridge branch BB, the setpoint value uL * is subtracted from the input voltage uin and limited up to uout and down to zero. By this mutual settlement of the output voltage uout in the

Target voltage uA * and the input voltage uin in the target voltage uB * and the corresponding limitation on the possible adjustment range, the two modes are finally excluded from each other, i. The converter works despite initial consideration of both modes, either in pure buck or pure boost mode. The duty cycle dA and dB to be set can then be obtained simply by dividing uA * by uin or uB * by uout.

Claims

claims

A converter for transmitting electrical energy between a DC (DC) system and an AC (AC) system, comprising on the DC side a positive DC input voltage rail (1) and a negative DC input voltage rail (2) and AC side at least two

Output phase connections (a, b, c),

wherein for each of the output phase terminals (a, b, c) there is a phase converter (10a, 10b, 10c) having on a first side the positive DC input voltage rail (1) and the negative DC input voltage rail (2) and at a second one Side is connected to this output phase terminal (a; b; c) and is designed as a step-up buck converter, and

wherein the converter comprises a regulator adapted to, during operation of the converter, generate each of the phase converters (10a, 10b, 10c) in response to a ratio of a DC input voltage to instantaneous values of the output phase terminals (a, b, c) Output phase voltages, temporarily operated either as a pure buck converter or as a pure boost converter.

2. Converter according to claim 1, wherein the scheme is designed, during operation of the converter in each of the phase converter (10a, 10b, 10c) a timing of switches of the phase converter (10a, 10b, 10c) temporarily on an input side buck converter part or bridge branch or to restrict to an output-side boost converter part or bridge branch of the phase converter (10a, 10b, 10c).

3. Converter according to claim 1, or 2 wherein the scheme is adapted to make the operation of the converter, the timing of all the phase converter (10a, 10b, 10c) such that for all phase converter (10a, 10b, 10c) is the same clock frequency and a

Synchronization of the clocking of the converter to minimize a differential voltage contained in the output phase voltages to minimize.

4. Converter according to claim 1, or 2 wherein the control is designed to perform the operation of the converter, the timing of all the phase converter (10a, 10b, 10c) such that for all phase converter (10a, 10b, 10c) is the same clock frequency and a

Synchronization of the clocking of the converter minimizes a common-mode voltage component contained in the output phase voltages.

5. Converter according to one of the preceding claims, wherein the control is adapted to, during operation of the converter, an offset to form

Specify output phase voltage setpoints from load phase voltage setpoints, thus,

an output phase voltage setpoint equal to zero results for each of those phase converters (10a, 10b, 10c) whose associated load phase voltage setpoint has the highest negative value, whereby this phase converter (10a, 10b, 10c) need not be clocked and its output phase connection (a b) c) may remain clamped to a reference voltage rail (s), and

the course of the output phase voltage setpoints of unblocked

6. Converter according to one of claims 1 to 4, wherein the control is designed to select a constant offset of the output phase voltages so large during operation of the converter at relatively small amplitudes of the output phase voltages, that on the one hand, caused by to be generated load phase voltages fluctuation

Output phase voltages symmetrically about a level of the DC input voltage comes to lie, and on the other hand, a double maximum amplitude of

Load phase voltages is not exceeded, this being achieved by lowering the offset at high amplitudes of the load phase voltages.

7. Converter according to claim 6, wherein the control is adapted to superimpose a third harmonic in addition to the constant offset.

8. Converter according to one of the preceding claims, wherein the phase converter (10a, 10b, 10c) are each formed as a cascaded down-up converter (buck-boost converter).

9. Converter according to one of claims 1 to 5, wherein the phase converter (10 a, 10 b, 10 c) are each realized by a circuit in which a bridge branch between the positive DC input voltage rail (1) and an associated

Output phase terminal (a; b; c) is arranged, a phase converter inductor (La, Lb, Lc) is connected between a midpoint of the bridge branch and the negative DC input voltage rail (2) has an output capacitance (Ca, Cb, Cc) between the output phase terminal ( a; b; c) and a common reference voltage rail (s) connected to the DC input voltage rail (2).

10. Converter according to claim 9, wherein in the phase converters (10a, 10b, 10c) in each case an output diode (Da, Db, De) between the output phase terminal (a; b; c) and the reference voltage rail (s) is connected which a positive Ensure output phase voltage at the output phase terminal (a; b; c) with respect to the reference voltage rail (s).

11. A converter according to claim 9 and 10, wherein in which the phase converters (10a, 10b, 10c) each in parallel with the output diode (Da, Db, De), a switch is connected in antiparallel or is replaced by a bidirectional switch.

12. A converter according to claim 9 and 11, wherein the control is designed to always choose a constant offset of the output phase voltages equal to the amplitude of the load phase voltage during operation of the converter.

13. A converter according to claim 9 to 12, wherein the control is adapted to superimpose a third harmonic in operation of the converter in addition to the constant offset, wherein the ratio of constant offset and the amplitude of the third harmonic can be freely selected and the sum of the two shares is always chosen so the minimum output phase voltage just reaches the potential of the negative DC input voltage rail.

14. The converter according to claim 11, wherein the control is designed to offset the formation of output phase voltage setpoints during operation of the converter

Specify load phase voltage setpoints, such that in each case for a phase for that phase converter (10a, 10b, 10c), whose associated

Load phase voltage setpoint has the highest negative value, a

Output phase voltage setpoint equals zero, whereby this phase converter (10a, 10b, 10c) does not have to be clocked and its output phase connection (a; b; c) can remain clamped to a reference voltage rail (s), and the course of the

Output phase voltage setpoints from non-clamped phase converters to be generated and passed through relative to the clamped output phase terminal

Subtraction of each of two load phase voltage setpoints in this period formed set values of Lastaussenleiterspannungen is defined, so that a total of sinusoidal waveform of all Lastaussenleiterspannungen is present.

15. Converter according to one of claims 1 to 8, wherein the scheme is adapted, in operation of the converter, starting from a buck converter operation of the converter as a regular operation, clocking an input-side bridge branch (BA)

switched upper switch (T3) of an output side bridge branch (BB) to produce a three-phase load phase voltage system u *, when feeding the converter by a DC input voltage Uin, wherein the control circuit performs an automatic change between buck and boost converter operation of the phase converter.

16. A converter according to one of claims 1 to 8, wherein the control is designed, in operation of the converter, starting from a buck converter operation of the converter as a regular operation, with clocking of an input-side bridge branch (BA)

switched upper switch (T3) of an output side bridge branch (BB), the converter as a three-phase pulse rectifier system, which generates a regulated DC output voltage and the network draws sinusoidal currents to operate, wherein the control circuit performs an automatic change between buck and boost converter operation of the phase converter.

17. Converter according to one of claims 1 to 8, wherein the control is adapted to, during operation of the converter, starting from a boost converter operation of the converter, with permanent on state of an upper transistor (Tl) of an input-side bridge branch (BA) and clocking of an output-side bridge branch ( BB) as

Regular operation, wherein for the determination of relative turn-on of the input and output side bridge arms (BA, BA) a setpoint uL * inverted and then this physically directed from the output side to the input side voltage -uL * to

Input voltage uin added to the phase converter and thus the voltage setpoint uB * to be set at the input B of the output side bridge branch (BB) is determined, and after limiting to uout up and zero down - physically only between zero and one lying duty ratios dB can be set - Duty cycle, ie the duty cycle of the upper transistor (T3) of the output side

Bridge branch (BB) is obtained, and then, in order to set the required voltage uL * when uB * exceeds the value uout, the difference delta uB * of uB * and uout is further determined and after limiting with uin up and Zero down from the input voltage uin subtracted, and this follows the consideration that for setting a target value uL * which uB * = uout or db = l leads, the output of the input-side bridge branch (BA) of the input voltage and solved by appropriate Clocking must be lowered in terms of potential, wherein the then to be set duty cycle dA is obtained by dividing uA * by uin.

18. Converter according to one of claims 1 to 8, wherein the control is adapted to, in operation of the converter, starting from both modes of the converter as

Regular operation, by mutual settlement of the output voltage uout in the

Setpoint voltage uA * and the input voltage uin in the setpoint voltage uB * and the corresponding limitation on the possible setting range, depending on the

Setpoint voltage uL * and the two voltages uin and uout the correct operating mode, ie either pure buck or pure boost operation to determine.

19. A converter according to any one of claims 1 to 8, wherein the control is adapted to each form a switching frequency triangular or trapezoidal current in the phase converter inductance (La, Lb, Lc) during operation of the converter, such that when switching off a power transistor always a correspondingly directed current for the charging of a parasitic capacitance of the switching off and the discharge of the parasitic capacitance of the subsequent turn on transistor of a bridge branch is available, so that turning on the subsequent transistor is de-energized, thus ensuring a lossless or ideal lossless (de-energized) switching is, in particular for current shaping respectively the input side and the output side

Bridge branch of a phase converter to be clocked simultaneously.

20. A converter according to one of claims 1 to 8, wherein the control is designed to operate synchronously in the operation of the converter, the deep boost converter DC / DC converter, with the same switching frequency and a carrier signal of the modulation such that a

Current load of a feeding DC voltage is minimized by superimposed by the individual bridge branches recorded current pulses such that overall there is a relatively low switching frequency fluctuation of the total input current taken from the DC voltage.

21. Converter according to one of claims 1 to 10, wherein the control is adapted to operate during operation of the converter with a supply voltage in the form of a rectified, but not smoothed Einphasenwechselspannung, hereinafter referred to as absolute value voltage, by the input side with respect to a local, Extending over a clock period, a mean value of the absolute magnitude is taken a proportional, ie also amount sinusoidal current, and on the other hand by the phase converter (10a, 10b, 10c) output voltages are formed such that there is a symmetrical sinusoidal Außenleiterspannungssystem for the three-phase load, the output capacitors (Ca, Cb, Cc) are used for the compensation of a difference between the constant power delivered to a three-phase load and the dual mains frequency fluctuation of the power drawn from the network in such a way that a simultaneous sliding increase or decrease all

Output voltages made by adding an offset and thus the in the Output capacitors (Ca, Cb, Cc) energy is increased or decreased, leaving the Ausgangsaussenleiterspannungen unchanged.

22. A converter according to any one of claims 1 to 10, wherein the control is adapted to the operation of the converter with respect to a phase shift of

Load voltage and load current adjustable electrical load to work, the phase shift is chosen so that a charge required for a transfer of the output capacitors (Ca, Cb, Cc) reactive power compensated and thus not on the phase converter inductors (La, Lb, Lc) must be supplied a reduction of the current load of the power semiconductors of the phase converters (10a, 10b, 10c) and the phase converter inductances (La, Lb, Lc) is achieved.