CH714180B1 - Converter for transferring electrical energy between a DC and an AC system. - Google Patents

Abstract

The invention relates to a converter for the transmission of electrical energy between a direct voltage (DC) system and an alternating voltage system. It has a positive DC input voltage rail (1) and a negative DC input voltage rail (2) on the DC voltage side and at least two output phase connections (a, b, c) on the AC voltage side. There is a phase converter for each of the output phase connections (a, b, c), which is connected on a first side to the positive DC input voltage rail (1) and the negative DC input voltage rail (2) and on a second side to this output phase connection (a ; b; c) is connected and is designed as a step-up / step-down converter. The converter has a control which is designed to switch each of the phase converters during operation of the converter, depending on a ratio of a DC input voltage to instantaneous values of the output phase voltages to be generated at the output phase connections (a, b, c), at times either as a pure step-down converter or to operate as a pure step-up converter.

Description

The power electronic conversion of a direct voltage into a three-phase alternating voltage system (DC / AC conversion) is widely used in industry, e.g. in drive technology, in uninterruptible power supplies (UPS) and in feeding photovoltaically generated energy into the three-phase network.

The input DC voltage level here has a relatively large fluctuation range due to the terminal voltage of electrochemical storage or fuel cells (drive technology or UPS), which is typically strongly dependent on the state of charge, or due to the temperature dependence of the characteristic curve of solar cells (photovoltaics), so that the power electronic converter typically has two stages, ie with an input-side DC / DC step-up converter, a voltage intermediate circuit and an output-side three-phase DC / AC converter (inverter) (see Fig. 1). In this way, the inverter, which ultimately acts as a step-down converter when there is a power flow from the DC side to the three-phase AC side, can advantageously be designed for operation with a constant intermediate circuit voltage and thus with minimal construction output. Furthermore, the higher intermediate circuit voltage level compared to the DC input voltage makes it possible to generate a relatively high output voltage, which can also be maintained regardless of the state of charge of the battery, or for photovoltaic systems to operate at the point of maximum power delivery regardless of the level of irradiation and temperature. In drive technology, the high intermediate circuit voltage offers the advantage of being able to control a wide speed range of a powered AC machine.

The inverter generates a three-phase pulse-width-modulated voltage system from the intermediate circuit voltage and, in the simplest case, applies it directly to the motor terminals when a variable-speed drive is implemented. However, as a result of the steep voltage flanks, this results in a considerable insulation load on the stator windings of the motor, and the stator current typically has a high switching frequency ripple, which can lead to high rotor losses and, due to the cooling restricted by the air gap, to a considerable thermal load on the rotor. Furthermore, bearing currents caused by the switching-frequency common-mode component of the machine terminal voltages, which can lead to the destruction of the bearing raceways, are to be mentioned as disadvantageous. The disadvantages mentioned can be avoided by a three-phase LC output filter of the inverter, which suppresses switching-frequency harmonics of the pulse-width-modulated inverter output phase voltages and thus ensures a smooth, typically sinusoidal inverter output voltage curve.

For UPS systems, this LC output filter is to be arranged in any case, since the connected AC voltage consumers generally have to be fed with a voltage that differs only slightly from a purely sinusoidal curve. The same applies to photovoltaic applications, where the LC output filter is the first stage of an EMC filter, which is intended to suppress the propagation of switching-frequency electromagnetic interference (currents) in the three-phase network.

In this context, it should be pointed out that the converter structure described above also when reversing the direction of energy, i.e. for applications in which, starting from a three-phase network voltage, a DC voltage that fluctuates over a wide range must be generated, as is the case, for example, when charging the battery of electric vehicles Case is, can find use. The DC / DC step-up converter then works as a DC / DC step-down converter (a power transistor antiparallel to the step-up converter diode and a diode antiparallel to the step-up converter power transistor) and regulates the power and current flow from the DC / DC step-up converter due to the opposite direction of energy Intermediate circuit in the battery. In this case, the three-phase AC / DC converter acts as an active rectifier and ensures a sinusoidal curve for the currents drawn from the network and a constant value of the intermediate circuit voltage.

However, the overall system with the inductance of the DC / DC step-up converter, the intermediate circuit capacitor and the filter inductance and filter capacitance arranged in each of the three output phases of the inverter has a high overall expenditure of passive components, which results in a relatively high volume high implementation costs are to be accepted. Furthermore, the two-stage energy conversion is to be seen as disadvantageous with a view to high energy efficiency.

In the literature, single-stage DC / AC converters have therefore been proposed which are formed from three identical bidirectional DC / DC phase converters, which have a common negative voltage rail and, based on the same DC supply voltage, three sinusoidally varying, phase-shifted offset, ie compared to the negative voltage rail always generate positive remaining voltages (phase converter output voltages). The unipolarity of the phase converter output voltages is created by shifting a symmetrical phase sine load voltage system (which should ultimately occur between the assigned phase terminal and the free star point of the three-phase load to be fed) by a positive offset equal to the amplitude of the phase sine load voltages. At the output of a phase converter, voltage values between twice the amplitude of the phase sine load voltage and zero occur, so operation with an output voltage level above the input voltage as well as with an output voltage level below the input voltage can generally be controlled in each phase. Cuk converters with or without potential separation for the implementation of the DC / DC converter are therefore proposed as phase converters in corresponding publications.

Since the external conductor voltages tapped by the load between two positive output terminals of the Cuk DC / DC phase converter correspond to the difference between the two associated phase converter output voltages, the offset shift, which is the same for all phases, is found in the external conductor voltages occurring at the terminals of the three-phase consumer (consumer external conductor voltages) no expression, the consumer external conductor voltages accordingly show a sinusoidal symmetrical curve.

As a variant of the above-described generation of unipolar output voltages by continuously clocking all three Cuk DC / DC phase converters, a control method is also known for which a phase converter output remains clamped for a third of the output voltage period on the negative voltage rail, the phase in each case is clamped with the most negative instantaneous value of the associated phase sine load voltage and only the two other Cuk DC / DC phase converters clock and generate output voltages in such a way that sections of the respective external conductor voltages are generated compared to the clamped phase output. Thus, a reduction of the switching losses of the system is possible, furthermore the value of the amplitude of the fundamental oscillation of the load line voltage to be formed and not twice the value of the amplitude of the phase sinusoidal voltage occurs at the output of a phase converter.

For both control methods, the load line-to-line voltage shows a smooth curve due to the smoothing capacitors arranged at the output of the Cuk DC / DC phase converter. An LC output filter (see above) required for conventional inverters with pulse width modulated output voltage can thus be omitted. However, there is still a high level of implementation effort for the overall system, since instead of a boost converter inductance of the conventional two-stage system described at the beginning (see Fig. 1), three input inductances and instead of the intermediate circuit capacitance three capacitances are to be used as core elements of the Cuk DC / DC phase converter based on capacitive power transfer . Furthermore, significantly higher reverse voltage loads occur on the power semiconductors, which are defined by the sum of the input and output voltage of a phase converter and not either by the input voltage or the output voltage, and thus ultimately also by high switching losses. The known single-stage Cuk-based DC / AC converter can therefore only be used for consumers with a relatively low effective value of the line-to-line voltage and can be implemented with a relatively low switching frequency, which limits the possibility of increasing the switching frequency to minimize the size of the filter elements.

Furthermore, the regulation of the phase converter of the single-stage system has so far only been carried out in a single loop, which results in a clear limitation of the dynamics of the regulation of the phase converter output voltages or the consumer external conductor voltages with a view to the high number of energy stores and the high order of the systems is particularly disadvantageous for highly dynamic drives with requirements for a rapid increase or decrease in speed or voltage.

The object of the invention is therefore to create a converter for the transmission of electrical energy between a DC and an AC system which eliminates at least one of the disadvantages mentioned above.

This object is achieved by a converter for the transmission of electrical energy between a DC and an AC system according to the claims.

The converter for transmitting electrical energy between a direct voltage (DC) system and an alternating voltage (AC) system has a positive DC input voltage rail and a negative DC input voltage rail on the DC voltage side and at least two output phase connections on the AC voltage side. There is a phase converter for each of the output phase connections, which is connected on a first side to the positive DC input voltage rail and the negative DC input voltage rail and on a second side to this output phase connection and is designed as a step-up converter. The converter has a control which is designed to operate each of the phase converters, depending on a ratio of a DC input voltage to instantaneous values of the output phase voltages to be generated at the output phase connections, temporarily either as a pure step-down converter or a pure step-up converter when the converter is in operation.

So there are the phase converter not designed as a DC / DC-Cuk converter but as a multi-loop regulated step-down DC / DC converter, the specification of the setpoints of the phase converter output voltages is such that on the one hand a minimum maximum value of the output voltages is required and on the other hand, a minimal fluctuation of the currents in the inductances of the phase converters results. In this way, for a given switching frequency, small inductance values can be selected and, with given inductance values, small switching frequencies can be selected, or low switching losses can occur.

In embodiments, the control is designed to limit a clocking of switches of the phase converter temporarily to an input-side step-down converter part or bridge branch or to an output-side step-up converter part or bridge branch of the phase converter when the converter is in operation.

In embodiments, the control is designed to make the clocking of all phase converters during operation of the converter such that the same clock frequency is present for all phase converters and a synchronization of the clocking of the phase converter minimizes a push-pull voltage component contained in the output phase voltages.

In embodiments, the control is designed to make the clocking of all phase converters during operation of the converter such that the same clock frequency is present for all phase converters and a synchronization of the clocking of the converter minimizes a common-mode voltage component contained in the output phase voltages.

In embodiments, the control is designed to specify an offset for the formation of output phase voltage setpoints from load phase voltage setpoints when the converter is in operation, such that an output phase voltage setpoint equal to zero results in each case in a time segment for that phase converter whose assigned load phase voltage setpoint has the highest negative value This phase converter does not have to be clocked and its output phase connection can remain clamped to a reference voltage rail, and the course of the output phase voltage setpoints of non-clamped from the phase converters through setpoint values to be generated by the output phase connections and generated by subtraction of two load phase setpoints in this time segment is defined by load outer conductor voltages, so that overall there is again a sinusoidal curve for all load outer conductor voltages t.

In embodiments, the phase converters are each designed as cascaded buck-boost converters.

In embodiments, the phase converters are each implemented by a circuit in which a bridge arm is arranged between the positive DC input voltage rail and an associated output phase connection, a phase converter inductance is connected between a center point of the bridge arm and the negative DC input voltage rail, an output capacitance between the output phase connection and a common reference voltage rail is connected, which is connected to the DC input voltage rail.

In embodiments, an output diode is connected between the output phase connection and the reference voltage rail in each of the phase converters, which ensures a positive output phase voltage at the output phase connection with respect to the reference voltage rail be replaced. This means that the phase with the lowest voltage can be clamped for a third of the period (no switching losses for this phase) and the converter efficiency can be increased.

In embodiments, the control is designed to select a constant offset of the output phase voltages so large during operation of the converter at relatively small amplitudes of the output phase voltages that on the one hand a fluctuation in the output phase voltages caused by the load phase voltages to be generated symmetrically around a level of the DC Input voltage comes to rest, and on the other hand a double maximum amplitude of load phase voltages is not exceeded, this being achieved by lowering the offset at high amplitudes of the load phase voltages.

In the following, the subject matter of the invention is explained in more detail on the basis of preferred exemplary embodiments which are illustrated in the accompanying drawings. They show schematically: . Fig. 2: Converter system with the arrangement of a DC / DC step-up converter for each output phase, each phase converter having an input-side and an output-side bridge arm and a phase converter inductance, which is arranged between the bridge arms and is used for step-down and step-up converter operation. Fig. 3: Time curve of the phase converter output voltages to be generated when a three-phase machine is supplied for (Fig. 3.1) a temporally constant offset shift uoff of the load phase voltage system actually to be generated in the amount of the amplitude of the load phase voltage; (Fig. 3.2) with a constant offset shift and additional superimposition of an alternating component of the offset signal with three times the output frequency and a phase position such that the maximum value of the phase converter output voltages is minimized; (Fig.3.3) with offset shifting of the load phase voltage system to be generated in such a way that a setpoint value equal to zero is present for a phase converter output over a third of the output period, and this converter is therefore in the clamped state can remain. Fig. 4: Execution of the phase converters with quasi minimal complexity, whereby the output terminals of the phase converters show negative potential, and furthermore to enable a simple start-up of the system starting from the output terminals of the phase converter diodes are placed against the reference voltage rail. One diode in each case in parallel with an output capacitor can have a parallel switch; this enables the phase with the lowest voltage to be clamped over a third of the period, analogous to the circuit in FIG * the phase converter output voltages uout (where uout in a summarizing way denotes the individual voltages uan, ubn, ucn for the converter circuits according to FIG. in order to achieve a minimization of the switching frequency fluctuation of the current in the phase converter inductance (see Fig. 5.1). In Fig. 5.2 the time course associated with the converter circuit according to Fig. 4 is shown, which can also be used for the converter circuit according to Fig. 2 as an alternative to Fig. 5.1 2uMpk, max denotes that at maximum load phase voltage amplitude occurring maximum value of the phase converter output voltages uout; the associated time courses of uout are shown in dashed lines. Fig. 6: Device for regulating the output voltages of the phase converters in order to set a predetermined curve uM * of the load phase voltages uM, as is required for UPS systems or when supplying variable-speed three-phase machines. The regulation has the same structure for each phase and is only shown for one phase for reasons of clarity. Fig. 7: Device for regulating the DC output voltage formed in the interaction of all phase converters when the converter system is used as a three-phase pulse rectifier circuit, whereby a subordinate control ensures a sinusoidal curve of the line phase currents, each in phase with the associated line phase voltage. The regulation has the same structure for each phase and is only shown for one phase for reasons of clarity. Fig. 8: Modification of part of the control devices according to Fig. 6 and Fig. 7. Fig. 9: Alternative version of a part of the control circuit according to Fig. 6bisFig. 8th.

Each phase converter of the system (seeFig. 2) has an input-side bridge arm 3a, 3b, 3c between the positive DC input voltage rail 1 and the negative DC input voltage rail 2, which is connected in series to an upper, typically collector or drain side connected to the positive DC input voltage rail and a lower switch, typically connected on the emitter or source side to the negative DC input voltage rail, generally a power transistor, with a freewheeling diode connected in anti-parallel to both transistors and a common connection point (connection of the emitter or source connection of the upper and the collector or drain connection of the lower transistor) forms the bridge branch output 4a, 4b, 4c, from which a phase converter inductance La, Lb, Lc branches off, which with its second end to the input 5a, 5b, 5c of a further output itigen bridge branches 6a, 6b, 6c is placed, whereby the source connection of the lower switch or transistor of this bridge branch is connected to a reference voltage rail n and the drain connection of the upper transistor of this bridge branch is connected to the assigned output phase terminal a, b, c, whereby to ensure a smooth course of the output phase voltage between the output phase terminal and the reference voltage rail, a smoothing capacitance Ca, Cb, Cc is applied. The common for all phase converters reference voltage rail n is finally connected to the negative rail 2 of the DC input voltage, so that each phase converter has the structure of a step-up converter DC / DC converter and the entire three-phase DC / AC converter system advantageously only three inductors La, Lb, Lc has.

A three-phase load is connected with its phase terminals to the output phase terminals a, b, c of the three phase converters and has a free star point, so that only the chained phase converter output voltages (load outer conductor voltages), defined as the difference between two phase converter output voltages or that of a load phase converter The load phase voltage measured against a load star point determines the formation of the load phase currents.

The phase converter output voltages are generated in such a way that the setpoint values of the load phase voltages u_an, u_bn, u_cn, which typically run sinusoidally with an output frequency and form a symmetrical three-phase system, are shifted to positive values by means of an offset u_off that is constant over time in the simplest case (see Fig. 3.1), that every phase output voltage shows a unipolar curve, ie only positive values or minimally the value zero. As mentioned above, this offset is not effective in the load line voltages and therefore has no influence on the current generation of the load. In embodiments, a further offset with three times the output frequency and an amplitude and phase can be added to this constant offset in such a way that the unipolarity of the output phase voltages is ensured with a minimum value of the constant offset, thus reducing the voltage load on the transistors of the output-side bridge branches 6a, 6b, 6c the phase converter can be minimized with a defined load phase voltage amplitude to be generated (see Fig. 3.2).

With regard to the timing of the input and output-side bridge branches 6a, 6b, 6c of the phase converter, it should be noted that in areas in which a phase converter output voltage above the DC input voltage must be generated, the upper switch or power transistor of the input-side bridge branch 3a, 3b, 3c of a phase converter can remain switched through, and only the output-side bridge branch 6a, 6b, 6c is clocked. The voltage translation of the converter then corresponds to that of a step-up converter for power flow from the DC input voltage to the phase converter output voltage, with the phase converter inductance La, Lb, Lc as the step-up converter inductance, the lower power transistor of the output-side bridge arm 6a, 6b, 6c as the step-up converter transistor and the top parallel transistor acts as a boost converter freewheeling diode, with the upper power transistor always being switched through in embodiments, ie the power transistors of the output-side bridge arm 6a, 6b, 6c being operated in push-pull mode. Since anti-parallel diodes are arranged with all power transistors, a power flow can then also take place from the phase converter output voltage into the DC input voltage, the function of the phase converter in this case corresponding to that of a step-down converter located between the phase converter output voltage and the DC input voltage.

In areas in which a phase converter output voltage below the DC input voltage has to be generated, in embodiments the upper power transistor of the output-side bridge arm 6a, 6b, 6c of the phase converter is switched through, and the clocking is switched to the input-side bridge arm 3a, 3b, 3c limited. The voltage translation of the converter then corresponds to the power flow from the DC input voltage to the phase converter output voltage that of a buck converter, whereby the phase converter inductance acts as buck converter inductance, the upper power transistor of the input-side bridge arm 3a, 3b, 3c acts as buck converter transistor and the diode parallel to the lower power converter acts as a buck converter transistor. wherein in embodiments the lower power transistor is always switched through, ie the power transistors of the input-side bridge arm 3a, 3b, 3c are operated in push-pull mode. Since anti-parallel diodes are arranged with all power transistors, a power flow can then also take place from the phase converter output voltage into the DC input voltage, the function of the phase converter in this case corresponding to that of a step-up converter located between the phase converter output voltage and the DC input voltage.

With regard to the clocking of all phase converters, it should be noted that in embodiments the same clock frequency is selected for all phase converters and the clocking of the converters is synchronized in such a way that the push-pull voltage component contained in the phase converter output voltages, which is the switching-frequency currents and thus possibly high-frequency losses leads in the connected three-phase load, is minimized, ie switching-frequency changes in the phase converter output voltages are mainly formed as common-mode components, which cause a voltage shift of the same type compared to the reference voltage rail for all phase outputs.

For consumers who are particularly sensitive to high-frequency common-mode shifts, on the other hand, the phase converters operating again at the same clock frequency can be synchronized in such a way that the switching-frequency common-mode voltages are minimized, although a higher differential-mode component of the phase converter output voltages must then be accepted.

An alternative course of the offset in Fig.3.1undFig.3.2 is defined in such a way that an output phase voltage setpoint value equal to zero results for the phase converter whose assigned load phase voltage has the highest negative value (see Fig.3.3), so that this phase converter does not have to be clocked , or the associated output phase terminal can remain clamped to the reference voltage rail, which can be achieved for the phase converter topology described above (see Fig. 2) simply by simultaneously switching through the upper and lower power transistor of the output-side bridge arm 6a, 6b, 6c. The lower power transistor of the input-side bridge branch 3a, 3b, 3c is then also advantageously switched through. The course of the output voltage setpoints of the two other phase converters is then defined directly by the sections of the setpoints of the load external conductor voltages to be generated in relation to the clamped phase and to be formed by subtracting two load phase voltage setpoints each, so that overall a sinusoidal profile of all three load external conductor voltages is achieved again. Since the clamping is passed cyclically between the phases, each phase remains clamped for a third of the load phase voltage system when a sinusoidal symmetrical load phase voltage system is generated and thus without switching losses, which increases the efficiency of the energy transmission.

With regard to the implementation of the phase converter, it should be noted that in addition to the design described above, there are a number of advantageous modifications: In embodiments, the input and / or output-side bridge branch can advantageously be implemented in a multilevel structure, so for example as a flying capacitor multilevel bridge branch, which for The setting of the voltage translation between the DC input voltage and the phase converter output voltage means that a higher number of voltage levels is available, which means that the switching frequency ripple of the currents in the phase inductances is lower.

Furthermore, in embodiments, the phase converter can be implemented by several parallel, phase-shifted clocked systems, so that the current fed into the output capacitance and the current drawn from the DC input voltage advantageously has a higher effective frequency and a smaller fluctuation compared to a single system.

A converter system in embodiments with phase converters of relatively low complexity is shown inFig.4, with only one bridge arm between the positive terminal of the DC input voltage and the associated output or load phase terminal in each phase to implement the bidirectional DC / DC buck converter is arranged and the associated phase converter inductance is connected from the midpoint of the bridge arm to the reference voltage rail. Depending on the function, the reference voltage rail then has a positive potential or the output terminals of the phase converters show negative potential, which must be taken into account when specifying the setpoint values for the output phase voltages (i.e. the voltage is counted starting from the reference voltage rail against the phase terminals). In order to enable a simple start-up of the system, in embodiments, furthermore, starting from the output terminals of the phase converter, diodes can be placed against the reference voltage rail. Corresponding to a clamping circuit, when there is an active three-phase load or when a three-phase network is connected instead of a three-phase load, a polarity reversal of the phase converter output voltages is prevented and a positive output voltage is ensured in a wide interval of the output period without clocking the power transistors, which can be used to start up the system. In addition to each output diode, a switch can also be connected in parallel, or the output diode can be replaced by a switch with an anti-parallel output diode. Thus, as for the circuit according to FIG. 2, the phase with the lowest voltage can be clamped over a third of the period (no switching losses for this phase) and the converter efficiency can thus be increased.

It should be noted that for phase converters with an input and output-side bridge arm (seeFig.2), the free-wheeling diodes of the output-side bridge arm act as clamping diodes during startup and therefore no explicit additional diodes need to be provided.

For use of the system nachFig.2oderFig.4 for the supply of a three-phase machine (load) lying at the output phase terminals, different amplitudes of the load phase voltage or different amplitudes of the assigned phase converter output voltages are to be generated depending on the speed of the machine, typically at the highest speed highest amplitude values occur for which the power semiconductors of the output-side bridge arm are to be designed.

Advantageously, for the circuit according to FIG. 2, at low speeds or relatively small amplitudes of the phase converter output voltages, the constant offset can be selected so large that on the one hand the fluctuation in the phase converter output voltages caused by the load phase voltages to be generated symmetrically around the level of the DC Input voltage comes to rest, and on the other hand the double maximum amplitude of the load phase voltage assigned to the maximum speed is not exceeded, this being achieved by a corresponding lowering of the offset at high amplitudes of the load phase voltages. As shown in Fig. 5.1, the nominal values of the phase converter output voltages then typically have minimum values significantly greater than zero and the currents in the phase converter inductances show a relatively low ripple, since the input and output bridge branches then alternately operate with duty cycles close to one (i.e. each upper power transistors are switched through almost continuously) which is known to result in a low switching frequency fluctuation of the current in the phase converter inductance, which in turn is expressed in low high-frequency losses. Even taking into account the higher switching losses of the output-side bridge branch due to the higher switched phase converter output voltage, an improvement in the efficiency of the energy transmission can thus be achieved.

For the circuit according to FIG. 4, the phase converter output phase voltages are always as low as possible, in contrast to FIG Zero occurs (see Fig. 5.2). This is because the upper power transistors of the input-side bridge arms of the phase converters then have low relative switch-on times, which in turn results in a low fluctuation of the currents in the phase converter inductances.

A cascaded control of the three-phase converter system according to FIG. 2 is shown in FIG. The control circuit is of the same type for each phase and, for the sake of clarity, is only shown for one phase. As entered, voltages are measured against the reference voltage rail n or the negative rail DC- of the DC input voltage Uin.

The setpoint of a phase converter output voltage uout * is formed by adding the typically sinusoidal running setpoint uM * of the associated load phase voltage uM of a fed three-phase load (e.g. an electrical machine M) and the setpoint uoff * of the offset uoff, which is the same for all phases, which is typically by Addition of a component uoffDC * that is constant over the output period and a component uoffAC * that fluctuates at three times the output frequency is generated. The time course of uoff * is advantageously chosen in such a way that uout * remains limited to the lowest possible values for a specified load phase voltage system uM * to be generated, which also minimizes the blocking voltage stress and the switching losses of the output-side bridge branches BB of the phase converters. This includes a specification of uoff * such that a phase converter remains in the clamped state for a third of the output period, i.e. uout * has correspondingly wide intervals with uout * = 0.

The phase converter output voltage setpoint uout * is compared with the measured actual value of the phase converter output voltage and the control deviation Deltauout is fed to a phase converter output voltage regulator Ruout, at the output of which the output capacitor required to correct Deltauout the output capacitor current setpoint iCout * measured, which is formed by a pre-load current control of the measured iCout * i of the output-side bridge arm BB of the phase converter is determined, which can be converted into a target value iL * of the current iL in the phase converter inductance L by dividing it by the relative switch-on duration dB of the upper transistor T3 of this bridge arm. By comparing iL * with the measured actual value iL, the control deviation DeltaiL of the current in L is then formed and fed to a phase inductance current controller RiL, which at its output forms the setpoint uL * of the voltage to be applied to L, which is required to correct the control deviation DeltaiL.

Based on the assumption of an operation with continuously switched through upper transistor T3 of the output-side bridge arm BB, which is characterized by the occurrence of uout at the input terminal B of BB and thus also at the output end of L, the setpoint is then uA * the to be applied to the input-side end A of L or to be obtained at the output A of the input-side bridge branch BA voltage uA by adding uL * and uout. The duty cycle dA, i.e. the relative switch-on duration of the upper transistor T1 of BA, is then simply obtained in the sense of a buck converter function from BB by dividing uA * and the actual value of the DC input voltage Vin.

Since dA is limited to values between zero and one, uA * is to be limited accordingly upwards by Uin and downwards by the value zero. As a result of this limitation, the relative switch-on duration of the bridge branch BB can also advantageously be generated in a simple manner by subtracting the measured DC input voltage Uin from uA *. The difference Delta uA * obtained in this way is limited at the bottom by the value zero and at the top by uout, which corresponds to the physically adjustable limits of uA. If a positive value DeltauA * now occurs, this ultimately means that BB cannot generate the voltage value uL * to be generated via L for correct current control, even with maximum modulation of BA with dA = 1 or uA = Uin. Correspondingly, the input B of BB must then no longer have the duty cycle dB = 1 or T3 must no longer remain permanently in the switched-through state as assumed above. The voltage of input B is therefore to be reduced by DeltauA *, or ultimately a setpoint uB * of the voltage to be generated at B must be formed by subtracting the limited value of uA * from uout, with the duty cycle dB of BB then with a view to the buck converter function from BB from uout to uB by dividing uB * by uout.

For values of the DC input voltage Uin above uout *, the converter system will then predominantly work in buck converter mode, i.e. with BA clocking, BB will remain continuously switched on with dB = 1 or T3. Only in the case of rapid transient changes in uout * or iLoad will a timing of BB occur temporarily.

However, the control circuit according to FIG. 6 can also operate for voltages Uin <uout, since the activation of the bridge branches BA and BB is derived directly from the setpoint uL * and the actual values uout and Uin. The control circuit can therefore be used independently of the respective ratio of Uin and uout * and can also be used for both power flow directions, i.e. for feeding a motor M from Uin or feeding back braking energy from the motor M in Uin.

The control signals of the push-pull bridge arms BA and BB are obtained on the basis of dA and dB by appropriate pulse width modulation.

As mentioned above, the converter circuit can be used on the one hand to feed an electrical machine M, but on the other hand also as a three-phase rectifier system with advantageously sinusoidal mains currents iN and a DC output voltage Uout regulated to a constant value.

As shown in FIG. 7, the positive outputs of the phase converters are then to be connected to the positive terminal DC + of an output capacitor Cout common to all phases, the negative rail of which is to be connected, using the terms introduced in connection with FIG. 6 as far as possible DC- is connected to the reference voltage rail n, against which the input-side bridge branches BA are connected. Furthermore, the forFig. All the inputs of the bridge arms BA of the phase converters that are connected to the positive terminal of the DC input voltage are now carried out separately and fed to the terminals aN, bN, cN of the three-phase network N via phase series inductances LN. Furthermore, in each phase converter a filter capacitor Cin is connected in parallel to the respective input-side bridge arm BA from the respective input terminal a, b, c to the reference voltage rail n common to all phase converters.

For the regulation of Vout, the difference between the DC output voltage setpoint Uout * and the measured value uout is formed and the control deviation Deltauout is fed to an output voltage regulator Ruout common to all phase converters, which has the current setpoint iCout required for a corresponding change in charge of Cout at its output * forms, to which the measured value iLoad of the current flowing to a DC load RLoad is advantageously added in order to obtain the setpoint iout * of the total output current iout to be formed by the parallel connection of the phase converters (sum of the output currents i of the output-side bridge branches BB). By multiplying by Uout *, a nominal value pout * of the converter output power is obtained and assuming a symmetrical and sinusoidal curve of the line phase voltages uN by dividing by the three times the square of the amplitude UNpk of a line phase voltage and dividing by 2, 3/2 UNpk ^ 2, into the Setpoint of an equivalent conductance G * of the phase branches of an equivalent star circuit, which is to be represented by the converter system for the network in order to ensure an ohmic network behavior, converted. By multiplying G * with the measured value of the assigned mains phase voltage uN, the setpoint iN * of the mains phase current iN to be drawn from the respective phase converter can then be obtained, from which the measured value iN of the mains phase current is subtracted to obtain a control deviation DeltaiN, which a mains current regulator RiN is supplied, which at its output generates the setpoint uLN * of the voltage uLN to be generated across the associated phase inductance LN, which is to be subtracted from uN in order to obtain the setpoint uinY * of the phase voltage uinY to be generated at the input of the phase converter opposite the network star point Y, to which a setpoint value of an offset, uoff, which is the same for all phases, is added in order to obtain the setpoint value uin * of the phase converter input voltage uin related to the reference voltage rail n. The offset setpoint uoff * is typically generated by adding a component uoffDC * that is constant over the network period and a component uoffAC * that fluctuates with three times the network frequency and is designed in such a way that uin * for a specified network phase voltage system uN is limited to the lowest possible values, which also means that the reverse voltage stress is limited and the switching losses of the input-side bridge arms of the phase converters are minimized. This includes a specification of uoff * in such a way that in each case a phase converter remains in the clamped state for a third of the output period, the assigned uin * then having correspondingly wide intervals with uout * = 0.

The phase converter input voltage setpoint uin * is then compared with the measured actual value of the phase converter input voltage uin and the control deviation Deltauin is fed to a phase converter input voltage regulator Ruin, at the output of which the input capacitor current setpoint iN * is subtracted from the associated setpoint current iN * of the associated network * in order to obtain the setpoint iin * of the input current iin of the input-side bridge arm BA of the phase converter. The nominal value iL * of the current iL in the phase converter inductance L can then be obtained by dividing iin * by the relative switch-on duration dA of the upper transistor of BA. The comparison (subtraction) of iL * with the associated measured value iL then leads to the control deviation DeltaiL of the current in L, which is fed to a phase inductance current controller RiL, which at its output sets the setpoint uL * of the voltage uL to be applied to L to correct the control deviation DeltaiL forms. The rest of the control circuit between iL * and the relative switch-on times dA and dB of the bridge branches BA and BB is the same as for the circuit according to Fig. 6, which is why a description can be dispensed with here.

The control circuit nachFig.6undFig.7 is based on a buck converter operation of the input-side bridge arm BA and a switched-through state of the transistor T3 of the output-side bridge arm BB as regular operation, but also the case of an output voltage of a phase converter above the input voltage, ie the boost converter operation will.

Alternatively, the step-up converter operation of the converter, i.e. a permanent through-connection of T1 and timing of the bridge arm BB, can also be viewed as regular operation, which results in the alternative embodiment of part of the control circuits shown in FIG. The other parts of the control circuits remain unchanged. The following description is therefore limited to the part of the devices already described that is to be replaced.

To determine the relative switch-on times of the bridge branches BA and BB, the setpoint uL * is inverted and then this physically directed voltage -uL * from the output side to the input side is added to the input voltage uin of the phase converter and thus the voltage setpoint to be set at input B of BB transmitted. After limiting to uout upwards and zero downwards - it is only possible to set duty cycle dB between zero and one - the duty cycle, i.e. the relative switch-on duration of the upper transistor T3, is obtained from BB.

In order to be able to set the required voltage uL * even if uB * exceeds the value uout, the difference delta uB * from uB * and uout is also determined and after limitation with uin upwards and zero downwards from the input voltage uin subtracted. This follows the consideration that in order to set a setpoint value uL * which leads to uB * = uout or db = 1, the output A of the bridge arm BA must be detached from the input voltage and reduced in terms of potential by appropriate timing. The pulse duty factor dA then to be set can then be obtained simply by dividing uA * by uin.

For values of the input voltage uin below uout, the converter system will then predominantly work in step-up converter operation, i.e. with BB timing, BA will remain switched on continuously with dA = 1 or T1. Only in the case of rapid transient changes in uin * or iLoad will BA clocking occur temporarily. However, the control circuit can also operate for voltages uin> uout, since the activation of the bridge branches BB and BA is derived directly from the setpoint uL * (and the actual values uin and uout). The control circuit is therefore advantageous regardless of the respective ratio of uin and uout and also for both power flow directions, ie for feeding a motor M from uin, or for implementing a photovoltaic inverter for feeding photovoltaically generated power into the grid (uin then represents the voltage of the solar panel) or for the feeding back of braking energy of a three-phase motor M into the DC input voltage uin, or for the operation of the device as an active three-phase rectifier system (generation of a DC output voltage uout) can be used.

An alternative embodiment of a part of the control circuit according toFig.6, which favors both operating modes, ie buck and boost operation, equally for calculating the duty cycle dA and dB, in contrast to the two control concepts according toFig.6bisFig.8, is inFig. 9 shown. On the one hand, a buck operation is assumed for the bridge branch BA, i.e. it is assumed that the bridge branch BA is clocked and, on the other hand, a boost operation is assumed for the bridge branch BB, i.e. it is assumed that the bridge branch BB is clocked. In order to obtain the setpoint voltage uA * of the bridge arm BA, the setpoint uL * is added to the output voltage uout and limited to uin at the top and to zero at the bottom. Conversely, for the calculation of the setpoint voltage uB * of the bridge branch BB, the setpoint uL * is subtracted from the input voltage uin and limited upwards to uout and downwards to zero. Through this mutual offsetting of the output voltage uout into the target voltage uA * and the input voltage uin into the target voltage uB * and the corresponding limitation to the possible setting range, the two operating modes are ultimately excluded from each other, i.e. the converter finally works either in the pure buck or pure boost operation. The pulse duty factor dA and dB to be set can then be obtained simply by dividing uA * by uin or uB * by uout.

Claims (22)

1. Converter for the transmission of electrical energy between a direct voltage or DC system and an alternating voltage or AC system, having on the DC voltage side a positive DC input voltage rail (1) and a negative DC input voltage rail (2) and on the AC voltage side at least two output phase connections (a, b, c), wherein for each of the output phase connections (a, b, c) a phase converter (10a, 10b, 10c) is present, which on a first side to the positive DC input voltage rail (1) and the negative DC input voltage rail (2) and on a second Side is connected to this output phase connection (a; b; c) and is designed as a step-up converter and has an input-side step-down converter part, also called the input-side bridge arm (BA), and an output-side step-up converter part, also called the output-side bridge arm (BB), and wherein the converter has a control which is designed to generate each of the phase converters (10a, 10b, 10c) as a function of a ratio of a DC input voltage to instantaneous values at the output phase connections (a, b, c) when the converter is in operation Output phase voltages, to operate temporarily either as a pure step-down converter or as a pure step-up converter. 2. Converter according to claim 1, wherein the control is designed to switch the switches of the phase converter (10a, 10b, 10c) temporarily to the input-side bridge branch (BA) during operation of the converter in each of the phase converters (10a, 10b, 10c) or to be restricted to the bridge arm (BB) of the phase converter (10a, 10b, 10c) on the output side. 3. Converter according to claim 1, or 2 wherein the control is designed to perform the clocking of all phase converters (10a, 10b, 10c) during operation of the converter such that the same clock frequency is present for all phase converters (10a, 10b, 10c) and one Synchronization of the clocking of the phase converter minimizes a push-pull voltage component contained in the output phase voltages. 4. Converter according to claim 1 or 2, wherein the control is designed to perform the clocking of all phase converters (10a, 10b, 10c) during operation of the converter in such a way that the same clock frequency is present for all phase converters (10a, 10b, 10c) and one Synchronization of the clocking of the phase converter minimizes a common-mode voltage component contained in the output phase voltages. 5. Converter according to one of the preceding claims, wherein the control is designed to specify an offset for the formation of output phase voltage setpoints from load phase voltage setpoints when the converter is in operation, in such a way that that in each case in a time segment for that phase converter (10a, 10b, 10c) whose assigned load phase voltage setpoint has the highest negative value, an output phase voltage setpoint equal to zero results, so that this phase converter (10a, 10b, 10c) does not have to be clocked and its output phase connection (a ; b; c) can remain clamped to a reference voltage rail (s), and The course of the output phase voltage setpoints of unclamped load line voltages from the phase converters is defined by setpoint values of load line voltages generated by the output phase connections by subtracting two load phase voltage setpoints in this time segment, so that overall there is a sinusoidal course of all load line voltages. 6. Converter according to one of claims 1 to 4, wherein the control is designed to select a constant offset of the output phase voltages in one mode of operation of the converter so large that on the one hand a fluctuation in the output phase voltages caused by the load phase voltages to be generated symmetrically around a level of DC input voltage comes to rest, and on the other hand a double maximum amplitude of load phase voltages is not exceeded, this being achieved by lowering the offset at high amplitudes of the load phase voltages. 7. Converter according to claim 6, wherein the control is designed to superimpose a third harmonic in addition to the constant offset. 8. Converter according to one of the preceding claims, wherein the phase converters (10a, 10b, 10c) are each designed as a cascaded step-down converter. 9. Converter according to one of claims 1 to 5, wherein the phase converters (10a, 10b, 10c) are each implemented by a circuit in which the input-side bridge arm (BA) between the positive DC input voltage rail (1) and an associated output phase connection ( a; b; c), a phase converter inductance (La, Lb, Lc) is connected between a midpoint of the input-side bridge arm (BA) and the negative DC input voltage rail (2), an output capacitance (Ca, Cb, Cc) between the Output phase connection (a; b; c) and a common reference voltage rail (n), which in the case of the dependency of claim 5 is the same as the reference voltage rail mentioned in claim 5, is connected, which is connected to the DC input voltage rail (2). 10. Converter according to claim 9, wherein in each of the phase converters (10a, 10b, 10c) an output diode (Da, Db, Dc) is connected between the output phase connection (a; b; c) and the reference voltage rail (s), which has a positive output phase voltage at the output phase connection (a; b; c) with respect to the reference voltage rail (s). 11. Converter according to claim 10, wherein in the phase converters (10a, 10b, 10c) in each case parallel to the output diode (Da, Db, Dc) a switch is connected in anti-parallel or is replaced by a bidirectional switch. 12. Converter according to claims 9 and 11, wherein the control is designed to always select a constant offset of the output phase voltages equal to the amplitude of the load phase voltage when the converter is in operation. 13. Converter according to one of claims 9 to 12, wherein the control is designed to superimpose a third harmonic in addition to the constant offset when the converter is in operation, the ratio of constant offset and the amplitude of the third harmonic being freely selectable, and however the sum of the two components is always chosen so that the minimum output phase voltage just reaches the potential of the negative DC input voltage rail. 14. Converter according to claim 11, wherein the control is designed to specify an offset for the formation of output phase voltage setpoints from load phase voltage setpoints during operation of the converter, in such a way that in each case in a time segment for that phase converter (10a, 10b, 10c) whose assigned load phase voltage setpoint the has the highest negative value, an output phase voltage setpoint value equal to zero results, which means that this phase converter (10a, 10b, 10c) does not have to be clocked and its output phase connection (a; b; c) can remain clamped to the reference voltage rail (s), and the profile of the output phase voltage setpoints of unclamped phase converters is defined by setpoints of load external conductor voltages to be generated with respect to the clamped output phase connection and generated by subtracting two load phase voltage setpoints in this time period, so that overall a sinusoidal profile of all loads conductor voltages exist. 15. Converter according to one of claims 1 to 8, wherein the control is designed to operate the converter starting from a step-down converter operation of the converter as regular operation, with clocking of one of the input-side bridge branches (BA) with the upper switch (T3) turned on one of the output-side Bridge branches (BB) to generate a three-phase load phase voltage system uM * when the converter is fed by a DC input voltage Uin, with a control circuit automatically changing between the step-down and step-up mode of the phase converter. 16. Converter according to one of claims 1 to 8, wherein the control is designed to operate the converter starting from a step-down converter operation of the converter as regular operation, with clocking of one of the input-side bridge branches (BA) with the upper switch (T3) switched on one of the output-side Bridge branches (BB) to operate the converter as a three-phase pulse rectifier system, which generates a regulated DC output voltage and draws sinusoidal currents from a network, the control circuit making an automatic change between buck and boost converter operation of the phase converter. 17. Converter according to one of claims 1 to 8, wherein the control is designed to, when the converter is in operation, starting from a step-up converter operation of the converter, with an upper transistor (T1) remaining on, one of the input-side bridge branches (BA) and clocking one of the output-side Bridge branches (BB) as regular operation, whereby a setpoint uL * is inverted to determine the relative switch-on times of the input and output-side bridge branches (BA, BA) and then this voltage -uL *, which is physically directed from the output side to the input side, is added to the input voltage uin of the phase converter and so the voltage setpoint uB * to be set at input B of the output-side bridge arm (BB) is determined, and after limiting to uout upwards and zero downwards, the duty cycle, i.e. the relative duty cycle of the upper transistor (T3) of the output-side bridge arm (BB), is obtained becomes, and then to the required voltage uL * can also be set if uB * exceeds the value uout, the difference Delta uB * from uB * and uout is also determined and, after limiting with uin upwards and zero downwards, subtracted from the input voltage uin, this being based on the consideration, that in order to set a setpoint uL * which leads to uB * = uout or db = 1, the output of the input-side bridge arm (BA) has to be detached from the input voltage and reduced in terms of potential by means of appropriate timing, whereby the pulse duty factor dA then to be set by dividing uA * is obtained by uin. 18. Converter according to one of claims 1 to 8, wherein the control is designed to operate the converter starting from both operating modes of the converter as regular operation, by mutually offsetting the output voltage uout into the target voltage uA * and the input voltage uin into the target voltage uB * and the corresponding limitation to the possible setting range, depending on the target voltage uL * and the two voltages uin and uout, the correct operating mode, ie to determine either pure buck or pure boost operation. 19. Converter according to one of claims 1 to 8, wherein the control is designed to form a switching frequency triangular or trapezoidal current in the phase converter inductance (La, Lb, Lc) when the converter is in operation, such that when a transistor is switched off A correspondingly directed current is always available for charging a parasitic capacitance of the switching-off transistor and discharging the parasitic capacitance of a subsequent switching-on transistor, so that the switching-on of the subsequent transistor is de-energized and thus low-loss or ideally loss-free switching is ensured, in particular for Current shaping the input-side and the output-side bridge arm (BA, BB) of a phase converter are clocked at the same time. 20. Converter according to claim 2 or one of claims 3 to 8 as a function of claim 2, wherein the control is designed to operate the step-up converter DC / DC converter synchronously when the converter is in operation, with the same switching frequency and a carrier signal of a modulation of this type that a current load of a feeding DC voltage is minimized by the fact that current pulses received by the individual input-side bridge branches (BA) are superimposed in such a way that overall there is a relatively low switching frequency fluctuation of the total input current taken from the DC voltage. 21. Converter according to one of claims 1 to 10, wherein the control is designed to work with a supply voltage in the form of a rectified but not smoothed single-phase alternating voltage, hereinafter referred to as magnitude sinusoidal voltage, when the converter is in operation. If the mean value of the magnitude sinusoidal voltage extends over a clock period, a proportional, i.e. also sinusoidal, current is drawn, and on the other hand, output voltages are formed by the phase converters (10a, 10b, 10c) in such a way that a symmetrical sinusoidal line-to-line voltage system is present for the three-phase load, with the output capacitors (Ca, Cb, Cc) can be used to compensate for a difference between the constant power delivered to a three-phase load and the double-frequency fluctuation of the power drawn from a network in such a way that a simultaneous equal Er increase or decrease of all output voltages by adding an offset and thus the energy stored in output capacitances (Ca, Cb, Cc), which in the case of the dependency of claim 9 are equal to the output capacitances mentioned in claim 9, is increased or decreased, whereby the output line-to-line voltages remain unchanged. 22. Converter according to one of claims 1 to 10, wherein the control is designed to work when the converter is in operation with an electrical consumer adjustable in terms of phase shift of consumer voltage and consumer current, the phase shift being selected so that one is used for reloading output capacities (Ca, Cb, Cc), which in the case of the dependency of claim 9 are equal to the output capacitances mentioned in claim 9, required reactive power is compensated and therefore does not have to be supplied via the phase converter inductances (La, Lb, Lc), which reduces the current load of the Power semiconductors the phase converter (10a, 10b, 10c) and the phase converter inductances (La, Lb, Lc) is achieved.