CH715813A2 - Method for regulating a three-phase pulse rectifier system with an intermediate circuit. - Google Patents

Abstract

The invention relates to a method for regulating a three-phase pulse rectifier system (1, 2, 3) with a three-phase bridge circuit (2), an intermediate circuit inductance (L), and a load converter (3). In chronologically successive sections, the following is carried out in one section: • In that bridge branch, hereinafter referred to as the selected bridge branch, the three-phase bridge circuit (2) to which the network phase with the largest phase current, hereinafter referred to as the selected network phase, is assigned this network phase is optionally connected depending on the polarity of the phase current with a switch of the selected bridge arm, hereinafter referred to as selected switch, a positive connection point (p) or a negative connection point (n) of the three-phase bridge circuit (2), this network phase with a positive phase current is connected to the positive and, in the case of a negative phase current, to the negative connection point, and remains connected for the duration of this section. • In the other two, unselected bridge branches, the corresponding positive or negative connection point is alternately connected to the two unselected phases by clocking the switches opposite the selected switch. The invention also relates to a device for regulating a three-phase pulse rectifier system (1, 2, 3).

Description

The invention relates to the field of three-phase pulse rectifier systems, in particular to a method for regulating the input phase currents to sinusoidal shape and the DC output voltage.

For converting the voltage of the three-phase network into a DC voltage whose DC value is below the minimum value of the rectified linked three-phase voltage, as is e.g. is required when charging the battery of electric vehicles, active three-phase pulse rectifier systems with buck converter characteristics are generally used according to the prior art.

The input terminals, i.e. the center taps, a bidirectionally lockable three-phase bridge circuit connected directly to the mains terminals, the individual switching elements of the three bridge branches e.g. can be realized by the anti-series connection of a unidirectional blocking component and a diode, the antiseries connection of two unidirectional blocking components, or a bidirectional blocking component.

By appropriate timing of the bridge branches, which have the function of switching the input voltage lying at the midpoint to either the positive or negative output voltage rail, is now at the output of the three-phase bridge circuit, i. between the positive and negative output voltage rail, a switched DC voltage is generated whose mean value just coincides with the DC voltage to be generated, but whose instantaneous value corresponds in sections to one of the possible chained input voltages depending on the selected pulse pattern. To smooth the switched DC voltage to a constant DC output voltage with the same mean value, a low-pass filter consisting of an output inductance and a DC backup capacitance is therefore arranged at the output terminals of the three-phase bridge circuit.

Clocking is understood to mean high-frequency switching of the converters or their power switches, in contrast to the low-frequency curve of the mains voltages. A corresponding clock frequency is also called a switching frequency; its reciprocal value is a clock period.

In the sense of low network perturbations, an input current profile proportional to the network voltage is advantageously set by appropriate selection of the pulse pattern. The three-phase pulse rectifier system in this case behaves like a three-phase resistance load and thus draws constant power from the three-phase network, i.e. When regulating to a constant DC output voltage, an average constant DC inductance current or intermediate circuit current flows in the output inductance.

Thus, the clocking of the bridge branches can also be understood as switching the constant DC inductance current to the three input phases, the pulse pattern being selected so that the division of the DC inductance current at the center taps of the three-phase bridge circuit leads to three input currents proportional to the mains voltage at a low frequency. By switching the DC inductance current, however, pulse-shaped phase currents are drawn from the center taps of the three-phase bridge circuit at switching frequency, which is why input capacitors are arranged in star or delta connection to smooth the phase currents at the input of the three-phase pulse rectifier system.

Alternatively, an input current curve with a defined phase shift relative to the mains voltage can also be set in a certain range.

If there is also the possibility of forming a higher output voltage in the underlying application, a DC / DC step-up converter stage is to be arranged downstream of the system, which results in a two-stage three-phase step-up converter pulse rectifier system, with the output inductance of the three-phase rectifier as the inductance of the step-up converter stage - buck converter stage is used, ie the bridge arm of the step-up converter stage is arranged between the output inductance of the three-phase rectifier step-down converter stage and the DC backup capacitance and thus the inductance as a DC intermediate circuit inductance forms a DC current intermediate circuit (see FIG. 1).

If the step-up converter stage is bidirectional, power supplied by an active load can then also be fed into the DC intermediate circuit between the two converter stages and from there power can be fed back into the network. This company is e.g. when feeding photovoltaically generated power into the three-phase network or when feeding a three-phase machine from a DC voltage.

For a compact implementation, it is advantageous in both cases to provide a high clock frequency of the converter stages, which, however, results in relatively high switching losses which reduce the efficiency of the energy conversion. Furthermore, a relatively high control power is required for the high-frequency clocking of the electronic switches, which also impairs efficiency.

The object of the invention is therefore to create a method for the regulation and modulation of a two-stage three-phase step-up converter pulse rectifier system, which has reduced switching losses, while still a sinusoidal, advantageously in phase or in phase opposition to the mains voltage and a constant output voltage should be ensured.

[0013] The object is achieved by a control method according to the claims.

The method is used to control a three-phase pulse rectifier system, which has a three-phase bridge circuit for power exchange between a three-phase network and a DC link inductance, and a load converter, for exchanging power between the DC link inductance and a load.

The bridge branches of the three-phase bridge circuit are arranged for switching phase currents flowing through the intermediate circuit inductance, with one section in each case in successive sections, each lasting one sixth of the period of the three-phase network <tb> • <SEP> in that bridge branch, hereinafter referred to as the selected bridge branch, of the three-phase bridge circuit to which the network phase with the largest phase current in terms of magnitude, hereinafter referred to as the selected network phase, is assigned, this network phase optionally depending on the polarity of the phase current a switch of the selected bridge branch, hereinafter referred to as selected switch, is connected to a positive connection point or a negative connection point of the three-phase bridge circuit, this network phase being connected to the positive connection point when the phase current is positive and to the negative connection point when the phase current is negative, and for the duration remains connected to this section, <tb> • <SEP> in the other two, unselected, bridge branches by clocking the switches opposite the selected switch, the corresponding positive or negative connection point is alternately connected to the two unselected phases.

In the selected bridge branch so the unselected switch remains open for the entire duration of the section, so non-conductive. There is therefore no freewheeling of the intermediate circuit current through a bridge branch. Neither the selected switch nor the opposite one in the same phase are clocked. Switching losses and a control power requirement, which would occur with clocking, are avoided.

These advantages can also be viewed as a consequence of the choice that the current through the intermediate circuit inductance in the time segment is equal to the phase current. Instead of a conventional regulation of this current to a constant value, a six-pulse course of this current results over an entire period of the three-phase system.

[0018] The current through the selected switch flows through the intermediate circuit inductance. Conversely, the entire intermediate circuit current also flows through the selected switch. The intermediate circuit current flows back through the other two phases and is divided between these two other phases by means of the two opposite switches.

By only switching these two opposite switches (alternately) to the positive or negative connection point, the number of switchings can be halved in one clock period and larger voltage jumps can be avoided.

As opposed switches, the upper switches are understood with respect to a lower switch, and vice versa. If, for example, the lower switch of the first bridge branch is the selected switch, then the opposite switches in the unselected bridge branches are the same as the upper switches in the second and third bridge branches.

In embodiments, a sinusoidal phase current is set in each case in a time segment by the clocking in each of the other two, unselected, bridge branches.

In embodiments, the load converter uses clocking to set a voltage at a load converter-side connection of the intermediate circuit inductance which, in cooperation with a switched DC voltage formed by the three-phase bridge circuit, results in a predetermined intermediate circuit current at the other, bridge-side connection of the intermediate circuit inductance.

Here and in the following, for the sake of simplicity, the AC voltage side or network side is regarded as the input, and the DC voltage side as the output. A power flow can not only take place from the input to the output but also vice versa. If the circuit is to allow power flow in both directions, the circuit breakers used are usually also bidirectionally conductive and switching, i.e. they can lead currents through the switch in both directions and switch them on or off. If a power flow is to be realized in only one direction, unidirectional conducting and switching circuit breakers can be used.

In the following, the subject matter of the invention is explained in more detail with reference to preferred exemplary embodiments which are illustrated in the accompanying drawings. They each show schematically: <tb> <SEP> Figure 1: Power section of the system, the input section being designed as a bidirectional blockable three-phase bridge circuit and a load converter as a DC / DC boost converter. <tb> <SEP> Figure 2: Current curves of the network input currents (ia, ib and ic) and the intermediate circuit current iL. The subdivision into the six current sectors and the allocation of the network currents to the intermediate circuit current (iL) takes place depending on the current ratios of the network input currents, whereby the intermediate circuit current (iL) always corresponds to the largest network input current (ia, iboder ic). <tb> <SEP> Figure 3: Voltage curves of the mains input voltages (ua, ub and uc) and the switched direct voltage ubu in the third sector at time (t1) for the conventional control method. The course of the switched DC voltage ubu has four voltage intervals, starting with a free-running interval (ucc), i.e. A total of four switchovers are necessary during one switching period. <tb> <SEP> FIG. 4: Exemplary voltage curves of the network input voltages (including, ub and uc) and the switched direct voltage ubu in the third sector at time (t1) for the inventive control method. The course of the switched DC voltage has only two voltage intervals, i.e. during one switching period, the number of switchings can be reduced to two. <tb> <SEP> FIG. 5: (composed of FIGS. 5a and 5b) Realization of the circuitry of the method for regulating and modulating the system according to FIG. 1. <tb> <SEP> Figure 6: Alternative design of the load converter as an active current-impressing series element in the form of a switching cell, i.e. The load converter is a full-bridge switching cell which is arranged in the connection line between the positive output voltage rail of the three-phase bridge branch and the positive output voltage terminal and actively forms the intermediate circuit current via appropriate timing. <tb> <SEP> Figure 7: Alternative design of the load converter as a pulse converter, in particular as a pulse inverter, for the direct supply of a machine M.

In the intermediate circuit, instead of a constant current, the intermediate circuit curve (iL) is regulated in such a way that a six-pulse current is established over a network period, the instantaneous value of which corresponds to the largest phase current in terms of magnitude (see Figure 2). Thus, within an input current sector, the bridge arm belonging to the largest phase current can be switched through depending on the polarity of the largest phase current, i.e. the upper switch remains switched on for a positive phase current and the lower switch remains switched on within an input current sector for a negative phase current, and this bridge branch can be switched to freewheeling, i.e. simultaneous switching on of the upper and lower switch can be prevented.

In contrast to a conventional implementation with constant current in the intermediate circuit, the degree of freedom with regard to the choice of the intermediate circuit current curve is used, the largest phase current being formed by changing the current in the intermediate circuit over time instead of by pulse width modulation of all phases. The method according to the invention thus avoids clocking the bridge arm with the largest phase current in terms of magnitude, which advantageously ensures lower switching losses and a lower control power requirement (see FIG. 2).

Furthermore, a continuous current curve is achieved within an input current sector for the largest phase current in terms of magnitude, which advantageously leads to lower EMC interference emission and thus better EMC behavior.

Since pulse rectifier systems typically have no connection to the network star point (m), the sum of the phase currents is forced to zero or the largest phase current flows back as a sum over the two other phases. Since in the method according to the invention the bridge branch with the largest phase current is not clocked, the division of the largest phase current to the two other phases is carried out exclusively by switching between the two remaining bridge branches instead of switching between all bridge branches, whereby the conduction duration of the two switching intervals can be divided in this way that a sinusoidal phase current curve is also achieved in the other two phases (see Figure 2).

Based on conventional control with a symmetrical pulse pattern, in this case the switched DC voltage at the output of the three-phase bridge circuit consists of only two instead of three concatenated input voltages, i.e. two instead of three voltage levels, which means that the number of switchings in one clock cycle can be halved from four to two compared to the conventional method. Advantageously, the largest voltage jump can be avoided both times, which results in lower switching losses and a lower switching-frequency current ripple in the intermediate circuit inductance (see Figures 3 and 4).

This situation is explained below for the conventional method as well as the method according to the invention, assuming ohmic network behavior using the example of the third input current sector, in which the largest phase current in terms of amount flows in phase (c).

While in the conventional method, the intermediate circuit current is kept constant and at least at the peak value of the input phase currents and thus all phase currents are always smaller than the intermediate circuit current during an entire network period or up to six discrete points in time, all three bridges must be clocked to to achieve a sinusoidal course of all phase currents. As shown by way of example in FIG. 3 for time (t1), the switched direct voltage (ubu) is then composed of four voltage intervals, assuming a symmetrical pulse pattern, with the upper and lower switches belonging to phase (c) beginning with a free-running interval (ucc) Bridge branches are switched on and then only the upper switch of phase (b) or (a) is switched on for the two active linked voltages (ubc) and (uac).

If the intermediate circuit current (iL) according to the method according to the invention is regulated to a six-pulse course corresponding to the magnitude of the largest phase current, the freewheeling interval (ucc) can then be dispensed with, as shown for the same point in time (t1) in FIG the switched direct voltage (ubu), assuming a symmetrical pulse pattern, is composed of only two voltage intervals, ie the two active interlinked voltages (ubc) and (uac) whereby only the upper switch of phase (b) or (a) is switched on and the lower switch of phase (c) remains switched on permanently.

It should be noted that in the conventional method, although the lower switch of the bridge arm belonging to phase (c) also remains permanently switched on, but the upper switches change between all three phases during a switching period, while in the method according to the invention the upper switches only between two Change phases and thus the intermediate circuit current (iL) flows back through phase (c) during the entire interval shown in FIG. According to the example, the pulse pattern and the switched voltage for the other sectors are carried out by cyclically interchanging the phases.

It should be noted that temporal fluctuations in the intermediate circuit current (iL) can be compensated for by appropriate pulse width modulation of the downstream load converter, for example a step-up converter stage, i.e. a constant output voltage (uo) can still be generated. In particular, the load converter can be used to set the voltage (ubo) at the load converter-side connection of the intermediate circuit inductance in such a way that the desired intermediate circuit current (iL) results in interaction with the voltage at the other connection on the bridge circuit side (towards the bridge circuit, i.e. the switched direct voltage ubu) . The switched direct voltage ubu is specified by the mains voltages and the switching states of the three-phase bridge circuit (2). The desired intermediate circuit current (iL) should - since it is in sections equal to one of the phase currents - follow the six-pulse curve mentioned.

It should be noted that the two-stage three-phase step-up converter pulse rectifier system is not limited to a pure step-up converter function, but can also be operated as a step-down converter. In this case, the upper switch of the step-up converter on the output side must be switched through so that the output voltage (uo) corresponds to the mean value of the switched direct voltage at the output of the three-phase rectifier (ubu); the active three-phase bridge is then operated as a conventional buck converter, with more than two bridge branches to be clocked to regulate a constant intermediate circuit current or output voltage. A method according to the prior art can then be used for the regulation. Depending on the operation (step-up or step-down converter operation), a switch is made between the regulation according to the invention and a regulation according to the prior art.

The three-phase buck-boost converter pulse rectifier system to be controlled and regulated by the method according to the invention can have a known structure on the input side by means of a bidirectionally blockable three-phase two-point bridge circuit (2) (bridge circuit) with three AC phase inputs (a, b and c) and a positive (p) and a negative voltage rail (s) are formed, whereby both voltage rails are led to the input of an output-side converter stage (load converter) (3), which feeds a consumer, or a voltage (load voltage) via the consumer ( uo) is generated (see Figure 1).

Furthermore, the phase inputs of the bridge circuit (a, b and c) are either directly or via an input filter with the associated phase terminals (a, b and c) of the feeding three-phase AC network (network) (1) connected, but at least each phase input of the bridge circuit (a, b and c) is fed to a filter capacitor (line filter capacitors) (C), which are connected either in a star or in a triangle in order to keep the operationally occurring pulse-shaped input currents in the three-phase bridge circuit away from the network or the To define the supply voltage independently of the internal impedance of the network.

The bridge circuit (2) generally has three bridge branches, each bridge branch having an upper electronic switch connected to the positive voltage rail (p) and a lower electronic switch with bipolar blocking capability connected to the negative voltage rail (s) and the phase output of the bridge branch ( a, b and c) is formed by the junction of the free ends of the upper and lower switch. The bipolar lockable switches (21 and 22) can each e.g. can be implemented by the anti-series connection of a unidirectional blocking component and a diode, the antiseries connection of two unidirectional blocking components, or by a bidirectional blocking component.

Furthermore, as noted in the introduction, the load converter (3) can be designed as a simple bidirectional step-up converter, which has a switched two-point bridge arm (step-up converter bridge arm) (31), the upper switch (311) of which with the positive DC output voltage rail (d) and the lower switch (312) is connected to the negative DC output voltage rail (n), a buffer capacitor (output capacitor) (Co) being arranged between these two DC output voltage rails to support the output voltage (uo) for the load above it.

The switching point (p) of the two-point bridge arm (31), i.e. the connection point of the upper switch (311) and lower switch (312) is led to a first connection of a step-up converter inductance (L), the second connection of which is connected on the input side to the positive voltage rail (p) of the input-side three-phase bridge circuit (2) and thus as an intermediate circuit inductance acts. The negative output voltage terminal of the two-point bridge arm (31) is directly connected to the negative voltage rail (s).

The system is modulated as a function of the size ratios of the line phase currents (in other words: as a function of the relationships between the absolute values of the line phase currents), with sections for a symmetrical three-phase network within 1/6 of the network period, i.e. Within a 60 ° -wide sector or section of a 360 ° corresponding complete oscillation period of the mains voltages, the bridge arm belonging to the largest phase current is switched through depending on the polarity of the largest phase current, with the upper switch (21) for a positive phase current and a negative one Phase current of the lower switch (22) remains switched on within an input current sector. This results in a six-pulse curve for the intermediate circuit current (iL) over a network period, with its instantaneous value corresponding to the largest phase current in terms of magnitude (see Figure 2).

FIG. 2 shows, for example, in a first time segment, corresponding to a sector 1: the current with the greatest magnitude is ib, it flows in the second phase (b) and has a negative sign. Thus, for the duration of this section, the lower switch sb, L of the second (or selected) phase is switched on and carries the intermediate circuit current (iL). The upper switch sb, H of this selected phase and the two other lower switches sa, L, sc, L remain open. The two other upper switches sa, H, sc, H can be switched in order to split the returning intermediate circuit current (iL) between the corresponding (unselected) two phases.

The largest phase current or the intermediate circuit current (iL) must flow back as a sum over the two other phases. If the largest phase current flows through the lower switch (22), the upper switches (21) of the bridge arms belonging to the two other phases must alternately be switched on, with their lower switch (22) remaining permanently switched off. The switching period is divided between the two switching intervals in such a way that a sinusoidal phase current curve is achieved in all phases. If the phase with the highest phase current is routed via one of the upper switch (21), the lower switches (22) of the two other phases must be switched on alternately, with their upper switch (22) then remaining permanently switched off (see Figure 2 ).

Advantageously, only two instead of three chained input voltages are connected to the output terminals of the three-phase bridge circuit, which reduces the number of switchings and thus the switching losses and the switching-frequency current ripple in the intermediate circuit inductance (see Figures 3 and 4). These show an excerpt, greatly enlarged over time, with the voltage ratios within a clock period Tp. During this, the voltages can be viewed as quasi constant. Typically, a clock frequency is at least ten times or twenty times or fifty times a basic frequency of the alternating voltages, in particular the line voltages.

If the size ratios of the input currents change when moving into the next following sector or section, the modulation is also adjusted accordingly. This means that the phase with the highest phase current is assigned to a different physical phase in each sector (see Figure 2).

The aim of the control of the system is, in the network phases, sinusoidal currents (ia, ib and ic) in phase (for power consumption from the network or in opposite phase for power recovery) with the associated network phase voltage (ia, ub and uc) to achieve, whereby for a symmetrical network all currents have the same amplitude and optionally at the output of the load converter (3) to generate a defined load voltage (uo) according to a specified target value (load voltage target value) (uo <*>), or generally a defined power to be delivered to the consumer (see Figure 5). Alternatively, the line phase currents can also have a phase shift with respect to the associated line phase voltages. For the further description, however, ohmic network behavior is assumed for the sake of clarity. Correspondingly, viewed from the network, the system can be seen as a star connection of equal ohmic resistances (equivalent input resistances) or conductance values (equivalent input conductance values), the performance of which is sent directly to the output under the idealized assumption of no loss, i.e. is passed on to the consumer.

Following this idea, the nominal value of the input equivalent conductance (input nominal conductance) (G *) is determined as a function of the load voltage control deviation, i.e. The difference between a specified load voltage setpoint (uo *) and the measured load voltage actual value (uo) is formed in that the load voltage control deviation is fed to the input of an output voltage regulator (51), which forms the required setpoint of the recharge current (iCo *) of the output capacitor (Co) at the output , which after (optional) addition of the measured load current (load current precontrol) (iLoad) and multiplication of this current sum with the output reference voltage (uo <*>) results in the setpoint of the power to be supplied to the output (output power setpoint) (Po <*>), which is ultimately to be obtained from the network, i.e. if the system losses are neglected, the input power setpoint is defined directly. Correspondingly, in the next step, division by the sum of the squares of the input phase voltages (ua, ub and uc) is used to determine the input setpoint conductance (G *), which corresponds to a power consumption from the network equal to the output power setpoint (Po <*>).

By multiplying the input setpoint conductance (G *) with the measured phase voltages (ua, ub and uc) then the input phase current setpoints (ia *, ib * <> and ic *) result, from which the intermediate circuit current setpoint (iL *) is determined, by forming the absolute value of all input phase current setpoints (ia *, ib * and ic *) and using the largest value as the intermediate circuit current setpoint (iL *).

Furthermore, the duty cycles for the three-phase bridge circuit (da, db and dc) can now be calculated from the ratio of the respective input phase current setpoints (ia *, ib <*> and ic <*>) and the intermediate circuit current setpoint (iL *) the effective duty cycle (da, H, da, L, db, H, db, L, dc, Hund dc, L) and the local mean value of the switched DC voltage at the output of the three-phase bridge circuit (ubu) can be obtained. <tb> • <SEP> Either the calculated pulse duty factor (da, db or dc) is positive and the relative switch-on time for the upper switch (da, H, db, H or dc, H) then corresponds to the calculated pulse duty factor (da, db or dc ) with the lower switch always off, ie the switch-on time is zero for the lower switch (da, L, db, L or dc, L), <tb> • <SEP> or the duty cycle (da, db or dc) is negative and the upper switch remains off, i.e. the switch-on time for the upper switch (da, H, db, H or dc, H) is zero, whereby the relative switch-on time for the lower switch (da, L, db, L or dc, L) corresponds to the value of the calculated duty cycle (da , db or dc).

From the effective duty cycle of the individual switches (da, H, da, L, db, H, db, L, dc, dog dc, L), the effective switching signals (sa, H1, sa, H2, sa, L1, sA, L2, sb, H1, sb, H2, sb, L1, sb, L2, sc, H1, sc, H2, sc, L1 and sc, L2) are generated for the individual switches.

The local mean value of the switched direct voltage (ubu) is obtained either by multiplying the calculated duty cycles (da, db and dc) with the corresponding phase voltages (ua, ub and uc) or alternatively (not shown) by dividing the output power setpoint (Po <* >) through the intermediate circuit current setpoint (iL <*>).

The control of the intermediate circuit current or inductance current (iL) is then carried out with a subordinate current control by first determining the control deviation by subtracting the measured intermediate circuit current (iL) from the intermediate circuit current setpoint (iL <*>) and this is then fed to an intermediate circuit current controller (52) which outputs the setpoint value of the voltage (uL *) to be formed on the associated intermediate circuit inductance (L) on average over a clock period. After subtracting this setpoint (uL *) from the calculated local mean value of the switched direct voltage (ubu), the local mean value of the voltage setpoint (ubo *) which is required at the midpoint of the step-up converter bridge branch results. If this midpoint voltage (ubo *) is divided by the nominal value of the output voltage (uo *), the relative duty cycle (dd) or, from a modulator (53), the effective switching signal (sd) for the upper switch (311) results directly from this. of the step-up converter bridge branch, the lower switch (312) of the bridge branch being switched off during the on-time of the upper switch (311), ie both switches of the bridge arm operate in push-pull mode and the clock period preferably has a constant length or the clock frequency preferably has a constant value. Overall, the intermediate circuit current actual value (iL) is managed in accordance with the associated intermediate circuit current setpoint curve (iL *).

It should be noted that the clocking of the three-phase bridge circuit and the step-up converter bridge branch can be performed, for example, with the same clock frequency and can be timed so that a minimum switching frequency fluctuation of the intermediate circuit current (iL) is achieved.

It should be noted that in addition to the implementation of the load converter as a DC / DC step-up converter, there are several other forms of implementation: <tb> • <SEP> a full bridge switching cell 6 with internal DC voltage, for implementing active shaping of the intermediate circuit current (see Figure 6). The intermediate circuit current is equal to the output current, which is impressed on the full-bridge switching cell 6 via corresponding clocking. Since the cell only compensates for power pulsations with six times the mains frequency, no DC-side supply is required. In addition, switching elements with a relatively low reverse voltage can advantageously be used for the full-bridge switching cell 6 compared to the three-phase bridge circuit. The <tb> • <SEP> A three-phase pulse converter, especially a pulse inverter 7 (see Figure 7), <tb> • <SEP> or another voltage stabilizing converter stage such as also galvanically separated DC / DC converters.

The full bridge switching cell 6 has two connections. It can be formed by two bridge branches which are connected in parallel to one another and in parallel to a switching cell capacitance between a switching cell positive pole and a switching cell negative pole. The center taps of the bridge branches form the two connections.

The circuit breakers of the full-bridge switching cell 6 can be designed to switch unidirectionally, each with anti-parallel freewheeling diodes.

It should be noted that ohmic network behavior is assumed to be desirable for the drawings and the above explanations, but the control method according to the invention can also be used for a phase shift of the network phase currents with respect to the assigned network phase voltages, in which case the phase current setpoints (which according to the above explanations for ohmic network behavior) corresponding reactive components are added.

Claims (10)

1. Method for regulating a three-phase pulse rectifier system (1, 2, 3), which has a three-phase bridge circuit (2) for exchanging power between a three-phase network (1) and an intermediate circuit inductance (L), and a load converter (3) for exchanging power between the DC link inductance (L) and a load, wherein the bridge branches of the three-phase bridge circuit (2) are arranged for switching phase currents flowing through the intermediate circuit inductance (L), where in chronologically successive sections, each lasting one sixth of the period of the three-phase network, each in one section • in that bridge branch, referred to below as the selected bridge branch, the three-phase bridge circuit (2) to which the network phase with the largest phase current in terms of magnitude, referred to below as the selected network phase, is assigned, this network phase optionally depending on the polarity of the phase current with a switch of the selected bridge branch, hereinafter referred to as selected switch, is connected to a positive connection point (p) or a negative connection point (n) of the three-phase bridge circuit (2), this network phase being connected to the positive connection point when the phase current is positive and to the negative connection point when the phase current is negative remains connected for the duration of this section, • in the other two, unselected, bridge branches by clocking the switch opposite the selected switch, the corresponding positive or negative connection point is alternately connected to the two unselected phases. 2. The method according to claim 1, wherein a sinusoidal phase current is set in each case in a time segment by the timing in each of the other two, unselected, bridge branches. 3. The method according to claim 1 or 2, wherein the load converter sets a voltage (ubo) at a load converter-side connection of the intermediate circuit inductance (L) which, in cooperation with a switched direct voltage (ubu) on the three-phase bridge circuit (2) formed by the load converter the other, bridge circuit-side connection of the intermediate circuit inductance (L) results in a specified intermediate circuit current (iL). 4. The method according to claim 3, wherein the intermediate circuit current (iL) is specified by an intermediate circuit current setpoint (iL *), and this is determined according to the following steps: • A nominal input conductance (G *) is formed as a function of a load voltage control deviation, which is equal to the difference between a specified nominal load voltage value (uo <*>) and a measured actual load voltage value (uo), o in that the load voltage control deviation is fed to the input of an output voltage regulator (51), which at the output forms a setpoint value of a recharging current (iCo *) of an output capacitor (Co) of the load converter (3), from which, after optional addition of a measured load current (iLoad) and after multiplication by an output reference voltage (uo <*>), an output power setpoint (Po *) of a power to be supplied to the output of the load converter (3) results; o and by dividing the output power setpoint (Po *) by a sum of squares of the input phase voltages (ua, ub and uc), the input setpoint conductance (G *) is determined, which means that the power consumption from the three-phase network (1) is equal to the output power setpoint (Po *) corresponds to; and • by multiplying the input setpoint conductance (G *) with the measured phase voltages (ua, ub and uc), input phase current setpoints (ia *, ib * and ic *) can be determined from which the intermediate circuit current setpoint (iL *) is determined by taking all input phase current setpoints (ia *) , ib * and ic *) the amount is formed and the largest value is used as the DC link current setpoint (iL *). 5. The method according to claim 4, wherein from the ratios of the input phase current setpoints (ia *, ib * and ic *) and the intermediate circuit current setpoint (iL *) duty cycles (da, db and dc) of the three-phase bridge circuit (2) are calculated from which the effective duty cycle (da, H, da, L, db, H, db, L, dc, dog dc, L) can be determined by each branch of the three-phase bridge circuit (2) • if the calculated duty cycle (da, db or dc) is positive, the relative switch-on time for an upper switch (da, H, db, H or dc, H) of the bridge arm is equal to the calculated duty cycle (da, db or dc), and the lower switch Switch of the bridge arm always remains off; • if the duty cycle (da, db or dc) is negative, the upper switch of the bridge arm remains switched off and the relative switch-on time for the lower switch (da, L, db, L or dc, L) of the bridge arm is equal to the value of the calculated duty cycle ( there, db or dc) is. 6. The method according to any one of the preceding claims, in which, in order to achieve a phase shift of the mains voltage and mains current, corresponding reactive components are added to the phase current setpoints. 7. The method according to any one of claims 1 to 6, in which the load converter (3) is a step-up converter. 8. The method according to any one of claims 1 to 6, in which • the load converter (3) is a pulse-controlled inverter; or • the load converter (3) is a full-bridge switching cell with internal switching cell capacitance arranged in a connecting line between the positive intermediate circuit voltage and positive output voltage terminal of the three-phase pulse rectifier system or between the negative intermediate circuit voltage and negative output voltage terminal of the three-phase pulse rectifier system. 9. The method according to claim 7, which switches between a first operating mode and a second operating mode, wherein • in the first operating mode, the three-phase bridge circuit (2) according to one of claims 1 to 6 and the load converter (3) are operated as a step-up converter; and • In the second operating mode, the three-phase bridge circuit (2) is operated as a step-down converter and the load converter (3) switches its output to its input and is not clocked. 10. Device for regulating a three-phase pulse rectifier system (1, 2, 3), which has a three-phase bridge circuit (2) for exchanging power between a three-phase network (1) and an intermediate circuit inductance (L), and a load converter (3) for exchanging power between the intermediate circuit inductance (L) and a load, characterized in that the device for performing the method is designed according to one of the preceding claims.