CA2391213A1 - Adressage simultane a l'aide de memoires ram a port unique - Google Patents

Adressage simultane a l'aide de memoires ram a port unique Download PDF

Info

Publication number
CA2391213A1
CA2391213A1 CA002391213A CA2391213A CA2391213A1 CA 2391213 A1 CA2391213 A1 CA 2391213A1 CA 002391213 A CA002391213 A CA 002391213A CA 2391213 A CA2391213 A CA 2391213A CA 2391213 A1 CA2391213 A1 CA 2391213A1
Authority
CA
Canada
Prior art keywords
port
input
memory bank
memory
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002391213A
Other languages
English (en)
Other versions
CA2391213C (fr
Inventor
Haggai Haim Haller
Elisha John Ulmer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2391213A1 publication Critical patent/CA2391213A1/fr
Application granted granted Critical
Publication of CA2391213C publication Critical patent/CA2391213C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Multi Processors (AREA)
CA002391213A 1999-11-12 2000-11-13 Adressage simultane a l'aide de memoires ram a port unique Expired - Fee Related CA2391213C (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/438,251 1999-11-12
US09/438,251 US6144604A (en) 1999-11-12 1999-11-12 Simultaneous addressing using single-port RAMs
PCT/US2000/031194 WO2001035419A1 (fr) 1999-11-12 2000-11-13 Adressage simultane a l'aide de memoires ram a port unique

Publications (2)

Publication Number Publication Date
CA2391213A1 true CA2391213A1 (fr) 2001-05-17
CA2391213C CA2391213C (fr) 2008-04-15

Family

ID=23739880

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002391213A Expired - Fee Related CA2391213C (fr) 1999-11-12 2000-11-13 Adressage simultane a l'aide de memoires ram a port unique

Country Status (9)

Country Link
US (1) US6144604A (fr)
JP (1) JP4718079B2 (fr)
KR (1) KR100663248B1 (fr)
CN (1) CN1423818A (fr)
AU (1) AU771163B2 (fr)
CA (1) CA2391213C (fr)
HK (1) HK1054613A1 (fr)
IL (2) IL149566A0 (fr)
WO (1) WO2001035419A1 (fr)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100280287B1 (ko) * 1998-08-28 2001-03-02 윤종용 반도체 메모리 장치
JP3298552B2 (ja) * 1999-04-15 2002-07-02 日本電気株式会社 半導体記憶装置及び半導体記憶装置システム
US6411557B2 (en) * 2000-02-02 2002-06-25 Broadcom Corporation Memory architecture with single-port cell and dual-port (read and write) functionality
US6603712B2 (en) 2000-02-02 2003-08-05 Broadcom Corporation High precision delay measurement circuit
US6937538B2 (en) * 2000-02-02 2005-08-30 Broadcom Corporation Asynchronously resettable decoder for a semiconductor memory
US6611465B2 (en) 2000-02-02 2003-08-26 Broadcom Corporation Diffusion replica delay circuit
US6745354B2 (en) 2000-02-02 2004-06-01 Broadcom Corporation Memory redundancy implementation
US6417697B2 (en) 2000-02-02 2002-07-09 Broadcom Corporation Circuit technique for high speed low power data transfer bus
US6535025B2 (en) 2000-02-02 2003-03-18 Broadcom Corp. Sense amplifier with offset cancellation and charge-share limited swing drivers
US8164362B2 (en) * 2000-02-02 2012-04-24 Broadcom Corporation Single-ended sense amplifier with sample-and-hold reference
US6492844B2 (en) 2000-02-02 2002-12-10 Broadcom Corporation Single-ended sense amplifier with sample-and-hold reference
US6414899B2 (en) * 2000-02-02 2002-07-02 Broadcom Corporation Limited swing driver circuit
US6724681B2 (en) * 2000-02-02 2004-04-20 Broadcom Corporation Asynchronously-resettable decoder with redundancy
US7173867B2 (en) * 2001-02-02 2007-02-06 Broadcom Corporation Memory redundancy circuit techniques
US7340664B2 (en) * 2000-09-20 2008-03-04 Lsi Logic Corporation Single engine turbo decoder with single frame size buffer for interleaving/deinterleaving
US6976114B1 (en) * 2001-01-25 2005-12-13 Rambus Inc. Method and apparatus for simultaneous bidirectional signaling in a bus topology
US6492881B2 (en) * 2001-01-31 2002-12-10 Compaq Information Technologies Group, L.P. Single to differential logic level interface for computer systems
US6714467B2 (en) * 2002-03-19 2004-03-30 Broadcom Corporation Block redundancy implementation in heirarchical RAM's
TW548923B (en) * 2001-06-12 2003-08-21 Realtek Semiconductor Corp Data register in communication system and method thereof
US6882562B2 (en) * 2001-11-01 2005-04-19 Agilent Technologies, Inc. Method and apparatus for providing pseudo 2-port RAM functionality using a 1-port memory cell
US6880056B2 (en) * 2002-03-28 2005-04-12 Hewlett-Packard Development, L.P. Memory array and method with simultaneous read/write capability
KR100481174B1 (ko) * 2002-08-02 2005-04-07 삼성전자주식회사 메모리 코어의 전 영역에서 동일한 스큐를 가지는 반도체메모리 장치
US6917536B1 (en) 2002-09-13 2005-07-12 Lattice Semiconductor Corporation Memory access circuit and method for reading and writing data with the same clock signal
EP1406265B1 (fr) * 2002-10-02 2007-01-03 Dialog Semiconductor GmbH Dispositif et procédé pour éviter des collisions d'accès mémoire
US7181650B2 (en) * 2003-06-02 2007-02-20 Atmel Corporation Fault tolerant data storage circuit
US7200693B2 (en) 2004-08-27 2007-04-03 Micron Technology, Inc. Memory system and method having unidirectional data buses
US7209405B2 (en) * 2005-02-23 2007-04-24 Micron Technology, Inc. Memory device and method having multiple internal data buses and memory bank interleaving
US20070028027A1 (en) * 2005-07-26 2007-02-01 Micron Technology, Inc. Memory device and method having separate write data and read data buses
KR100785892B1 (ko) * 2005-12-07 2007-12-17 한국전자통신연구원 양방향 데이터 통신용 단일 포트 메모리 제어 장치 및 그제어 방법
CN101232434B (zh) * 2007-01-22 2011-08-24 中兴通讯股份有限公司 一种利用双口ram进行异步数据传输的装置
KR101388134B1 (ko) * 2007-10-01 2014-04-23 삼성전자주식회사 뱅크 충돌 방지 장치 및 방법
US7660178B2 (en) * 2008-05-13 2010-02-09 Lsi Corporation Area efficient first-in first-out circuit
TWI409816B (zh) * 2009-02-27 2013-09-21 Himax Tech Ltd 解決單埠靜態隨機存取記憶體之請求衝突的系統及方法
US8209478B2 (en) * 2009-03-03 2012-06-26 Himax Technologies Limited Single-port SRAM and method of accessing the same
KR101586844B1 (ko) 2010-01-06 2016-02-02 삼성전자주식회사 영상 처리 장치 및 방법
US8942248B1 (en) * 2010-04-19 2015-01-27 Altera Corporation Shared control logic for multiple queues
US8339887B2 (en) 2010-11-17 2012-12-25 Lsi Corporation Double line access to a FIFO
CN102567259A (zh) * 2010-12-27 2012-07-11 北京国睿中数科技股份有限公司 面向高速通信接口的低功耗缓冲装置
WO2013033882A1 (fr) * 2011-09-05 2013-03-14 Huawei Technologies Co., Ltd. Procédé et appareil pour stocker des données
CN102388359B (zh) 2011-09-15 2014-01-01 华为技术有限公司 信号保序方法和装置
KR20130102393A (ko) 2012-03-07 2013-09-17 삼성전자주식회사 Ｆｉｆｏ 메모리 장치 및 이를 포함하는 전자 장치
TWI528362B (zh) * 2013-05-30 2016-04-01 鈺創科技股份有限公司 靜態隨機存取記憶體系統及其操作方法
TWI639159B (zh) 2015-05-28 2018-10-21 東芝記憶體股份有限公司 Semiconductor device
US10817493B2 (en) 2017-07-07 2020-10-27 Raytheon Company Data interpolation
CN109388370B (zh) * 2017-08-03 2023-06-27 深圳市中兴微电子技术有限公司 一种实现先入先出队列的方法及装置
CN110134365B (zh) * 2019-05-21 2022-10-11 合肥工业大学 一种多通道并行读出fifo的方法及装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592058B2 (ja) * 1977-04-28 1984-01-17 日本電信電話株式会社 記憶装置
JPH01248261A (ja) * 1988-03-29 1989-10-03 Nec Corp デュアルポートメモリにおけるメモリアクセス制御回路
US5267191A (en) * 1989-04-03 1993-11-30 Ncr Corporation FIFO memory system
JP3039963B2 (ja) * 1990-06-18 2000-05-08 株式会社日立製作所 半導体記憶装置
US5255239A (en) * 1991-08-13 1993-10-19 Cypress Semiconductor Corporation Bidirectional first-in-first-out memory device with transparent and user-testable capabilities
US5371877A (en) * 1991-12-31 1994-12-06 Apple Computer, Inc. Apparatus for alternatively accessing single port random access memories to implement dual port first-in first-out memory
JP3199207B2 (ja) * 1993-12-16 2001-08-13 シャープ株式会社 マルチポート半導体記憶装置
FR2717591B1 (fr) * 1994-03-15 1996-06-21 Texas Instruments France Mémoire virtuelle d'interconnexion notamment pour la mise en communication de terminaux de télécommunication fonctionnant à des fréquences différentes.
JP3531208B2 (ja) * 1994-03-17 2004-05-24 ヤマハ株式会社 ディジタル信号処理装置
US5546347A (en) * 1994-07-22 1996-08-13 Integrated Device Technology, Inc. Interleaving architecture and method for a high density FIFO
JPH08328941A (ja) * 1995-05-31 1996-12-13 Nec Corp メモリアクセス制御回路
JP3664777B2 (ja) * 1995-08-18 2005-06-29 株式会社ルネサステクノロジ 半導体記憶装置
US5568443A (en) * 1995-09-08 1996-10-22 Smithills Multimedia Systems, Inc. Combination dual-port random access memory and multiple first-in-first-out (FIFO) buffer memories
US5802579A (en) * 1996-05-16 1998-09-01 Hughes Electronics Corporation System and method for simultaneously reading and writing data in a random access memory
JP3359251B2 (ja) * 1996-12-11 2002-12-24 ソニー・テクトロニクス株式会社 リアルタイム信号アナライザ
US5912898A (en) * 1997-02-27 1999-06-15 Integrated Device Technology, Inc. Convolutional interleaver/de-interleaver
KR19980077474A (ko) * 1997-04-19 1998-11-16 김영환 비디오 신호의 스캔방식 변환장치 및 그 제어방법
TW321770B (en) * 1997-06-21 1997-12-01 Ind Tech Res Inst Single block static random access memory without read/write collision
US5982700A (en) * 1998-05-21 1999-11-09 Integrated Device Technology, Inc. Buffer memory arrays having nonlinear columns for providing parallel data access capability and methods of operating same

Also Published As

Publication number Publication date
IL149566A0 (en) 2002-11-10
HK1054613A1 (zh) 2003-12-05
WO2001035419A1 (fr) 2001-05-17
IL149566A (en) 2006-06-11
US6144604A (en) 2000-11-07
KR100663248B1 (ko) 2007-01-02
AU771163B2 (en) 2004-03-18
JP2003514314A (ja) 2003-04-15
JP4718079B2 (ja) 2011-07-06
KR20020059716A (ko) 2002-07-13
CN1423818A (zh) 2003-06-11
CA2391213C (fr) 2008-04-15
AU1657901A (en) 2001-06-06

Similar Documents

Publication Publication Date Title
CA2391213A1 (fr) Adressage simultane a l'aide de memoires ram a port unique
US5809557A (en) Memory array comprised of multiple FIFO devices
EP0840324A3 (fr) Mémoire à semi-conducteurs et méthode d'accès d'une telle mémoire
EP0262468A3 (fr) Dispositif de mémoire fifo reconfigurable
KR100301054B1 (ko) 데이터 입출력 버스의 전송 데이터율을 향상시키는 반도체 메모리장치 및 이를 구비하는 메모리 모듈
WO2003001360A3 (fr) Systeme memoire premier entre, premier sorti et procede associe
WO1995034030A3 (fr) Memoire centrale s'articulant autour d'une memoire flash
MY121258A (en) Packet video signal inverse transport processor memory address circuitry
WO2001069603A3 (fr) Fonctionnement simultane de plusieurs blocs d'une memoire flash
GB2312305A (en) Embedded memory block with fifo mode for programmable logic device
CA2106271A1 (fr) Architecture de memoires premier entre premier sorti a un et a plusieurs etages pour synchroniseurs de transfert de donnees
US4679173A (en) Sequential access LSI memory circuit for pattern generator
US6259648B1 (en) Methods and apparatus for implementing pseudo dual port memory
CA2199571A1 (fr) Creation d'une ram multiport au moyen d'un multiplexage temporel
US5341488A (en) N-word read/write access achieving double bandwidth without increasing the width of external data I/O bus
US5764967A (en) Multiple frequency memory array clocking scheme for reading and writing multiple width digital words
US5319596A (en) Semiconductor memory device employing multi-port RAMs
EP0495217A3 (fr) Mémoire sequentielle
US5448714A (en) Sequential-access and random-access dual-port memory buffer
CA2163850A1 (fr) Arbitrage de bus entre un dispositif d'entree-sortie et un dispositif de traitement dans un tampon d'enregistrement du type premier entre premier sorti
JPH04505679A (ja) 記憶装置準拠式線遅延アーキテクチャ
EP1459291B1 (fr) Ligne numerique a retard avec memoire a port unique
WO2005029347A3 (fr) Circuit integre equipe d'une pluralite de processeurs de signaux numeriques mis en communication
KR100664009B1 (ko) 메모리 억세스 제어기
JP2002190193A (ja) メモリ装置およびデータ記憶方法

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed
MKLA Lapsed

Effective date: 20121113