經濟部中央揉準局負工消费合作社印製 321770 A7 _B7 五、發明説明（1 ) 本發明係有關於一種積體電路記憶體裝置，特別是可 適用於一種連續性資料之讀寫，而且僅僅使用單一區塊之 靜態隨機存取記憶體（static random access memory， SRAM)，在同時讀寫連續性資料時，不會發生讀寫衝突的 情形，可以使某些視訊和語音處理之應用範圍擴大，例如 電視訊號格視（NTSC)12.5M操作頻率和電腦訊號格視 (VGA)25M操作頻率之間的格視轉換，其讀寫頻率互為彼此 的整數倍皆適用本發明方法，同時晶片面積減少，成本降 低，功率消耗方面也降低了。 靜態隨機存取記憶體（以下簡稱SRAM)為常見之記憶 趙裝置，本身係屬於一種揮發性(volatile)的記憶體，亦即， 當供給SRAM的電力消失之後’所儲存之資料會同時抹除。 SRAM儲存資料的方式是利用記憶單元（mein〇ry cell)内電 晶體的導電狀態達成’這與同屬於揮發性記憶體的動態隨 機存取記憶體(DRAM)利用電容器帶電狀態儲存資料的方 式並不相同。SRAM的存取速度相當快，因此經常在電腦系 統中當做快取記憶體(cache memory)，以及在部份需要即時 (real time)運算的視訊和語音應用中使用。 第1A圖為NMOS邏輯中所常用之SRAM記憶單元之電 路圖。電晶體Ml、M2、M3和M4構成栓鎖電路(latch)，其 中’電晶體M3和M4做為主動負載之用，端點χ*γ則會產 生邏輯位準相異之邏輯信號。字元線评則做為定址用，控制 電晶體Μ5和Μ6的開關狀態；位元線Β和位元線百則分別讀 取或寫入端點X和γ的邏輯值。CMOS邏輯電路中的sram記 3 本纸張尺度逋用中國固家榡率（CNS > A4規格（210X297公釐） I I I _ —裝 I 訂 I I I ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貞工消費合作社印製 A7 ________B7 五、發明説明（2 ) 憶單元結構則與第1囷大致相同，不同之處僅在於栓鎖電路 係以CMOS電路組成，如第1B圖所示。第⑺圏為習知CMOS 邏輯中SRAM記憶單元之電路圖。電晶體M7、M8、M9和 M10構成栓鎖電路，其中，M7和M8為NMOS電晶體，M9和 M10為PMOS電晶體。在資料讀取或寫入的動作中，同樣係 利用電晶艎Mil和M12控制資料存取(access)的路徑，至於 其讀寫操作方式，則與NMOS邏輯的SRAM記憶單元相同。 由第1A圖和第1B圖可知，SRAM的最大缺點，即在於 所需的電晶體數量太多，無論在NMOS邏輯或是CMOS邏 輯，每一記憶單元需要六個電晶體構成。雖然目前亦有技 術將栓鎖電路中做為主動負載之電晶體以複晶矽電阻加以 取代，但是仍需要至少四個電晶體。換句話說，一般SRAM 的積集度相較於DRAM都相當低，製造成本也就相對提高。 因此，對特殊積體電路(ASIC)中的嵌入式靜態隨機存取記 憶體(Embed SRAM)來說，如何降低成本是一重要課題。 除此之外，在某些視訊和語音處理應用中，SRAM尚需 具備同時進行讀寫動作的特性，亦即SRAM的讀取動作和寫 入動作是同時連續進行的。架構上，係將如第1圖的記憶單 元以陣列方式（array)構成，每一橫列的記憶單元利用相同之 字元線定址，每一直行的記憶單元利用相同之位元線讀取 或是寫入資料。在記憶單元陣列外則具有週邊電路，包括 列解碼器、行解碼器、感測放大器等等，以處理資料之讀 寫動作。但是，由於SRAM在X軸方向具有共用字元線(word line)以及γ轴方向具有共用位元線（bit line)的結構，當同 本紙張尺度適用中國國家標率（CNS ) A4规格（210X297公釐） ---------—裝------訂------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央橾準局貞工消费合作社印装 321770 A7 _____B7 "X、發明説明（3 ) 時進行讀寫動作，以及在讀寫速度不同之情形下，會發生 讀/寫相衝(read/write collision)的現象。因此，勢必要利用 雙區塊(two-port)SRAM，作為讀/寫動作的資料緩衝器。 故而，習知可以同時進行讀寫動作之SRAM，都是採用 雙區塊的結構，以避免讀寫相衝的情況。亦即，在同一個 SRAM中，具有兩個重複(duplicate)的記憶區塊，這兩個獨 立的s己憶區塊具有相同的定址位址，相等的記憶單元長 度，但是進行讀寫動作時的順序是交錯的。當寫入第一個 記憶區塊的資料時，第二個記憶區塊正在進行讀取動作； 當寫入第二記憶區塊的資料時，則進行第一個記憶區塊的 讀取動作。對於具有雙區塊結構的SRAM之外部電路而言， 寫入動作和讀取動作都是連續性的，即SRAM是在同時進行 讀寫動作，因此可適用於即時處理的視訊語音處理。 然而’上述可以同時讀寫的雙區塊s RAM顯然必須採用 更多的記憶體單元，佔用更多的晶片面積。因此，對於每 一記憶單元位址而言，雙區塊SRAM的電晶體數量要比傳統 SRAM多出了一倍，即12個電晶體。這使得雙區塊811八]^的 電路積集度更低，造成製造成本更高。 有鑑於此，本發明之主要目的在於提供一種讀/寫速度 可彈性變化且無讀寫衝突之單一區塊靜態隨機存取記憶 體’其利用少許的X軸、以及Y轴控制電路，將傳統讀/寫雙 區塊SRAM架構中的字元讀取線(read-word_iine)及字元寫 入線(write-word-line) ’經由γ轴控制電路整合為讀/寫共用 的字元控制線(word-line)。同理，傳統讀/寫雙區塊訊八^^架 本紙張尺度逋用中ΒΗ家標率（CNS > Α4规格（210X297公釐） ----------装-----丨訂------. '冰 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（4 ) 構中的位元讀取線（read-bit-line)及位元寫入線（write-bit-line)，經由X軸控制電路整合為讀/寫共用的位元控制線 (bit-line)。如此一來，SRAM内的記憶單元並不需要以重複 的方式來避免讀寫相衝的情況發生，亦即每個記憶單元的 電晶體數量仍然維持在6個或4個，可以大大提高可同時讀 寫SRAM的電路積集度，降低製造成本。 根據上述之目的，本發明提供一種無讀寫衝突之單一 區塊靜態隨機存取記憶體，其包括：複數記憶體單元配置 成一記憶體單元陣列，每一記憶體單元具有獨立之資料讀 取/寫入路徑，由一讀取時脈信號以及一寫入時脈信號分別 控制上述記憶體單元之循序讀取以及寫入；複數字元控制 線、及複數位元控制線，其分別接收一字元線控制信號、 及一位元線控制信號，用以在上述記憶體單元中致能及定 址出一特定位置之記憶體單元以供讀取或寫入資料；複數Y 轴控制電路，分別耦接於上述每一字元控制線，每一Y軸控 制電路分別接收一讀取字元信號、一寫入字元信號、上述 讀取時脈信號、以及上述寫入時脈信號，而輸出一字元線 控制信號，由於上述Y軸控制電路之邏輯運作，使得上述字 元線控制信號僅能在相對於上述讀取時脈信號之前半週期 中致能上述Y軸控制電路所對應字元控制線上之記憶體單 元以供讀取資料，且使得上述字元線控制信號僅能在相對 於上述讀取時脈信號之後半週期中致能上述Y轴控制電路 所對應字元控制線上之記憶體單元以供寫入資料，如此在 同一瞬間，上述記憶體單元僅能進行讀取或寫入資料，而 本紙張尺度逋用中固國家標隼（CNS ) Μ规格（210X297公釐） ---------1 裝------訂------^ (請先閱讀背面之注意事項再填寫本頁) ' A7 -----------B7 五、發明説明（5 ) '---、^ 避免出現同時讀寫記憶趙單元而造成資料錯亂之情形；、 及複數X軸控制電路，分別耗接於上述每一位元控制: - X軸控制電路分別接收—讀取位元信號、—寫人仅 號、上述讀取時脈信號、上述寫入時脈信號、以及 : 時脈信號，而輸出-位元線控制信號，由於上述x抽控隔 路之邏輯運作，使得上述位元線控制信號僅能在相對於= 述讀取時脈信號之前半週期中致能上述乂轴控制電路所對 應位元控制線上之記憶體單元以供讀取資料，且使得上述 位元線控制信號僅能在相對於上述讀取時脈信號之後半週 期中致能上述X軸控制電路所對應位元控制線上之記憶體 單元以供寫入資料，如此在同一時間内上述記憶體單元僅 能進行讀取或寫入資料，而避免出現同時讀寫記憶體單元 而造成資料錯亂之情形。其中，上述靜態隨機存取記憶體 讀取動作之讀取速度可為寫入動作之寫入速度之整數倍， 抑或上述寫入動作之寫入速度可為上述讀取動作之讀取速 度之整數倍。 應用本發明之一種無讀寫衝突之單一區塊靜態隨機存 取記憶體控制方法，可以獲致如下之優點： 一、 面積減少：額外增加一點些許之控制電路，便可 以使用單一區塊取代雙區塊SRAM，所以面積幾乎減少了一 半。 二、 應用彈性增加：由於讀取速度可為寫入速度之整 數倍，並且寫入速度亦可為讀取速度之整數倍，故而可以 擴大應用於日新月異之影像、語音等領域做更特殊之處 本紙張尺度適用中困國家橾牟（CNS ) A4规格（210X297公釐） I 1 -- - · • n- I - n n n n J . 1 ^ 1 I (請先閲讀背面之注意事項再填寫本頁} 經濟部中央標準局貝工消费合作社印氧 經濟部中央標準局貝工消费合作社印製 321770 A7 ----- B7 五、發明説明（6 ) 理。 二、電路穩定性不變：本發明額外增加之控制電路， 僅整合子元控制線、以及位元控制線之開/關時序Printed 321770 A7 _B7 by the Negative Work Consumer Cooperative of the Ministry of Economic Affairs of the Ministry of Economic Affairs 5. Description of the invention (1) The present invention relates to an integrated circuit memory device, especially applicable to the reading and writing of a continuous data, and only Use a single block of static random access memory (static random access memory, SRAM), when reading and writing continuous data at the same time, there will be no conflicts between reading and writing, which can expand the scope of application of some video and voice processing For example, the TV signal grid TV (NTSC) 12.5M operating frequency and the computer signal grid (VGA) 25M operating frequency conversion, the read and write frequency is an integer multiple of each other are applicable to the method of the present invention, and the chip area Reduction, cost reduction, and power consumption are also reduced. Static random access memory (hereinafter referred to as SRAM) is a common memory device, which is a volatile memory, that is, when the power supplied to SRAM disappears, the stored data will be erased at the same time. . SRAM stores data by using the conductive state of the transistor in the memory cell. This is the same as the dynamic random access memory (DRAM), which is also volatile memory, uses the capacitor charged state to store data. Not the same. The access speed of SRAM is quite fast, so it is often used as cache memory in computer systems, and in some video and voice applications that require real-time computing. Figure 1A is a circuit diagram of an SRAM memory cell commonly used in NMOS logic. Transistors M1, M2, M3, and M4 constitute a latch circuit, in which 'transistors M3 and M4 are used as active loads, and the end point χ * γ will generate logic signals with different logic levels. The word line evaluation is used for addressing to control the switching states of transistors M5 and M6; bit line B and bit line 100 read or write the logical values of endpoints X and γ, respectively. Sram in CMOS logic circuit 3 The size of this paper is based on China's Gujia rate (CNS> A4 specification (210X297mm) III _ — Pack I order III ^ (please read the precautions on the back before filling this page ) Printed by the Central Standards Bureau of the Ministry of Economic Affairs Zhengong Consumer Cooperative A7 ________B7 V. Description of the invention (2) The structure of the memory unit is roughly the same as the first one, the only difference is that the latch circuit is composed of a CMOS circuit, as shown in Figure 1B As shown in Figure ⑺, the circuit diagram of the SRAM memory cell in the conventional CMOS logic. Transistors M7, M8, M9, and M10 constitute a latch circuit, where M7 and M8 are NMOS transistors, and M9 and M10 are PMOS transistors. In the operation of data reading or writing, the path of data access is also controlled by the transistors Mil and M12, and the read and write operation mode is the same as the SRAM memory cell of NMOS logic. By 1A As can be seen from the figure and Figure 1B, the biggest disadvantage of SRAM is that the number of transistors required is too much. Whether in NMOS logic or CMOS logic, each memory cell requires six transistors. Although there are currently technologies to plug As the lock circuit The transistors of the dynamic load are replaced by polycrystalline silicon resistors, but at least four transistors are still required. In other words, the accumulation degree of general SRAM is relatively low compared to DRAM, and the manufacturing cost is relatively increased. Therefore, For embedded static random access memory (Embed SRAM) in special integrated circuits (ASIC), how to reduce costs is an important issue. In addition, in some video and voice processing applications, SRAM still needs It has the characteristics of simultaneous read and write operations, that is, the read and write operations of SRAM are performed simultaneously and continuously. Architecturally, the memory cells as shown in Figure 1 are formed in an array, each row The memory cells are addressed using the same word line, and the memory cells in each row use the same bit line to read or write data. Outside the memory cell array, there are peripheral circuits, including column decoders, row decoders, Sensing amplifiers, etc., to process the reading and writing of data. However, due to the structure of the SRAM having a common word line in the X-axis direction and a common bit line in the γ-axis direction, The same paper size applies to China National Standard (CNS) A4 specification (210X297mm) ---------— installed ------ ordered ------ line (please read the back page first (Notes to fill out this page) The Ministry of Economic Affairs, Central Bureau of Prefectural Affairs, Zhengong Consumer Cooperative prints 321770 A7 _____B7 " X, invention description (3), and reads and writes, and in the case of different read and write speeds, reading will occur / The phenomenon of read / write collision. Therefore, it is necessary to use a two-port SRAM as a data buffer for read / write operations. Therefore, the conventional SRAM, which can perform both read and write operations at the same time, adopts a dual-block structure to avoid the conflict between read and write. That is, in the same SRAM, there are two duplicate memory blocks. The two independent memory blocks have the same addressing address and the same memory unit length, but when performing read and write operations The order is staggered. When writing data in the first memory block, the second memory block is being read; when writing data in the second memory block, the first memory block is being read. For the external circuit of the SRAM with a dual block structure, the writing and reading operations are continuous, that is, the SRAM is reading and writing at the same time, so it can be applied to real-time video and audio processing. However, the above dual-block s RAM that can be read and written at the same time must obviously use more memory cells and occupy more chip area. Therefore, for each memory cell address, the number of transistors in a dual-block SRAM is double that of a conventional SRAM, that is, 12 transistors. This results in a lower degree of circuit integration for the dual block 811 and a higher manufacturing cost. In view of this, the main purpose of the present invention is to provide a single block static random access memory whose read / write speed can be flexibly changed without read-write conflicts. It utilizes a few X-axis and Y-axis control circuits Read / write word read line (read-word_iine) and word write line (write-word-line) in dual-block SRAM architecture 'integrated as read / write shared character control line through γ-axis control circuit (word-line). In the same way, the traditional read / write dual-block information eight ^^ frame paper is used in the standard standard (CNS > Α4 specification (210X297 mm) ---------- installed --- -丨 Subscribe ------. 'Bing (please read the precautions on the back before filling in this page) A7 B7 printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention description (4) Position in the structure The read-bit-line and write-bit-line are integrated into a read-write shared bit-line through the X-axis control circuit. , The memory cells in SRAM do not need to repeat the way to avoid the situation of read and write conflicts, that is, the number of transistors in each memory cell is still maintained at 6 or 4, which can greatly improve the ability to read and write SRAM at the same time According to the above purpose, the present invention provides a single block static random access memory without read and write conflicts, which includes: a plurality of memory cells are configured as a memory cell array, each The memory unit has an independent data read / write path, consisting of a read clock signal and a write clock signal Separately control the sequential reading and writing of the memory unit; the complex digital control line and the complex bit control line, which respectively receive a word line control signal and a bit line control signal, are used in the memory Enabling and addressing a specific location of the memory unit in the body unit for reading or writing data; a plurality of Y-axis control circuits, respectively coupled to each of the above character control lines, and each Y-axis control circuit receiving A read character signal, a write character signal, the read clock signal, and the write clock signal output a word line control signal. Due to the logical operation of the Y-axis control circuit, the above The character line control signal can only enable the memory cell on the character control line corresponding to the Y-axis control circuit for reading data in the half cycle before the read clock signal, and enables the character line control The signal can only enable the memory cell on the character control line corresponding to the Y-axis control circuit for writing data in a half cycle after the read clock signal, so that the same In an instant, the above-mentioned memory unit can only read or write data, and this paper standard uses the Zhonggu National Standard Falcon (CNS) Μ specification (210X297mm) --------- 1 installed- ---- Subscribe ------ ^ (Please read the precautions on the back before filling in this page) 'A7 ----------- B7 5. Description of the invention (5)' --- , ^ To avoid the situation of data confusion caused by simultaneous reading and writing of the Zhao unit; and a plurality of X-axis control circuits, which are consumed by each of the above bit controls:-The X-axis control circuit receives-reads bit signals, -Write only the number, the above read clock signal, the above write clock signal, and: the clock signal, and the output-bit line control signal, due to the logic operation of the above x pumping control circuit, the above bit The line control signal can only enable the memory cell on the bit control line corresponding to the above-mentioned axis control circuit for reading data in the first half cycle relative to the read clock signal, and makes the bit line control signal The bit control line corresponding to the X-axis control circuit can only be enabled in the half-cycle after the read clock signal The memory unit is used for writing data, so that the above memory unit can only read or write data at the same time, so as to avoid the situation of data confusion caused by simultaneous reading and writing of the memory unit. Wherein, the read speed of the static random access memory read operation may be an integer multiple of the write speed of the write operation, or the write speed of the write operation may be an integer of the read speed of the read operation Times. The application of a single block static random access memory control method without read-write conflicts of the present invention can achieve the following advantages: 1. Area reduction: a little extra control circuit can be used to replace the dual area with a single block Block SRAM, so the area is almost reduced by half. 2. Increased application flexibility: Since the reading speed can be an integer multiple of the writing speed, and the writing speed can also be an integer multiple of the reading speed, it can be expanded and applied to the ever-changing fields of image, voice, etc. The size of this paper is applicable to the A4 size (210X297mm) of the Moushou (CNS) in troubled countries. Printed by the Ministry of Economic Affairs, Central Bureau of Standardization, Beigong Consumer Cooperative, printed by the Ministry of Economic Affairs, Central Bureau of Standards, printed 321770 A7 ----- B7 Fifth, the description of the invention (6) Principle 2. The stability of the circuit is unchanged: the invention is extra The added control circuit only integrates the on / off timing of the sub-element control line and the bit-element control line
，而 SRAM 之電路架構不變，因此電路之穩定性不受影響。 四、功率消耗減少：由於使用單一區塊取代雙區塊 SRAM而達到無讀寫衝突之目的，所以面積減少一半，電晶 體數目亦減少一半，所以功率損耗估計減少一半，另一方 面，在SRAM寫入動作時，會造成一條vdd—gnd的直流 路^ ’例如’圖1B中此直流路徑為Vd_^Mpl—^11—►Μ?— GND或Vd—Mp2~>M12->M8—GND。而本發明之方法將寫 入之動作控制在讀取時脈（或寫入時脈）之最後四分之一週 期中，縮短了直流路徑打開的時間，故更可以降低功率之 損耗。 為讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，做詳細說明如 下： 圖式之簡單說明： 第1A圏為習知NMOS邏輯中靜態隨機存取記憶體之記 憶體單元之電路圖； 第1B圖為習知CMOS邏輯中靜態隨機存取記憶體之記 憶趙單元之電路圓； 第2A圖為依據本發明之一種無讀寫衝突之單一區塊靜 態隨機存取記憶體之架構； 第2B圖為一般(：1^08邏輯中靜態隨機存取記憶體内部 本紙張;^逋用中國國家標準（CNS ) (210X297公釐） ---------1赛-- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央梯準局貝工消费合作社印«. A7 _________— 五、發明説明（7) 架構； 第3圖為依據本發明之X轴控制電路其讀寫動作之時序 团 . 圍， 第4圖為依據本發明用以實現第3圖動作時序之一種X 軸控制電路圖； 第5圖為依據本發明之Y軸控制電路其讀寫動作之時序 圖；以及 第6圖為依據本發明用以實現第5圖動作時序之一種γ 軸控制電路圖。 實施例： 請參照第2A圖’其概要顯示一種無讀寫衝突之單一區 塊靜態隨機存取記憶體之架構1，其包括複數記憶體單元配 置成一記憶體單元陣列2,每一記憶體單元具有獨立之資料 讀取路徑(dataO/P)3、及資料寫入路徑(dataI/P)4，由一讀 取時脈信號RCLK以及一寫入時脈信號WCLK(在此未圖示）分 別控制上述記憶體單元之循序讀取以及寫入。 在此實施例中，讀取速度係為寫入速度之兩倍，然而， 本發明並非僅適用於讀取速度係為寫入速度之兩倍的操作 模式下’本發明可適用於讀取速度為寫入速度之整數倍、 或寫入速度為讀取速度之整數倍的操作模式下'。 複數字元控制線5、及複數位元控制線6，其分別接收 一字元線控制信號Y! ’ Υζ.,.Υ^.Υν、及一位元線控制信號 X!，X2…Xj...XM，用以在上述記憶體單元中致能及定址出一 特定位置之記憶體單元以供讀取或寫入資料，其中數字1^與 本纸張尺度適用中困a家棣半（CNS) a4規格（2丨〇><297公嫠） (請先閲讀背面之注意事項再填寫本頁) •裝· 訂 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（8 ) Μ分別表示字元控制線及位元控制線之個數。 一 Υ轴控制裝置7，包含複數Υ轴控制電路（在此未圖 示），分別耦接於每一上述複數字元控制線5，每一上述Υ轴 控制電路至少接收一讀取字元信號（rY)i、一寫入字元信號 (wY)i、上述讀取時脈信號RCLK、以及上述寫入時脈信號 其中1«N’而輸出上述字元線控制信號Yi至其對應 之字元控制線5。 一X軸控制裝置8,包含複數X轴控制電路，分別耦接於 每一上述複數位元控制線6，每一上述X轴控制電路至少接 收一讀取位元線信號(rX)j、一寫入位元線信號(wX)j、上述 讀取時脈信號Rcuc、以及上述寫入時脈信號Wcuc，其中1勾 ，而輸出一位元線控制信號Xj至位元控制線6 ;上述記憶 體陣列2利用複數字元控制線5、以及複數位元控制線6，用 以定址出所要讀取/寫入之記憶體單元之位置。 於習知技術中，當讀/寫動作同時於單一區塊靜態隨機 存取記憶體中進行，而且讀寫速度不同之情形下，會發生 之讀/寫相衝情形有下列兩種： 一、 當讀/寫位置在同一個記憶體單元，也就是說讀和 寫之動作皆定址在同一字元控制線以及同一位元控制線上 (以下簡稱為同一 Y轴以及X轴位置）。 二、 當讀和寫之動作皆定址在同一位元控制線上，但 是不同之字元控制線上，即是相同X轴位置且不同之Y軸位 置。 第一種讀/寫相衝情形 10 本紙張尺度適用中國國家標準（CNS > A4規格（2丨0X297公釐） I- I I I !!> n^^lln I ^—訂 I I I I I f 線 (請先閲讀背面之注意事項再填寫本頁) A7 B7 321770 五、發明説明（9 ) 當讀/寫位置在同一 Y轴以及X轴位置上時，讀/寫動作 交集在某一記憶趙單元上，為避免資料錯亂，本發明之方 法係將記憶體單元中之舊資料先行讀取，再將新資料寫 入。所以任一位元控制線上之信號X〗(其中K拉Μ，Μ表示 位元控制線之個數）都是交替輸出一位元讀取致能信號 (readX)』或是一寫入位元寫入致能信號(writex)j給其對應之 位元控制線而作為位元線控制信號X』，而分別定址記憶雜 單元得以進行讀取及寫入資料。 本發明即是利用每一X轴控制電路將其所接收之信號 作簡單之邏輯運算’俾將資料讀取及寫入動作分隔開以避 免讀寫相衝之情形發生。任一X轴控制電路之一可能的邏輯 運算式為：The circuit structure of SRAM remains unchanged, so the stability of the circuit is not affected. 4. Power consumption reduction: As a single block is used to replace the dual block SRAM to achieve the purpose of no read and write conflicts, the area is reduced by half and the number of transistors is also reduced by half. When writing, it will cause a vdd-gnd DC path ^ 'For example' in Figure 1B, this DC path is Vd_ ^ Mpl— ^ 11—►Μ? — GND or Vd—Mp2 ~> M12- > M8— GND. The method of the present invention controls the writing operation in the last quarter cycle of the reading clock (or writing clock), which shortens the opening time of the DC path, so that the power loss can be further reduced. In order to make the above objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is described below in conjunction with the attached drawings, which are described in detail as follows: Brief description of the drawings: Section 1A The circuit diagram of the memory unit of the static random access memory in the NMOS logic; FIG. 1B is the circuit circle of the memory Zhao unit of the conventional random access memory in the CMOS logic; FIG. 2A is a non-volatile memory according to the present invention. The structure of a single block static random access memory for read-write conflicts; Figure 2B is the general (: 1 ^ 08 logic in the static random access memory internal paper; ^ use China National Standards (CNS) (210X297 Ali) --------- 1 competition-(please read the notes on the back before filling in this page) Ordered by the Ministry of Economic Affairs Central Bureau of Standardization Beigong Consumer Cooperative Society «. A7 _________— V. Description of the invention ( 7) Architecture; Figure 3 is a timing group of the X-axis control circuit according to the present invention for reading and writing operations. Figure 4 is a diagram of an X-axis control circuit for realizing the timing of the operation of Figure 3 according to the present invention; The picture shows the reading and writing of the Y-axis control circuit according to the present invention The timing diagram of the operation; and FIG. 6 is a γ-axis control circuit diagram for implementing the operation timing of FIG. 5 according to the present invention. Embodiment: Please refer to FIG. 2A 'for an overview showing a single block static without read-write conflict The random access memory architecture 1 includes a plurality of memory cells arranged as a memory cell array 2, each memory cell has an independent data read path (dataO / P) 3, and a data write path (dataI / P) 4, a read clock signal RCLK and a write clock signal WCLK (not shown here) respectively control the sequential reading and writing of the above-mentioned memory cells. In this embodiment, the reading speed It is twice the writing speed. However, the present invention is not only applicable to the operating mode where the reading speed is twice the writing speed. The present invention is applicable to the reading speed being an integer multiple of the writing speed, or The writing speed is an operating mode that is an integer multiple of the reading speed. The complex digital control line 5 and the complex digital control line 6 respectively receive a word line control signal Y! 'Υζ.,. Υ ^. Υν, and one-bit line control signals X !, X2 ... Xj ... XM is used to enable and address a specific location of the memory unit in the above memory unit for reading or writing data, where the number 1 ^ and the paper size are suitable for trouble Semi (CNS) a4 specification (2 丨 〇 < 297 gong) (please read the notes on the back before filling in this page) • Binding · Order A7 B7 printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention Description (8) M represents the number of character control lines and bit control lines, respectively. A Υ-axis control device 7, including a complex Υ-axis control circuit (not shown here), respectively coupled to each of the above complex numbers Element control line 5, each of the Y axis control circuits receives at least a read character signal (rY) i, a write character signal (wY) i, the read clock signal RCLK, and the write clock Among them, 1 «N 'outputs the above word line control signal Yi to its corresponding word control line 5. An X-axis control device 8 includes a plurality of X-axis control circuits, respectively coupled to each of the above-mentioned complex bit control lines 6, each of the X-axis control circuits receives at least one read bit line signal (rX) j, one Write bit line signal (wX) j, the read clock signal Rcuc, and the write clock signal Wcuc, where 1 tick, and output a bit line control signal Xj to bit control line 6; the memory The volume array 2 uses a complex digital control line 5 and a complex digital control line 6 to address the location of the memory cell to be read / written. In the conventional technology, when read / write operations are simultaneously performed in a single block of static random access memory and the read and write speeds are different, the following two types of read / write conflicts can occur: 1. When the read / write position is in the same memory unit, that is to say, the read and write operations are addressed on the same character control line and the same bit control line (hereinafter referred to as the same Y-axis and X-axis positions). 2. When the read and write operations are addressed on the same bit control line, but on different character control lines, it is the same X-axis position and different Y-axis position. The first reading / writing phase conflict situation 10 This paper scale is applicable to the Chinese national standard (CNS > A4 specification (2 丨 0X297mm) I-III !! > n ^^ lln I ^ —order IIIII f line (please Read the precautions on the back first and then fill out this page) A7 B7 321770 5. Description of the invention (9) When the read / write position is on the same Y-axis and X-axis position, the read / write action intersects on a memory Zhao unit, In order to avoid data confusion, the method of the present invention is to read the old data in the memory unit first, and then write the new data. Therefore, the signal X on any bit control line (where K pulls M, M represents the bit The number of control lines) is to alternately output a bit read enable signal (readX) "or a write bit write enable signal (writex) j to its corresponding bit control line as a bit Line control signal X ”, and separately address memory cells to read and write data. The present invention utilizes each X-axis control circuit to perform simple logic operations on the signals it receives to read and write data. Write action is separated to avoid the situation of reading and writing conflict. Any X axis control One of the possible logic expressions of the control circuit is:
Xj=(readX)j+(writeX)j =rclk * (rX)j + WCLK · (wX)j · Rclr (1) 利用此邏輯運算即可將讀取動作安排於讀取時脈之前半週 期’而寫入動作則安排在讀取時脈之後半週期而避免讀寫 相衝之情形。其中SCLK係為一間隔時脈信號，在此例中其週 期為讀取時脈週期之二分之一，用以將寫入動作與讀取動 作完全區隔開來。若以讀取時脈之前半週期為高電位為 例’則任一位元控制線6之信號及其相關信號之時序安排如 第3圖所示。本發明之X轴控制裝置中之每一χ軸控制電路可 以簡單之邏輯電路來實現，如第4圖所示即為一可能之實施 例。 請參照第3圖與邏輯算式（1)，在讀取時脈信號Rcuc之第 本纸張尺度適用中國困家樣準（CNS > A4規格（2丨0X297公釐） ---------,1裝------訂------^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 M濟部中央標準局貝工消费合作社印裝 A7 _________B7___ 五、發明説明（10 ) I週期内’無同時讀寫同一記憶體單元之情形發生，在此期 間第(j-l)位元控制線上輸出（readX)』-,信號，所以一記憶體單 元在相對於讀取時脈信號RCLK第I週期之前半週期内進行讀 取動作。 在讀取時脈信號RCLK之第II週期内，第j位元控制線上 之一記憶體單元在此時間内同時進行讀/寫之動作。依照第j 個X轴控制電路之邏輯算式（1)之控制，第j位元控制信號Xj 在讀取時脈第II週期之前半週中係為一位元讀取致能信號 (readX)』’以使得記憶體單元之資料得以先行讀取出來。第j 位元控制信號Xj在讀取時脈第II週期之後半週中係為一位 元寫入致能信號(writeX)』，再配合間隔時脈信號sCLK之控制 而將寫入動作之進行限定在第II週期之最後四分之一週期 中’用以區分出讀取與寫入動作之界線，又由於寫入動作 之時間僅佔讀取時脈週期之四分之一故更可以降低功率之 損耗。所以，應用本發明之X軸控制電路，可避免同時讀/ 寫同一記憶體單元而發生讀/寫衝突之情形發生。 第二種讀/窵相衛情形 請參照第2B囷’其顯示一般CMOS邏輯中靜態隨機存取 記憶體内部架構。當讀/寫動作發生在相同的某一X軸位置 (Xj) ’但是不同的Y轴位置(Yi和Yi+1)時，即同一時間内要讀 出記憶體單元C1中之資料至data O/P，又要將data Ι/P之資料 寫入記憶體單元C2中。其中，W為一寫入致能信號。 但是由於在同一 X軸位置上之記憶體單元其位元資料 傳輸線（第1B和2B圖中的位元線B，及位元線百)係共用，所 12 ---------f'1裝------訂------^線 _ : (請先閲讀背面之注意事項再填寫本頁)Xj = (readX) j + (writeX) j = rclk * (rX) j + WCLK · (wX) j · Rclr (1) With this logic operation, the read operation can be scheduled in the half cycle before the read clock. The write operation is arranged half a cycle after the read clock to avoid the read and write conflict. SCLK is an interval clock signal. In this example, the period is one-half of the read clock period, which is used to completely separate the write operation from the read operation. If the high potential before the half cycle of the reading clock is taken as an example, the timing of the signal of any bit control line 6 and its related signal is shown in FIG. Each x-axis control circuit in the X-axis control device of the present invention can be implemented by a simple logic circuit, as shown in Fig. 4 is a possible embodiment. Please refer to Figure 3 and the logic formula (1), the first paper standard for reading the clock signal Rcuc is applicable to China's poor family standard (CNS > A4 specification (2 丨 0X297mm) ------ ---, 1 pack ------ order ------ ^ (please read the notes on the back before filling out this page) Printed by the Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperative M Central Economic Bureau Printed by Beigong Consumer Cooperative A7 _________B7___ V. Description of invention (10) I did not have the situation of reading and writing the same memory unit at the same time in the I cycle, during this period, the (jl) bit control line output (readX) ", signal , So a memory cell performs a read operation in the half cycle before the first cycle of the read clock signal RCLK. In the second cycle of the read clock signal RCLK, the jth bit controls a memory on the line The unit performs simultaneous read / write operations within this time. According to the logic formula (1) of the j-th X-axis control circuit, the j-th bit control signal Xj is half a week before the second period of the reading clock. Read enable signal (readX) for one bit to enable the data of the memory unit to be read in advance. The bit control signal Xj is a one-bit write enable signal (writeX) half a week after the second period of the read clock, and then the write operation is limited to the control of the interval clock signal sCLK. In the last quarter of the second cycle, it is used to distinguish the boundary between the read and write operations, and because the time of the write operation only occupies a quarter of the read clock cycle, the power can be reduced. Loss. Therefore, the application of the X-axis control circuit of the present invention can avoid the situation of read / write conflicts when reading / writing the same memory unit at the same time. For the second read / symmetry situation, please refer to the 2B The internal structure of static random access memory in general CMOS logic. When the read / write operation occurs at the same X-axis position (Xj) 'but different Y-axis positions (Yi and Yi + 1), it is the same time To read the data in the memory cell C1 to data O / P, and write the data Ι / P data into the memory cell C2. Among them, W is a write enable signal. But because the same X axis The location of the memory unit and its bit data transmission line (Figure 1B and 2B The bit line B, and bit line 100) are shared, so 12 --------- f'1 installed ------ order ------ ^ line_: (please first (Read the notes on the back and fill in this page)
本紙張尺度逋用中國固家樣牟（CNS > A4規格（210X297公釐）The size of this paper adopts China Gujia Sample Mou (CNS > A4 specification (210X297mm)
經濟部中央揉準局負工消费合作社印*. A7 B7_ 五、發明説明（11 ) 以不論於讀取或寫入資料之過程中，將造成同時對兩個記 憶體單元C1、C2讀取資料，亦或是同時對(n、C2寫入資料， 如此而將造成資料傳輸之混淆，而得到錯誤之結果。 為了解決上述難題，本發明利用Y轴控制電路，將γ轴 方向之任一字元控制線上之輸出信號Yi調整成在同一時 間内僅能致能一個記憶體單元以供讀取或是寫入資料（其 中，，N表示字元控制線之個數）。也就是說，字元控 制線(word line)上之輸出信號丫丨係交替輸出一字元讀取致 能信號(readY)i或是一字元寫入致能信號(write Yh給其對應 之位元控制線(word line)，而分別定址記憶體單元得以進行 讀取及寫入資料》藉由錯開讀取與寫入之時間而避免讀/寫 相衝之情形發生。本發明即是利用每一 Y轴控制電路將其所 接收之信號作簡單之邏輯運算，俾將資料讀取及寫入動作 分隔開以避免讀寫相衝之情形發生。任一γ軸控制電路之一 可能的邏輯運算式為： Y i=(readY)i+(write Y)j =rclk * (rY)> + WCLK · (wY)j · Rclk。 （2) 利用此邏輯運算即可將讀取動作安排於讀取時脈之前半週 期’而寫入動作則於後半週期中執行。 請參考第5圖及上述之邏輯運算式(2)。在b-c時段中第} 個Y轴控制電路同時接收到讀取字元線信號(rY)。以及寫入 字元線信號(wY)i ’經由上述邏輯運算式（2)之運算，在相對 於讀取時脈信號rclk之前半週期輸出讀取字元線信號 (readYX ’而在讀取時脈信號rclk之後半週期輸出寫入字元 13 本紙張尺度適用中國國家橾车（CNS > A4規格（2丨0χ297公嫠） ---------T彳裝------訂------' ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印51 A7 —----------B7_ 五、發明说明（12 ) " 線信號(writeΥ)ί最後整合成字元控制線信號γί在此情形 下，其配合上述X轴控制電路即可避免同時讀/寫相 同記憶 艘而造成讀/寫相衝之情形。 在cd時段中’第1+1個丫袖控制電路接收到讀取字元線 信號(rY)i+i ’所以第1+1字元控制線上之記憶趙單元將被 致能以供循序讀取》此時第i字元控制線上之仍有部份記憶 體單元正進行寫人之動作^經由上述邏輯運算式⑺之運 算’在相對於讀取時脈信敝咖之前半週期輸出讀取字線 元信號(readY)i+1至第（i+1)字元控制線而成為字元線控制信 號Yi+, ’而纟RCLK之後半週期仍輸出寫入字元線信號 (wdteYL至至第i字元控制線而成為字元線控健號γί。如 此，即使上述讀/寫動作係發生在同一 X軸位元控制線上， 由於讀取及寫入動作已相互錯開半個週期，所以在讀/寫過 程中，不會有同-瞬間對兩個相同乂轴位置之記憶體單元進 行讀/寫而發生讀寫相衝之情形。 本發明除了可避免讀/寫衝突之外，更可以降低電路之 佈局面積，兹比較如下。 面稽的比較 1.傳統方法（雙區塊SRAM)的面積估算： 個位元之SRAM單元實際佈局面積為Ι5μπιχ18μιη，因 此’以單一區塊664(8x83)記憶體單元SRAM為例其面積如 下 ’ X轴方向為 15μιηχ8χ8=960μιη，Y軸方向為 18μιηχ83+60 μηι+80μηι=1634 μηι，所以傳統可同時讀寫雙區塊具有664 記憶體單元之SRAM其面積為960μιηχ1634μιηχ8。 14 本纸張尺度適用令國國家梯率（CNS ) Α4規格（2丨0X297公釐） ! I— —I—^ 1 裝^訂 '^, (請先閲讀背面之注意事項再填寫本頁) A7 B7 321770 五、發明説明（13 ) 2. 本發明方法（單一區塊SRAM)的面積估算： 單一區塊664(8x83)記憶體單元SRAM，如上所述X軸方 向為 15μιηχ8χ8=960μιη，Y軸方向為 18μιηχ83+60μπι+80μ ιη=1634μπι 〇 額外增加的X轴控制電路面積估算如下，X轴方向15μιη χ8χ8 =960μιη ’ Υ軸方向30μηιχ4=120μιη，所以X轴控制電路 所增加之面積為960μηιχ120μιη ;額外增加的Υ轴控制電路面 積估算如下，X轴方向65μιη，Υ轴方向18μοιχ83=1494μιη， 所以Υ轴控制電路所增加之面積為65μπι><1494μιη。所以依據 本發明單一區塊可同時讀寫664個記憶體單元之SRAM面積 為. 960μηιχ1634μηι+[960μιηχ120μιη]+[65μιηχ1494μιη] 〇 3. 兩者面積比： a. 傳統方法：本發明之方法=2 : 1.14。 b. 當傳統方法與本發明之方法同時應用在影像處理r， G ’ B三種色彩時，則傳統方法：本發明之方法=2 : 1.047。 縱上所述，應用本發明有如下優點： 一、 面積減少：額外增加一點點控制電路，便可以使 用單一區塊取代雙區塊SRAM，所以面積幾乎減少了一半。 二、 應用彈性增加：由讀取動作之讀取速度可為寫入 動作之寫入速度之整數倍，且寫入動作之寫入速度亦可為 上述讀取動作之讀取速度之整數倍，故而可以擴大應用於 曰新月異之影像、語音等領域做更特殊之處理。 三、 電路穩定性不變：本發明僅額外增加之控制電路， 15 本纸張尺度適用中國囷家標率（CNS > A4規格（210X297公釐） ---------^ 1裝------訂------二' (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印装 A7 _______B7 五、發明説明（14 ) 僅改變字元控制線、以及位元控制線開/關時序，而SRAM 之電路架構不變，因此電路之穩定性不受影響。 四、功率消耗減少一半：由於使用單一區塊取代雙區 塊SRAM而達到無讀寫衝突之目的，所以面積減少一半，功 率損耗也減少一半。另外由於寫入之動作可以控制在讀取 時脈之最後四分之一週期中，故更可以降低功率之損耗。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，本發明亦適用於讀取速度等於寫入速度、讀 取速度為寫入速度之整數倍、或寫入速度為讀取速度之整 數倍的情形，任何熟悉本項技藝者，在不脫離本發明之精 神和範圍内’當可做些許之更動和潤飾’因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 n I - - - n I I - n ϋ I I n 丁 U3 、T (請先閲讀背面之注意事項再填寫本頁) 經濟部中央揉準局負工消費合作杜印裝 本紙張从適^國國家標準（〇10><297公釐)Printed by the Ministry of Economic Affairs, Central Bureau of Accreditation and Consumer Cooperatives *. A7 B7_ V. Description of the invention (11) In the process of reading or writing data, it will cause data to be read from two memory units C1, C2 at the same time , Or write data to (n, C2 at the same time, which will cause confusion in data transmission and obtain erroneous results. In order to solve the above problems, the present invention uses a Y-axis control circuit to convert any word in the γ-axis direction The output signal Yi on the element control line is adjusted to enable only one memory unit for reading or writing data at the same time (where, N represents the number of character control lines). That is, the word The output signal on the word control line alternately outputs a word read enable signal (readY) i or a word write enable signal (write Yh to its corresponding bit control line ( word line), and individually address memory cells to read and write data "by staggering the time of reading and writing to avoid read / write conflicts. The present invention uses each Y-axis control The circuit simply makes the signal it receives Operation, to separate the data reading and writing operations to avoid the conflict between reading and writing. One of the possible logic expressions of any γ-axis control circuit is: Y i = (readY) i + (write Y ) j = rclk * (rY) > + WCLK · (wY) j · Rclk. (2) With this logic operation, the read operation can be scheduled in the first half cycle of the read clock 'and the write operation in the second half Executed during the cycle. Please refer to Figure 5 and the above logic expression (2). In the bc period, the} th Y-axis control circuit simultaneously receives the read word line signal (rY) and write word line signal (wY) i 'Through the operation of the above logic operation formula (2), the read word line signal (readYX' is output half a cycle before the read clock signal rclk and half a cycle is output after the read clock signal rclk Write characters 13 This paper standard is suitable for China National Pickup Truck (CNS & A4 specifications (2 丨 0χ297 public daughter) --------- T 彳 装 ------ 定 ----- -'^ (Please read the precautions on the back before filling in this page) 51 A7 —--------- B7_ of the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of the invention (12) " line The number (writeΥ) is finally integrated into a character control line signal. In this case, it can avoid the situation of read / write conflicts caused by reading / writing the same memory vessel at the same time with the above-mentioned X-axis control circuit. 'The 1 + 1th sleeve control circuit receives the read word line signal (rY) i + i', so the memory Zhao unit on the 1 + 1th character control line will be enabled for sequential reading. " There are still some memory cells on the i-th character control line that are writing people ^ Through the operation of the above logic operation formula ⑺ ', the read word line signal is output half a cycle before the signal relative to the reading clock (readY) i + 1 to (i + 1) th word control line to become the word line control signal Yi +, and the write word line signal (wdteYL to the i-th character control) is still output after half a cycle of RCLK The line becomes the character line control health number γί. In this way, even if the above-mentioned read / write operations occur on the same X-axis bit control line, since the read and write operations have been staggered by half a cycle from each other, there will be no same-instant pair of two during the read / write process The memory unit at the axis position reads / writes and the read-write conflict occurs. In addition to avoiding read / write conflicts, the present invention can also reduce the layout area of the circuit. The comparison is as follows. Comparison of face-to-face 1. Area estimation by traditional method (dual-block SRAM): The actual layout area of a single-bit SRAM cell is Ι5μπιχ18μιη, so 'Take a single block 664 (8x83) memory cell SRAM as an example. The X-axis direction is 15μιηχ8χ8 = 960μιη, and the Y-axis direction is 18μιηχ83 + 60μηι + 80μηι = 1634μηι, so the traditional SRAM that can simultaneously read and write dual blocks with 664 memory cells has an area of 960μιηχ1634μιηχ8. 14 The size of this paper is applicable to the National Grading Rate (CNS) Α4 specification (2 丨 0X297mm)! I— —I— ^ 1 Binding ^ ordering, (please read the precautions on the back before filling this page) A7 B7 321770 5. Description of the invention (13) 2. Area estimation of the method of the present invention (single block SRAM): Single block 664 (8x83) memory cell SRAM, as described above, the X axis direction is 15μιηχ8χ8 = 960μιη, Y axis The direction is 18μιηχ83 + 60μπι + 80μιη = 1634μπι. The additional area of the X-axis control circuit is estimated as follows. The X-axis direction is 15μιη χ8χ8 = 960μιη 'Υaxis direction 30μηιχ4 = 120μιη, so the area of the X-axis control circuit increased by 960μηιχ120μιη; additional The area of the increased Υ-axis control circuit is estimated as follows, 65 μιη in the X-axis direction and 18 μοχ83 = 1494 μιη in the Υ-axis direction, so the increased area of the Υ-axis control circuit is 65 μπι > < 1494μιη. Therefore, according to the present invention, the SRAM area of a single block that can simultaneously read and write 664 memory cells is 960μηιχ1634μηι + [960μιηχ120μιη] + [65μιηχ1494μιη] 〇3. Area ratio of the two: a. Traditional method: the method of the present invention = 2: 1.14. b. When the traditional method and the method of the present invention are applied to image processing r, G ’B three colors at the same time, the traditional method: the method of the present invention = 2: 1.047. As mentioned above, the application of the present invention has the following advantages: 1. Area reduction: With a little additional control circuit, a single block can be used to replace the dual block SRAM, so the area is almost reduced by half. 2. Increased application flexibility: the read speed from the read operation can be an integer multiple of the write speed of the write operation, and the write speed of the write operation can also be an integer multiple of the read speed of the above read operation, Therefore, it can be expanded to be used in the fields of rapidly changing images, voice and other fields for more special processing. 3. The circuit stability is unchanged: the present invention only has an additional control circuit, 15 paper scales are applicable to the Chinese standard rate (CNS> A4 specification (210X297 mm) --------- ^ 1 Install ------ order ------ two '(please read the precautions on the back before filling in this page) Printed A7 _______B7 of the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (14) Only Change the word control line and bit control line on / off timing, and the circuit structure of SRAM remains unchanged, so the stability of the circuit is not affected. Fourth, power consumption is reduced by half: due to the use of a single block instead of dual block SRAM To achieve the goal of no read-write conflict, the area is reduced by half, and the power loss is also reduced by half. In addition, because the writing operation can be controlled in the last quarter cycle of the reading clock, the power loss can be reduced. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. The present invention is also applicable to the reading speed equal to the writing speed, the reading speed is an integer multiple of the writing speed, or the writing speed is The situation of the integer multiple of reading speed Anyone who is familiar with this skill will not deviate from the spirit and scope of the present invention as 'may be used for some changes and retouching'. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application. N I ---n II-n ϋ II n D U3, T (please read the precautions on the back before filling in this page) The Ministry of Economic Affairs Central Bureau of Accreditation and Consumer Cooperation Cooperate Du Printed Paper from the national standard (〇 10 > < 297mm)