CA2322080A1 - New metamorphic heterojunction bipolar transistor having material structure for low cost fabrication on large size gallium arsenide wafers - Google Patents
New metamorphic heterojunction bipolar transistor having material structure for low cost fabrication on large size gallium arsenide wafers Download PDFInfo
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- CA2322080A1 CA2322080A1 CA002322080A CA2322080A CA2322080A1 CA 2322080 A1 CA2322080 A1 CA 2322080A1 CA 002322080 A CA002322080 A CA 002322080A CA 2322080 A CA2322080 A CA 2322080A CA 2322080 A1 CA2322080 A1 CA 2322080A1
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 title claims abstract description 28
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 25
- 239000000463 material Substances 0.000 title claims abstract description 20
- 235000012431 wafers Nutrition 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052738 indium Inorganic materials 0.000 abstract description 4
- 230000008901 benefit Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 230000001413 cellular effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000037230 mobility Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000000979 retarding effect Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
A metamorphic heterojunction bipolar transistor having a material structure for low cost fabrication on large size gallium arsenide wafers comprises a semi-insulating GaAs substrate; an undoped AlGaAsSb (or AlInGaAs) metamorphic buffer layer; a heavily doped n-type InGaAs layer, forming an ohmic contact for the collector of said MHBT; a lightly doped n-type InGaAs or InP or InAlAs layer, forming the collector of said MHBT;
a heavily doped p-type InGaAs layer, forming the base and an ohmic contact for the base of said MHBT; an n-type InAlAs (or graded AlInGaAs or InP) layer, forming the emitter of said MHBT; and a heavily doped n-Such material structure makes high-indium content MHBTs feasible to be fabricated on large size gallium arsenide wafers with diameters of six inches or larger, resulting in lower manufacturing cost, higher power, higher efficiency at a very low operation voltage.
a heavily doped p-type InGaAs layer, forming the base and an ohmic contact for the base of said MHBT; an n-type InAlAs (or graded AlInGaAs or InP) layer, forming the emitter of said MHBT; and a heavily doped n-Such material structure makes high-indium content MHBTs feasible to be fabricated on large size gallium arsenide wafers with diameters of six inches or larger, resulting in lower manufacturing cost, higher power, higher efficiency at a very low operation voltage.
Description
New Metamorphic Heterojunction Bipolar Transistor Having Material Structure for Low Cost Fabrication on Large Size Gallium Arsenide Wafers s FIELD OF THE INVENTION
The present invention generally relates to a metamorphic heterojunction bipolar transistor (to be abbreviated as "MHBT" here below), and more particularly, to an MHBT having a material structure for low cost fabrication on large size gallium arsenide (GaAs) wafers.
io BACKGROUND OF THE INVENTION
Recently, there has been increasing interest in developing high performance transistor-based amplifiers which are essential for both military and commercial applications in digital computers, telecommunication systems, and advanced electronic systems as they can is handle signals at high frequencies. These amplifiers have the potential for low cost, high gain, low noise, and high efficiency operation with reliability superior to that of IMPATTs and TWTAs.
Heterojunction bipolar transistor (HBT), as the term suggests, has a heterojunction formed between semiconductors of different compositions ao and band-gaps. The use of a wide band-gap emitter and a low band-gap base provides band offset at the hetero-interface that favors electron injection, in an N-p-n transistor, into the base while retarding hole injection into the emitter. It also provides benefits for high-speed operation because the electrons that surmount the energy barrier are injected into the base Zs with high forward velocities, reducing base transit time.
Accordingly, GaAs HBTs, based on AIGaAs (or InGaP)/GaAs material structure, have gained a wide acceptance especially for cellular phone power amplifier (PA) applications, as they exhibit advantages of high frequency, high linearity, and small die size, and only one power 3o supply is required. The high turn-on voltage of GaAs HBTs, however, practically limits the operation of the devices in the range of 3.0 to 3.6V in the cellular phones now in use.
The trend in mobile communication is to reach a system level solution that will support a single cell Li battery design of 1.2 to 1.5V (down from 3.6V). This is due to size and weight reduction of the battery pack, which accounts for approximately 60% of the total weight of a wireless handset.
s The InP HBT is, on the contrary, is an ideal candidate for 1.5V operation, since it has a lower turn on voltage, and also offers higher gain and higher efficiency than the GaAs HBT due to its intrinsic advantages of higher mobilities, faster non-equilibrium transport velocities and lower surface recombination.
to The InP HBT, based on InAIAs (or graded AIInGaAs)/InGaAs heterojunction material structure, has been fabricated on an InP substrate.
Please refer to FIG. 1, which is a schematic cross-sectional view illustrating an example of material structure an InP-based HBT in the prior art. As can be seen in the drawing, the epitaxially grown material structure comprises a is semi-insulating InP substrate 10; a heavily doped n-type InGaAs layer 12, forming an ohmic contact for the collector of said InP-based HBT; a lightly doped n-type InGaAs layer 13, forming the collector of said InP-based HBT; a heavily doped p-type InGaAs layer 14, forming the base and an ohmic contact for the base of said InP-based HBT; an n-type InAIAs (or Zo graded AIInGaAs) layer 15, forming the emitter of said InP-based HBT;
and a heavily doped n-type InGaAs layer 16, forming an ohmic contact for the emitter of said InP-based HBT.
Therefore, the InP-based HBT has advantages of providing higher maximum frequency of operation and cutoff frequency for significantly Zs lower noise figure, higher gain and better efficiency. This is due to the fact that the InP-based HBT has high indium content, and thus has higher electron velocity, current density, and transconductance. Although InP HBTs are very attractive for low voltage and high efficiency operation especially in use in the PAs of the cellular phones, they are, however, difficult to process 30 (primarily due to the InP substrate). Furthermore, the InP wafer is very fragile, costly (about 10 times of GaAs) and presently limited to only 3-in.
in size. On the contrary, the processing technology for GaAs HBTs has higher yield and lower cost (presently 40% less), if 6-in. wafers are used.
Accordingly, there is a need for a new device with both high efficiency, low voltage operation and low manufacturing cost.
SUMMARY OF THE INVENTION
It is therefore a main object of the present invention to provide a new metamorphic heterojunction bipolar transistor having material structure s with high efficiency, low voltage operation.
It is another object of the present invention to provide a new metamorphic heterojunction bipolar transistor having material structure with low manufacturing cost.
In order to accomplish the foregoing objects, the present invention to provides a metamorphic heterojunction bipolar transistor (MHBT), having a material structure for low cost fabrication on large size gallium arsenide (GaAs) wafers, comprising: a semi-insulating GaAs substrate; an undoped metamorphic buffer layer, such as AIGaAsSb or AIInGaAs buffer; a heavily doped n-type InGaAs layer, forming an ohmic contact for the ~ s collector of said MHBT; a lightly doped n-type InGaAs layer or InP or InAIAs layer, forming the collector of said MHBT; a heavily doped p-type InGaAs layer, forming the base and an ohmic contact for the base of said MHBT; an n-type InAIAs layer or graded AIInGaAs or InP layer, forming the emitter of said MHBT; and a heavily doped n-type InGaAs layer, Zo forming an ohmic contact for the emitter of said MHBT.
It is preferable that said material structure is epitaxially grown on large size GaAs wafers with diameters of six inches or larger.
BRIEF DESCRIPTION OF THE DRAWINGS
The object, features and advantages of the present invention will be as readily understood from the following descriptions of the preferred embodiment with reference to the drawings, in which:
FIG. 1 is a schematic cross-sectional view illustrating an example of material structure of an InP-based HBT in the prior art.
FIG. 2 is a schematic cross-sectional view illustrating an example of ~o material structure of an MHBT in accordance with the preferred embodiment of the present invention.
The present invention generally relates to a metamorphic heterojunction bipolar transistor (to be abbreviated as "MHBT" here below), and more particularly, to an MHBT having a material structure for low cost fabrication on large size gallium arsenide (GaAs) wafers.
io BACKGROUND OF THE INVENTION
Recently, there has been increasing interest in developing high performance transistor-based amplifiers which are essential for both military and commercial applications in digital computers, telecommunication systems, and advanced electronic systems as they can is handle signals at high frequencies. These amplifiers have the potential for low cost, high gain, low noise, and high efficiency operation with reliability superior to that of IMPATTs and TWTAs.
Heterojunction bipolar transistor (HBT), as the term suggests, has a heterojunction formed between semiconductors of different compositions ao and band-gaps. The use of a wide band-gap emitter and a low band-gap base provides band offset at the hetero-interface that favors electron injection, in an N-p-n transistor, into the base while retarding hole injection into the emitter. It also provides benefits for high-speed operation because the electrons that surmount the energy barrier are injected into the base Zs with high forward velocities, reducing base transit time.
Accordingly, GaAs HBTs, based on AIGaAs (or InGaP)/GaAs material structure, have gained a wide acceptance especially for cellular phone power amplifier (PA) applications, as they exhibit advantages of high frequency, high linearity, and small die size, and only one power 3o supply is required. The high turn-on voltage of GaAs HBTs, however, practically limits the operation of the devices in the range of 3.0 to 3.6V in the cellular phones now in use.
The trend in mobile communication is to reach a system level solution that will support a single cell Li battery design of 1.2 to 1.5V (down from 3.6V). This is due to size and weight reduction of the battery pack, which accounts for approximately 60% of the total weight of a wireless handset.
s The InP HBT is, on the contrary, is an ideal candidate for 1.5V operation, since it has a lower turn on voltage, and also offers higher gain and higher efficiency than the GaAs HBT due to its intrinsic advantages of higher mobilities, faster non-equilibrium transport velocities and lower surface recombination.
to The InP HBT, based on InAIAs (or graded AIInGaAs)/InGaAs heterojunction material structure, has been fabricated on an InP substrate.
Please refer to FIG. 1, which is a schematic cross-sectional view illustrating an example of material structure an InP-based HBT in the prior art. As can be seen in the drawing, the epitaxially grown material structure comprises a is semi-insulating InP substrate 10; a heavily doped n-type InGaAs layer 12, forming an ohmic contact for the collector of said InP-based HBT; a lightly doped n-type InGaAs layer 13, forming the collector of said InP-based HBT; a heavily doped p-type InGaAs layer 14, forming the base and an ohmic contact for the base of said InP-based HBT; an n-type InAIAs (or Zo graded AIInGaAs) layer 15, forming the emitter of said InP-based HBT;
and a heavily doped n-type InGaAs layer 16, forming an ohmic contact for the emitter of said InP-based HBT.
Therefore, the InP-based HBT has advantages of providing higher maximum frequency of operation and cutoff frequency for significantly Zs lower noise figure, higher gain and better efficiency. This is due to the fact that the InP-based HBT has high indium content, and thus has higher electron velocity, current density, and transconductance. Although InP HBTs are very attractive for low voltage and high efficiency operation especially in use in the PAs of the cellular phones, they are, however, difficult to process 30 (primarily due to the InP substrate). Furthermore, the InP wafer is very fragile, costly (about 10 times of GaAs) and presently limited to only 3-in.
in size. On the contrary, the processing technology for GaAs HBTs has higher yield and lower cost (presently 40% less), if 6-in. wafers are used.
Accordingly, there is a need for a new device with both high efficiency, low voltage operation and low manufacturing cost.
SUMMARY OF THE INVENTION
It is therefore a main object of the present invention to provide a new metamorphic heterojunction bipolar transistor having material structure s with high efficiency, low voltage operation.
It is another object of the present invention to provide a new metamorphic heterojunction bipolar transistor having material structure with low manufacturing cost.
In order to accomplish the foregoing objects, the present invention to provides a metamorphic heterojunction bipolar transistor (MHBT), having a material structure for low cost fabrication on large size gallium arsenide (GaAs) wafers, comprising: a semi-insulating GaAs substrate; an undoped metamorphic buffer layer, such as AIGaAsSb or AIInGaAs buffer; a heavily doped n-type InGaAs layer, forming an ohmic contact for the ~ s collector of said MHBT; a lightly doped n-type InGaAs layer or InP or InAIAs layer, forming the collector of said MHBT; a heavily doped p-type InGaAs layer, forming the base and an ohmic contact for the base of said MHBT; an n-type InAIAs layer or graded AIInGaAs or InP layer, forming the emitter of said MHBT; and a heavily doped n-type InGaAs layer, Zo forming an ohmic contact for the emitter of said MHBT.
It is preferable that said material structure is epitaxially grown on large size GaAs wafers with diameters of six inches or larger.
BRIEF DESCRIPTION OF THE DRAWINGS
The object, features and advantages of the present invention will be as readily understood from the following descriptions of the preferred embodiment with reference to the drawings, in which:
FIG. 1 is a schematic cross-sectional view illustrating an example of material structure of an InP-based HBT in the prior art.
FIG. 2 is a schematic cross-sectional view illustrating an example of ~o material structure of an MHBT in accordance with the preferred embodiment of the present invention.
Table 1 shows the comparisons of present power transistor technologies for wireless handsets.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Please refer to FIG. 2, which is a schematic cross-sectional view s illustrating an example of material structure of an MHBT in accordance with the preferred embodiment of the present invention. As shown in the drawing, the epitaxially grown material structure comprises: a semi-insulating GaAs substrate 20; an undoped metamophic buffer layer, such as AIGaAsSb or AIInGaAs buffer layer 21; a heavily doped n-type InGaAs ~o layer 22, forming an ohmic contact for the collector of said MHBT; a lightly doped n-type InGaAs or InP or InAIAs layer 23, forming the collector of said MHBT; a heavily doped p-type InGaAs layer 24, forming the base and an ohmic contact for the base of said MHBT; an n-type InAIAs (or graded AIInGaAs or InP) layer 25, forming the emitter of said is MHBT; and a heavily doped n-type InGaAs layer 26, forming an ohmic contact for the emitter of said MHBT.
It is notable that the MHBT material structure featuring a buffer layer 21 sandwiched between the substrate 20 and the collector contact layer 22.
This allows the MHBT to employ the InP-based HBT active structure Zo 2226 on a GaAs substrate20, since the buffer layer 21 makes a lattice-constant transition between the GaAs substrate 20 and high-indium epitaxially grown layers 2226 lattice-matched to InP 10.
Therefore, the MHBT has the InP-based HBT performance but with the GaAs wafer 20 processing cost. Particularly, the use of a GaAs Zs substrate in MHBT allows a production of very high performance devices/MMICs with very low substrate and wafer processing cost. The chip cost of MHBTs can be further reduced when a larger size GaAs wafer, for instance 6-in. is used. It is notable that 6-in. GaAs wafers are available, but only 3-in. InP wafers are available. The lattice constant shifting buffer 3o growth technology needed in the MHBT is currently commercially available (e.g. epi houses such as IQE in U.S.A. and Picogiga in France).
The metamorphic technology also allows a wider range of Al and In compositions in the material structure, providing an excellent potential for even higher performance, such as higher breakdown and efficiency, than that of the conventional InP-based HBT.
To sum up, let us review the previously disclosed arts and the present s invention, we will find, in Table 1, that the advantages of the new MHBT
include:
( 1 ) ten times lower substrate cost of the same size, (2) less fragile substrate for improved line yield, (3) easy to process backside of the wafer, translating to 40% cost to savings in processing, (4) larger wafer size available for very low cost chip production.
Although the present invention has been disclosed and illustrated with reference to the preferred embodiments, the principles involved are susceptible for use in numerous other embodiments that will be apparent to Is persons skilled in the art such that modifications and changes may be made to the present invention without departing from the spirit and scope thereof.
This invention is, therefore, to be determined not with reference to the above description but with reference to the appended claims along with their full scope of equivalents.
s Table 1 Comparisons of power transistor technologies for wireless handsets Transistor Key Elements Remarks Technology GaAs HBT AIGaAs(or InGaP)/ Good reliability, mature InGaAs heterojunctiontechnology GaAs substrate Low cost Production read InP HBT AIInAs(or graded Difficult to process AIInGaAs or InP)/ High substrate and InGaAs/ (or InP processing cost or InAIAs) Limited substrate size Hereojunction available InP substrate Not suitable for manufacturing MHBT AIInAs(or graded GaAs-like processing AIInGaAs or InP)/ 6" substrates available InGaAs(or InP Low cost, suitable for or InAIAs) manufacturing /AIGaAsSb(or Flexibility of Layer AIInGaAs) compositions provides Heterojunction even higher Lattice constant breakdown shifting buffer and efficiency than GaAs substrate conventional InP HBTs
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Please refer to FIG. 2, which is a schematic cross-sectional view s illustrating an example of material structure of an MHBT in accordance with the preferred embodiment of the present invention. As shown in the drawing, the epitaxially grown material structure comprises: a semi-insulating GaAs substrate 20; an undoped metamophic buffer layer, such as AIGaAsSb or AIInGaAs buffer layer 21; a heavily doped n-type InGaAs ~o layer 22, forming an ohmic contact for the collector of said MHBT; a lightly doped n-type InGaAs or InP or InAIAs layer 23, forming the collector of said MHBT; a heavily doped p-type InGaAs layer 24, forming the base and an ohmic contact for the base of said MHBT; an n-type InAIAs (or graded AIInGaAs or InP) layer 25, forming the emitter of said is MHBT; and a heavily doped n-type InGaAs layer 26, forming an ohmic contact for the emitter of said MHBT.
It is notable that the MHBT material structure featuring a buffer layer 21 sandwiched between the substrate 20 and the collector contact layer 22.
This allows the MHBT to employ the InP-based HBT active structure Zo 2226 on a GaAs substrate20, since the buffer layer 21 makes a lattice-constant transition between the GaAs substrate 20 and high-indium epitaxially grown layers 2226 lattice-matched to InP 10.
Therefore, the MHBT has the InP-based HBT performance but with the GaAs wafer 20 processing cost. Particularly, the use of a GaAs Zs substrate in MHBT allows a production of very high performance devices/MMICs with very low substrate and wafer processing cost. The chip cost of MHBTs can be further reduced when a larger size GaAs wafer, for instance 6-in. is used. It is notable that 6-in. GaAs wafers are available, but only 3-in. InP wafers are available. The lattice constant shifting buffer 3o growth technology needed in the MHBT is currently commercially available (e.g. epi houses such as IQE in U.S.A. and Picogiga in France).
The metamorphic technology also allows a wider range of Al and In compositions in the material structure, providing an excellent potential for even higher performance, such as higher breakdown and efficiency, than that of the conventional InP-based HBT.
To sum up, let us review the previously disclosed arts and the present s invention, we will find, in Table 1, that the advantages of the new MHBT
include:
( 1 ) ten times lower substrate cost of the same size, (2) less fragile substrate for improved line yield, (3) easy to process backside of the wafer, translating to 40% cost to savings in processing, (4) larger wafer size available for very low cost chip production.
Although the present invention has been disclosed and illustrated with reference to the preferred embodiments, the principles involved are susceptible for use in numerous other embodiments that will be apparent to Is persons skilled in the art such that modifications and changes may be made to the present invention without departing from the spirit and scope thereof.
This invention is, therefore, to be determined not with reference to the above description but with reference to the appended claims along with their full scope of equivalents.
s Table 1 Comparisons of power transistor technologies for wireless handsets Transistor Key Elements Remarks Technology GaAs HBT AIGaAs(or InGaP)/ Good reliability, mature InGaAs heterojunctiontechnology GaAs substrate Low cost Production read InP HBT AIInAs(or graded Difficult to process AIInGaAs or InP)/ High substrate and InGaAs/ (or InP processing cost or InAIAs) Limited substrate size Hereojunction available InP substrate Not suitable for manufacturing MHBT AIInAs(or graded GaAs-like processing AIInGaAs or InP)/ 6" substrates available InGaAs(or InP Low cost, suitable for or InAIAs) manufacturing /AIGaAsSb(or Flexibility of Layer AIInGaAs) compositions provides Heterojunction even higher Lattice constant breakdown shifting buffer and efficiency than GaAs substrate conventional InP HBTs
Claims (3)
1.A metamorphic heterojunction bipolar transistor (MHBT) having a material structure for low cost fabrication on large size gallium arsenide (GaAs) wafers with six inches or larger, comprising:
a semi-insulating GaAs substrate;
an undoped metamorphic buffer layer;
a heavily doped n-type InGaAs layer, forming an ohmic contact for the collector of said MHBT;
a lightly doped n-type layer forming the collector of said MHBT, wherein the lightly doped n-type layer is In GaAs, or InP or InAlAs;
a heavily doped p-type InGaAs layer, forming the base and an ohmic contact for the base of said MHBT;
a layer forming the emitter of said MHBT, wherein the layer is an n-type InAlAs layer, or an graded n-type AlInGaAs layer, or an n-type InP
layer; and a heavily doped n-type InGaAs layer, forming an ohmic contact for the emitter of said MHBT.
a semi-insulating GaAs substrate;
an undoped metamorphic buffer layer;
a heavily doped n-type InGaAs layer, forming an ohmic contact for the collector of said MHBT;
a lightly doped n-type layer forming the collector of said MHBT, wherein the lightly doped n-type layer is In GaAs, or InP or InAlAs;
a heavily doped p-type InGaAs layer, forming the base and an ohmic contact for the base of said MHBT;
a layer forming the emitter of said MHBT, wherein the layer is an n-type InAlAs layer, or an graded n-type AlInGaAs layer, or an n-type InP
layer; and a heavily doped n-type InGaAs layer, forming an ohmic contact for the emitter of said MHBT.
2.The MHBT as recited in claim 1, wherein said undoped metamorphic buffer layer is AlGaAsSb buffer layer.
3.The MHBT as recited in claim 1, wherein said undoped metamorphic buffer layer is AlInGaAs buffer layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15802699P | 1999-10-07 | 1999-10-07 | |
| US60/158,026 | 1999-10-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2322080A1 true CA2322080A1 (en) | 2001-04-07 |
Family
ID=22566406
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002322080A Abandoned CA2322080A1 (en) | 1999-10-07 | 2000-10-03 | New metamorphic heterojunction bipolar transistor having material structure for low cost fabrication on large size gallium arsenide wafers |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP2001144101A (en) |
| KR (1) | KR100400486B1 (en) |
| CN (1) | CN1296291A (en) |
| CA (1) | CA2322080A1 (en) |
| DE (1) | DE10049148A1 (en) |
| FR (1) | FR2799884A1 (en) |
| GB (1) | GB2358959B (en) |
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| US7122734B2 (en) | 2002-10-23 | 2006-10-17 | The Boeing Company | Isoelectronic surfactant suppression of threading dislocations in metamorphic epitaxial layers |
| JP2006210452A (en) * | 2005-01-26 | 2006-08-10 | Sony Corp | Semiconductor apparatus |
| CN100452303C (en) * | 2005-05-24 | 2009-01-14 | 中国科学院微电子研究所 | Metal alloy system suitable for ohmic contact of high-speed gallium arsenide-based device |
| RU2474923C1 (en) * | 2011-06-23 | 2013-02-10 | Учреждение Российской академии наук Институт сверхвысокочастотной полупроводниковой электроники РАН (ИСВЧПЭ РАН) | SEMICONDUCTOR METAMORPHIC NANOHETEROSTRUCTURE InAlAs/InGaAs |
| RU2474924C1 (en) * | 2011-08-08 | 2013-02-10 | Учреждение Российской академии наук Институт сверхвысокочастотной полупроводниковой электроники РАН (ИСВЧПЭ РАН) | Semiconductor nanoheterostructure inalas/ingaas with metac metamorphic buffer |
| CN102651417B (en) * | 2012-05-18 | 2014-09-03 | 中国科学院苏州纳米技术与纳米仿生研究所 | Three-knot cascading solar battery and preparation method thereof |
| US20170084771A1 (en) * | 2015-09-21 | 2017-03-23 | The Boeing Company | Antimonide-based high bandgap tunnel junction for semiconductor devices |
| CN110970340B (en) * | 2019-10-31 | 2022-06-10 | 中国电子科技集团公司第五十五研究所 | Flexible InP HBT device and preparation method thereof |
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| JPH0432220A (en) * | 1990-05-28 | 1992-02-04 | Mitsubishi Electric Corp | Structure of semiconductor buffer layer |
| JPH0590283A (en) * | 1991-09-30 | 1993-04-09 | Nec Corp | Semiconductor device |
| FR2692721B1 (en) * | 1992-06-17 | 1995-06-30 | France Telecom | METHOD FOR PRODUCING A BIPOLAR HETEROJUNCTION TRANSISTOR AND TRANSISTOR OBTAINED. |
| US5404028A (en) * | 1993-01-22 | 1995-04-04 | Hughes Aircraft Company | Electrical junction device with lightly doped buffer region to precisely locate a p-n junction |
| JPH06318606A (en) * | 1993-05-10 | 1994-11-15 | Mitsubishi Electric Corp | Semiconductor device, hbt, and hemt |
| US5631477A (en) * | 1995-06-02 | 1997-05-20 | Trw Inc. | Quaternary collector InAlAs-InGaAlAs heterojunction bipolar transistor |
| KR100243409B1 (en) * | 1996-12-12 | 2000-02-01 | 이계철 | Method for forming epi-layer of pnp/npn compound semiconductor hbt on the same plane |
| JP2000150529A (en) * | 1998-11-06 | 2000-05-30 | Furukawa Electric Co Ltd:The | Epitaxial wafer for hetero junction bi-polar transistor |
| JP2000223498A (en) * | 1999-01-28 | 2000-08-11 | Sharp Corp | Fabrication of semiconductor device and heterojunction bipolar transistor, and amplifier |
-
2000
- 2000-08-24 GB GB0020938A patent/GB2358959B/en not_active Expired - Fee Related
- 2000-09-04 CN CN00124312A patent/CN1296291A/en active Pending
- 2000-09-26 JP JP2000292682A patent/JP2001144101A/en active Pending
- 2000-10-03 CA CA002322080A patent/CA2322080A1/en not_active Abandoned
- 2000-10-04 DE DE10049148A patent/DE10049148A1/en not_active Withdrawn
- 2000-10-05 KR KR10-2000-0058495A patent/KR100400486B1/en not_active IP Right Cessation
- 2000-10-06 FR FR0012813A patent/FR2799884A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| KR100400486B1 (en) | 2003-10-01 |
| FR2799884A1 (en) | 2001-04-20 |
| JP2001144101A (en) | 2001-05-25 |
| GB0020938D0 (en) | 2000-10-11 |
| DE10049148A1 (en) | 2001-04-19 |
| KR20010050866A (en) | 2001-06-25 |
| CN1296291A (en) | 2001-05-23 |
| GB2358959B (en) | 2002-01-16 |
| GB2358959A (en) | 2001-08-08 |
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