JP2000150529A - Epitaxial wafer for hetero junction bi-polar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an epitaxial wafer for a hetero junction bi-polar transistor that functions as an etching stop layer, can accurately position a base electrode, and can improve the manufacturing yield of HBT. SOLUTION: In an epitaxial wafer for the hetero junction bi-polar transistor based on GaAs, at least a collector layer 3, a base layer 4, an AlX2Ga1-X2As emitter layer 5, a graded layer 16, and GaAs cap layer 8a are sequentially laminated on a GaAs substrate 1. In the graded layer 16, AlXGa1-XAs graded layers 16a-16c and InYAlZGa1-Y-ZAs layer 16d are sequentially laminated from the side of the emitter layer. An Al composition X of AlXGa1-XAs graded layers 16a-16c is reduced from the side of the emitter layer 5 to the side of the cap layer 8a, and X becomes equal to X1 at the side of the cap layer 8a. The above Al composition X, an In composition Y of the InYAlZGa1-Y-ZAs layer, and an Al composition Z meet the conditions of X1<=X<=X2, Y<=0.25, 0.2<=Z<=0.3, and 0<=Z-Y<=X1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor (HBT).
ransistor).

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been vigorously researched and developed for higher integration and higher speed. In particular, a heterojunction bipolar transistor (hereinafter, referred to as an HBT) using a heterojunction of a compound semiconductor is expected to have a high emitter injection efficiency, a high gain and a high speed, and is attracting attention as a next-generation semiconductor device. Conventional GaAs HBT
Is, for example, as shown in FIG.
A sub-collector layer 2, a collector layer 3, a base layer 4, an emitter layer 5, an inclined layer 6, a ballast layer 7, and a cap layer 8 are sequentially laminated on a substrate 1. Collector electrode 9 is formed on subcollector layer 2. Further, the base electrode 10 has a thin lower emitter layer 5a below the emitter layer 5.
It is formed on the base layer 4 with a thickness of, for example, 20 nm. Further, the emitter electrode 11 is formed on the cap layer 8.

This HBT is manufactured from, for example, an epitaxial wafer shown in FIG. The collector layer 3
It is made of n-GaAs having a low carrier concentration such as a thickness of 800 nm and a carrier concentration of 5 × 10 ¹⁶ cm ⁻³ . If the collector electrode is formed directly on the collector layer 3 having a low carrier concentration, the collector resistance increases, so the sub-collector layer 2 having a high carrier concentration is provided. Subcollector layer 2
Is made of n-GaAs having a high carrier concentration such as a thickness of 500 nm and a carrier concentration of 5 × 10 ¹⁸ cm ⁻³ . The base layer 4 has a thickness of 70 nm and a carrier concentration of 4 ×
It is made of p-GaAs as high as 10 ¹⁹ cm ⁻³ . The emitter layer 5 has a thickness of 200 nm and a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ Al _x Ga ₁ -x As (X = 0.2
5). The graded layer 6 has a thickness of 40 nm, a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ , and an Al _X Ga _{1 -X} As (X: 0.2
5 → 0). This inclined layer 6 has the following functions. That is, when the emitter layer 5 and the following ballast layer 7 are directly joined, the potential barrier formed by the band gap difference of the Al _x Ga ₁ -x As / GaAs junction becomes a barrier for the current injected from the emitter electrode 11. . The gradient layer 6 is for alleviating this potential barrier. The ballast layer 7 is for suppressing thermal runaway during the HBT operation, and is made of GaAs having a thickness of 250 nm and a carrier concentration of 5 × 10 ¹⁶ cm ⁻³ . Further, the cap layer 8 is provided to reduce the contact resistance of the emitter electrode 11, and has a thickness of 100 nm, a GaAs layer 8a having a carrier concentration of 5 × 10 ¹⁸ cm ⁻³ , and an In composition increasing upward. An In _Y Ga _1-Y As composition gradient layer 8b (Y: 0 → 0.5) having a thickness of 30 nm and a carrier concentration of 1 × 10 ¹⁹ cm ⁻³ , and a thickness of 50 nm and a carrier concentration of 2 × 10 ¹⁹ cm ^−3. In _0.5 Ga _0.5 As layer 8 of ¹⁹ cm ^-3
c. Here, the GaAs layer 8a, In _Y Ga _1-Y
The reason for providing the As composition gradient layer 8b is that In _0.5 Ga _0.5
This is because, when the As layer 8c is directly laminated on the ballast layer 7, a notch is formed in the valence band due to discontinuity of the band gap, which hinders conduction.

[0004]

As described above, the base electrode 10 is formed on the base layer 4 via the thin lower emitter layer 5a (for example, 20 nm thick) in which the emitter layer 5 is thinned. Since the lower emitter layer 5a needs to be depleted, its thickness needs to be accurately formed. However, it is difficult to control the thickness with high accuracy, and there is a problem that the production yield of the HBT is reduced. The reason will be described below.

Conventionally, in order to form the base electrode 10, as shown in FIG. 4A, an epitaxial wafer is formed from an In _0.5 Ga _0.5 As layer 8c to a lower emitter layer 5a.
The surface had been etched. For example, in the epitaxial wafer shown in FIG. 4B, since the thickness from the surface of the In _0.5 Ga _0.5 As layer 8c to the lower part of the emitter layer 5 (the surface of the base layer 4) is 670 nm, the etching amount for forming the base electrode 10 is 650 nm. Become. The control of the etching amount is performed by measuring the etching rate in advance and controlling the etching time. However, such a method of controlling the etching amount has the following problems. That is, 1) the etching amount varies within the epitaxial wafer surface. 2) From the surface of the In _0.5 Ga _0.5 As layer 8c to the emitter layer 5
If the thickness of the laminate up to the lower portion (the surface of the base layer 4) varies, the thickness of the remaining lower emitter layer 5a after the etching varies even if the etching time is accurately controlled.

Incidentally, the accuracy of etching can be improved by reducing the amount of etching. Therefore, the lower emitter layer 5a
The etching reaching the lower emitter layer 5a is performed in two separate steps, and the amount of the second etching reaching the lower emitter layer 5a is reduced.
The accuracy of the thickness of the remaining lower emitter layer 5a after the etching can be improved.

[0007] For example, using selective etching to etch first from the epitaxial wafer surface to the ballast layer 7 and then from the inclined layer 6 to the lower emitter layer 5a, the second etching amount is 220
nm and the total etching amount of 650 nm 1
/ 3. Therefore, the accuracy of the second etching amount is
This is improved as compared with the case where the entire etching is performed once.

However, in the composition of the gradient layer 6, since the Al composition increases from the upper part to the lower part, the stop position of the first selective etching becomes unclear, and the second etching amount must be set accurately. However, there is a problem that the production yield of the HBT is reduced. The present invention
HBT having graded layer with function of etching stop layer
It is an object of the present invention to provide an epitaxial wafer for use, to accurately set a second etching amount, and to improve the production yield of HBT.

[0009]

The present invention solves the above problems.
It was decided to make at least on the GaAs substrate
Collector layer, base layer, Al_X2Ga_1-X2As emitter
Layer in which a layer, a gradient layer, and a GaAs cap layer are sequentially stacked
Epitaxy for aAs-based heterojunction bipolar transistor
In the axial wafer, the inclined layer is
Al_XGa_1-XAs graded layer and In_YAl_ZGa
_1-YZAs layers are sequentially laminated, and Al_XGa _1-XAs
The Al composition X of the gradient layer is from the emitter layer side to the cap layer side.
, X = X on the cap layer side₁And above
Al composition X, In_YAl_ZGa_1-YZIn layer of As layer
The composition Y and the Al composition Z are represented by X₁≤X≤X_Two (1) Y ≦ 0.25 (2) 0.2 ≦ Z ≦ 0.3 (3) 0 ≦ Z−Y ≦ X₁ (4) is satisfied.

The present invention has been obtained as a result of intensive studies. According to the present invention, the above composition conditions (1)
When the gradient layer satisfying the conditions (4) to (4) is laminated on the emitter layer, the original function of the gradient layer (reducing the potential barrier of the current injected from the emitter electrode) is not deteriorated and the etching stop layer of the selective etching is not damaged. A function can be provided, and a thin emitter layer interposed between the base electrode and the base layer can be accurately formed to a desired thickness.

That is, when the In _Y Al _Z Ga _1-YZ As layer satisfies the composition conditions (2) and (3), the In _Y Al _Z Ga
_{When a} GaAs layer is stacked on the _1-YZ As layer, if citric acid / ammonia / hydrogen peroxide is used as an etchant, the In _Y Al _Z Ga _1-YZ As layer becomes an etching stop layer, so that selective etching can be performed. it can. Also, I
When the band gap of the n _Y Al _Z Ga _{1 -YZ} As layer becomes large, the function as a gradient layer is impaired. However, when the composition condition (4) is satisfied, the band gap is prevented from expanding and the function of the gradient layer can be maintained. . Note that the composition condition (1) is a condition for the composition of the gradient layer to be gradient.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
This will be described in detail. FIG. 1 is a diagram showing an HBT air supply according to the present invention.
FIG. 3 is a cross-sectional view of one embodiment of a epitaxial wafer. Figure 1
Indicates the same parts as those described with reference to FIG.
I have. This embodiment is based on a semi-insulating GaAs substrate 1.
Has a thickness of 500 nm and a carrier concentration of 5 × 10¹⁸cm^-3
Sub-collector layer 2 of n-GaAs, thickness 800
nm, carrier concentration is 5 × 10¹⁶cm^-3N-GaAs
Layer 3 of thickness 70 nm, carrier concentration
4 × 10¹⁹cm^-3A base layer 4 made of p-GaAs,
200 nm thickness, 5 × 10 carrier concentration¹⁷cm^-3A
l_X2Ga_1-X2As (X _Two= 0.25)
Layer 5, graded layer 16, thickness 250 nm, carrier concentration 5
× 10¹⁶cm^-3Ballast layer 7 of GaAs, thickness
100 nm, carrier concentration 5 × 10¹⁸cm^-3G that is
a As layer 8a, the In composition increases upward, and the thickness increases.
30 nm, carrier concentration 1 × 10¹⁹cm^-3I
n_YGa _1-YAs composition gradient layer 8b (Y: 0 → 0.5)
And a carrier concentration of 2 × 10¹⁹cm^-3so
Some In_0.5a_0.5The cap layer 8 composed of the As layer 8c
These are sequentially laminated.

The inclined layer 16 is, from the emitter layer 5 side, an Al _0.2 Ga _0.8 As layer 16 a having a thickness of 10 nm and a carrier concentration of 5 × 10 ¹⁷ cm ^-3 , and an Al _0.15 Ga _0.85 layer.
As layer 16b, Al _0.1 Ga _0.9 As layer 16c, In _Y
The Al _Z Ga _1-YZ As layer 16d is obtained by sequentially stacking. In this case, Al composition X ₁ on the surface side of the graded layer 16 becomes 0.1.

Here, the In _Y Al _Z Ga _{1 -YZ} As layer 1
The following experiment was performed to examine the selective etching property of 6d. That is, as shown in FIG. 2, a GaAs layer 22 having a thickness of 200 nm and an In _Y Al _Z Ga
_An epitaxial wafer is manufactured by sequentially laminating a _1-YZ As layer 23 and a GaAs layer 24 having a thickness of 200 nm, and a known citric acid / ammonia / hydrogen peroxide etchant (IEICE Technical Report)
ED93-99 (see 1993-10)). I
by changing the n _Y Al _Z composition and thickness of the Ga _1-YZ As layer 23 shows the results of measuring the amount of etching in Table 1. In addition,
The etching amount is a value obtained when etching is performed for 1.5 times the time required for etching the GaAs layer 24. Therefore, if the etching amount is 200 nm or less, the In _Y Al _Z Ga _{1 -YZ} As layer 23 is not etched, indicating that it has the function of an etching stop layer.

[0015]

As can be seen from Table 1, 0.2 ≦ Z ≦ 0.
3 (composition condition (3) of the present invention) and Y ≦ 0.25 (composition condition (2) of the present invention), the etching amount is G
The thickness of the aAs layer 22 does not exceed about 200 nm, and
_Y Al _Z Ga _1-YZ As layer 23 has a function of etch stop layer.

It should be noted that In _Y Al _Z Ga _{1 -YZ} As is In
If the composition Y is high, the lattice constant increases, so that a lattice mismatch occurs between GaAs and AlGaAs. In the above experiment, No. No lattice mismatch occurred in the samples Nos. 1 to 5 and N
o. In the sample No. 6 (thickness: 10 nm), slight cross hatching was observed on the surface, and slight lattice mismatch occurred. However, even if Y is 0.25, the thickness is 5n.
m. In the sample No. 7, no cross hatch was observed. Therefore, under the condition of the etching stop layer, that is, Y ≦ 0.25, the thickness (critical film thickness) at which lattice mismatch does not occur can be made about 10 nm.

Next, for the epitaxial wafer shown in FIG. 1, as shown in Table 2, In _Y Al _Z Ga _{1 -YZ} A
By changing the composition Y and Z of the s layer 16d, the samples (No.
4) was produced. Note that the sample (No. 1) has the inclined layer 16
The sample (No. 2) having no
_{n Y Al Z Ga 1-YZ} As layer 16d excluding the (in other words, equivalent to a conventional example) is.

[0019]

The evaluation of the sample was made based on whether or not the original function of the gradient layer 16 (reducing the potential barrier of the current injected from the emitter electrode) was impaired. Therefore, the sample was subjected to etching including selective etching with the citric acid / ammonia / hydrogen peroxide etchant to form a lower emitter layer as shown in FIG. 4A and position the base electrode. For the conventional example (sample No. 2), the base electrode was positioned by etching using a conventional time management method. Then, to see the effect of the potential barrier,
The emitter resistance was measured, and the emitter resistance (7.2Ω) of the conventional example (Sample No. 2) did not greatly exceed (7.2.Ω).
0 Ω or less).

As shown in Table 2, 3, 4, 5, 8, 9, 1
It can be seen that the samples Nos. 0, 12, and 13 satisfy the potential barrier relaxation conditions. The above sample (No. 3 to 1)
If 4) is positioned on the (Z, Y) coordinates indicating the In composition Y and the Al composition Z, the result is as shown in FIG. As can be seen from FIG. 3, the range of Z−0.1 ≦ Y ≦ Z, in other words,
In a sample satisfying the composition condition (4), 0 ≦ Z−Y ≦ 0.1 (corresponding to the value of X ₁ ), the emitter resistance becomes 9.0Ω or less, and the potential barrier is reduced. ing. On the other hand, a sample (No. 6,
In Nos. 7 and 11), the emitter resistance value exceeds 9.0Ω, and the influence of the potential barrier appears.

[0022] The above embodiments are Al _X Ga _1-X As the composition of the surface side of the graded layer is Al _0.1 Ga _{0. 9} As layer 16c, but is equivalent to X ₁ = 0.1, X ₁ is 0.
Even if it was not 1, it was recognized that the potential barrier was relaxed in the range of the composition condition (4).

As described above, when the gradient layer 16 satisfies the composition condition (2), the critical film thickness can be sufficiently increased (for example, 10 nm) without causing lattice mismatch, and the composition condition (3) When satisfied, the etching selectivity is improved, and the positioning of the base electrode can be performed with high accuracy.
Further, when the composition condition (4) is satisfied, the potential barrier is relaxed, and the original function of the gradient layer 16 can be achieved. Therefore, by satisfying the composition conditions (1) to (4), the gradient layer 16 can have the function of the etching stop layer without impairing the function as the gradient layer.

[0024]

As described above, according to the present invention, since the inclined layer has a function as an etching stop layer, the base electrode can be accurately positioned, and the production yield of the HBT can be improved. There is an excellent effect.

[Brief description of the drawings]

FIG. 1 is a sectional view of an embodiment of an epitaxial wafer for HBT according to the present invention.

FIG. 2 is a cross-sectional view of an epitaxial wafer for examining selective etching properties.

FIG. 3 shows In _Y Al _Z Ga _{1 -YZ} As forming a gradient layer.
FIG. 4 is a diagram showing a relationship between an In composition Y and an Al composition Z of a layer and an emitter resistance.

4A and 4B are a partial sectional view of a conventional HBT and a sectional view of an HBT epitaxial wafer, respectively.

[Explanation of symbols]

1 GaAs substrate 2 subcollector layer 3 a collector layer 4 base layer 5 emitter layer 5a lower emitter layer 6,16 graded layer 7 ballast layer 8 capping layer 8a GaAs layer 8b In _Y Ga _1-Y As gradient composition layer 8c In _0.5 Ga _0.5 As layer 9 the collector electrode 10 base electrode 11 emitter electrode 16a Al _0.2 Ga _0.8 As layer 16b Al _0.15 Ga _0.85 As layer 16c Al _0.1 Ga _0.9 As layer _{16d In Y Al Z Ga 1-} YZ As layer

Claims (1)

[Claims] At least a collector is provided on a GaAs substrate.
Layer, base layer, Al_X2Ga_1-X2As emitter layer, graded layer
And a GaAs cap layer in this order.
Epitaxial for heterojunction bipolar transistor
In the wafer, the inclined layer is made of Al from the emitter layer side._XGa
_1-XAs graded layer and In_YAl_ZGa _1-YZAs layer
Layered in order, Al_XGa_1-XAl group of As graded layer
X decreases from the emitter layer side to the cap layer side.
X = X on the cap layer side₁And the above Al composition X,
In_YAl_ZGa_1-YZIn composition Y and Al of As layer
Composition Z is X₁≤X≤X_Two Y ≦ 0.25 0.2 ≦ Z ≦ 0.3 0 ≦ Z−Y ≦ X₁ Heterojunction bipolar characterized by satisfying the following conditions:
Epitaxial wafer for transistors.