CN115566057A - Heterojunction bipolar transistor and manufacturing method thereof - Google Patents

Heterojunction bipolar transistor and manufacturing method thereof Download PDF

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CN115566057A
CN115566057A CN202211393727.1A CN202211393727A CN115566057A CN 115566057 A CN115566057 A CN 115566057A CN 202211393727 A CN202211393727 A CN 202211393727A CN 115566057 A CN115566057 A CN 115566057A
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ingap
gaas
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李峰柱
王冲
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Smic Yuezhou Integrated Circuit Manufacturing Shaoxing Co ltd
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Smic Yuezhou Integrated Circuit Manufacturing Shaoxing Co ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
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    • H01L29/0804—Emitter regions of bipolar transistors
    • H01L29/0817—Emitter regions of bipolar transistors of heterojunction bipolar transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors

Abstract

The invention provides a heterojunction bipolar transistor and a manufacturing method thereof.A 1 st InGaP emitter region layer to an m-th InGaP emitter region layer of a first conduction type are formed on a GaAs base region layer of a second conduction type, and each InGaP emitter region layer contains In y Ga 1‑y P, and y from the 1 st InGaP emitter region layer to the m-th InGaP emitter region layer decreases layer by layer, m is not less than 3 and isAnd the integral number is integral, so that a gradual change band gap difference is formed between the 1 st to m layers of InGaP emitting region layers and the material of the P GaAs base region layer on the whole, the potential barrier peak at the InGaP/GaAs heterojunction is effectively reduced, the Vbe of the HBT during working is prevented from being increased, and the performance of the device is improved.

Description

Heterojunction bipolar transistor and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a heterojunction bipolar transistor and a manufacturing method thereof.
Background
A Heterojunction Bipolar Transistor (HBT) is a Transistor structure formed by replacing a Heterojunction with a homogeneous emitter Junction of a wide band gap semiconductor material, i.e., a BJT, on the basis of a Bipolar Junction Transistor (BJT), and has the advantages of high speed, low power consumption, and the like.
For example, as shown in fig. 1, a conventional HBT has a specific structure including a GaAs substrate layer 100, an n GaAs sub-collector layer 101, an n GaAs collector layer 102, a P GaAs base layer 103, an n InGaP emitter layer 104, an n GaAs contact layer 105, and an InGaAs contact layer 106, which are stacked in this order from bottom to top. The base 108 is embedded in the n InGaP emitter region layer 104, the collector 107 is formed on the n GaAs sub-collector region layer 101, and the emitter 109 is formed on the InGaAs contact layer 106. The n InGaP emitter region layer 104 forms a heterojunction with the P GaAs base region layer 103, and serves as a passivation layer when the base 108 is formed.
Referring to fig. 2, the n InGaP emitter layer 104 is typically In 0.5 Ga 0.5 P semiconductor material, i.e., the In fraction In the n InGaP emitter layer 104 is constant with thickness.
On one hand, referring to fig. 3, in the npn HBT, because there is an inherent band gap difference between the two materials of the n InGaP emitter region layer 104 and the P GaAs base region layer 103, a barrier peak exists at the InGaP/GaAs heterojunction, which causes the turn-on voltage Vbe to be high during the HBT operation; on the other hand, the formation of the base 108 generally requires the use of an annealing process, but since its n InGaP emitter layer 104 uses In 0.5 Ga 0.5 P semiconductor material (Bulk InGaP) is formed, and n-type impurities (e.g., si) of the InGaP emitter layer are low-doped (doping concentration of Si is about 2e 17/cm) 3 ) Therefore, it is easy to cause incomplete contact annealing process between the base electrode 108 and the n InGaP emitter region layer 104, so that the base electrode 108 cannot penetrate through the n InGaP emitter region layer 104 to contact the P GaAs base region layer 103, which results in that a good ohmic contact cannot be formed between the base electrode 108 and the PGaAs base region layer 103, and the base region series resistance is increased, thereby further increasing the turn-on voltage Vbe when the HBT operates.
Disclosure of Invention
The invention aims to provide a Heterojunction Bipolar Transistor (HBT) and a manufacturing method thereof, which can reduce barrier peak of InGaP/GaAs heterojunction and enable the turn-on voltage Vbe to be reduced when the HBT works.
In order to achieve the above object, the present invention provides a heterojunction bipolar transistor comprising, stacked in order from bottom to top:
a GaAs substrate layer;
a first conductivity type GaAs collector layer;
a GaAs base region layer of a second conductivity type;
from the 1 st InGaP emitter region layer to the m-th InGaP emitter region layer of the first conduction type, each of the InGaP emitter region layers contains In y Ga 1-y P, and y from the 1 st InGaP emitting area layer to the mth InGaP emitting area layer is reduced layer by layer, m is not less than 3 and is an integer;
and an InGaAs contact layer of the first conductivity type.
Optionally, y is more than or equal to 0.4 and less than or equal to 0.7 in each InGaP emitter region layer from the 1 st InGaP emitter region layer to the m-1 st InGaP emitter region layer, and the m-th InGaP emitter region layer is made of 0-y-0.4; or, y is more than or equal to 0.45 and less than or equal to 0.7 in each InGaP emission area layer from the 1 st InGaP emission area layer to the m-1 st InGaP emission area layer, and the m-th InGaP emission area layer is provided with 0-y-0.45.
Optionally, y of each InGaP emitter region layer is respectively constant from the 1 st InGaP emitter region layer to the m-1 st InGaP emitter region layer; the y of the mth InGaP emitter layer gradually decreases as the stack thickness increases.
Optionally, the total thickness of the stack from the 1 st InGaP emitter region layer to the m-2 nd InGaP emitter region layer is 1 nm-200 nm, the film thickness of the m-1 st InGaP emitter region layer is 1 nm-100 nm, and the film thickness of the m-1 st InGaP emitter region layer is not higher than 50nm.
Optionally, the doping concentration of the impurity of the first conductivity type in the mth InGaP emitter region layer is 5e17/cm 3 ～5e19/cm 3 (ii) a And/or the doping concentration of the impurity of the first conductivity type in at least one InGaP emitter region layer from the 1 st InGaP emitter region layer to the m-1 st InGaP emitter region layer is 5e15/cm 3 ～5e18/cm 3 。
Optionally, the ratio of the content of the group V element to the sum of the contents of the group III elements in at least one InGaP emitter layer from the 1 st InGaP emitter layer to the m-th InGaP emitter layer is 0.5 to 100.
Optionally, the heterojunction bipolar transistor further comprises: the GaAs sub-collector region layer of the first conduction type is positioned between the GaAs substrate layer and the GaAs collector region layer; and/or a GaAs contact layer of the first conduction type positioned between the InGaAs contact layer and the m-th InGaP emitter region layer.
Optionally, the heterojunction bipolar transistor further comprises:
an emitter formed on the InGaAs contact layer and having a bottom electrically contacting the InGaAs contact layer;
a collector formed on the GaAs subcollector layer and having a bottom in electrical contact with the GaAs subcollector layer and a top exposed by a film layer over the GaAs subcollector layer;
the base electrode sequentially penetrates through the 1 st InGaP emitter region layer to the mth InGaP emitter region layer from bottom to top, and the bottom of the base electrode is electrically contacted with the GaAs base region layer.
The present invention also provides, based on the same inventive concept, a method of manufacturing a heterojunction bipolar transistor as defined in any one of claims 1 to 7, comprising:
providing a GaAs substrate layer;
forming a GaAs collector region layer of a first conduction type on the GaAs substrate layer;
forming a GaAs base region layer of a second conduction type on the GaAs collector region layer;
sequentially laminating a1 st InGaP emission region layer to an m-th InGaP emission region layer of a first conduction type on the GaAs base region layer, wherein each InGaP emission region layer contains In y Ga 1-y P, and y from the 1 st InGaP emission region layer to the mth InGaP emission region layer is reduced layer by layer, m is more than or equal to 3 and is an integer;
an InGaAs contact layer of the first conductivity type is formed on the mth InGaP emitter region layer.
Optionally, the growth temperature of the 1 st InGaP emitter region layer to the m-2 nd InGaP emitter region layer is reduced layer by layer, the growth temperature of the m-2 nd InGaP emitter region layer to the m-2 th InGaP emitter region layer is reduced layer by layer or the growth temperature of at least two adjacent InGaP emitter region layers is the same.
Optionally, the forming process conditions of at least one InGaP emitter region layer from the 1 st InGaP emitter region layer to the mth InGaP emitter region layer include: the growth temperature is 400-800 ℃, the growth pressure is 50-200mbar, the ratio of the content of the V group element to the content sum of the III group element is 0.5-100.
Optionally, the manufacturing method further comprises:
forming a GaAs sub-collector region layer of a first conduction type on the GaAs substrate layer before forming the GaAs collector region layer of the first conduction type on the GaAs substrate layer;
and before the InGaAs contact layer is formed on the mth InGaP emitter region layer, a GaAs contact layer of the first conduction type is formed on the mth InGaP emitter region layer.
Optionally, forming an emitter, a collector and a base, wherein the emitter is formed on the InGaAs contact layer and the bottom of the emitter is in electrical contact with the InGaAs contact layer, the collector is formed on the GaAs sub-collector layer and the bottom of the collector is in electrical contact with the GaAs sub-collector layer, the top of the collector is exposed by a film layer above the GaAs sub-collector layer, the base sequentially penetrates through the InGaP 1 st InGaP emitter layer to the InGaP m emitter layer from bottom to top, and the bottom of the base is in electrical contact with the GaAs base layer;
and etching and removing the mth InGaP emitter region layer in at least partial region between the emitter and the base.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
1. forming a1 st InGaP emitter region layer to an m-th InGaP emitter region layer of the first conductivity type on the GaAs base region layer of the second conductivity type, wherein each InGaP emitter region layer containsWith In y Ga 1-y P, y from the 1 st InGaP emitting region layer to the m th InGaP emitting region layer is reduced layer by layer, m is more than or equal to 3 and is an integer, therefore, the potential barrier at the InGaP/GaAs interface is gradually raised from low through y layer by layer reduction (namely In component with small jump), a gradual band gap difference is formed between the 1 st InGaP emitting region layer to the m th InGaP emitting region layer and the material of the P GaAs base region layer on the whole, further, the potential barrier peak at the InGaP/GaAs heterojunction is effectively reduced, the starting voltage Vbe is prevented from being increased when the HBT works, and the device performance is improved.
2. Because the band gap of InGaP is related to the In and Ga arrangement order, when the growth temperature of the InGaP emitting region layer is controlled to be different, the InGaP emitting region layers of all layers can be changed from disorder to more order, the band gap is reduced, the starting voltage Vbe is further prevented from being increased when the HBT works, and the performance of the device is improved.
3. The mth InGaP emission region layer is doped in a high n type, so that the emitter and the InGaP can form better ohmic contact, the starting voltage Vbe during the work of the HBT is further reduced, the mth InGaP emission region layer in at least part of the region between the base and the emitter is easily removed through etching, the electric leakage between the base and the emitter is avoided, and the performance of a device is guaranteed.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:
fig. 1 is a schematic cross-sectional view of a conventional Heterojunction Bipolar Transistor (HBT).
Figure 2 is a graphical representation of the In fraction as a function of thickness for the HBT shown In figure 1.
Fig. 3 is a schematic diagram of InGaP/GaAs heterojunction barrier curves in the HBT shown in fig. 1.
Figure 4 is a schematic cross-sectional view of a Heterojunction Bipolar Transistor (HBT) in accordance with an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional structure diagram of an example (i.e., m = 5) of the Heterojunction Bipolar Transistor (HBT) shown in fig. 4.
Figure 6 is a graphical representation of the variation of y with depth THK from top to bottom for the HBT shown in figure 5.
Figure 7 is a schematic cross-sectional view of the HBT after further formation of a base, emitter, and collector on top of the exemplary structure shown in figure 5.
Fig. 8 is a schematic diagram of InGaP/GaAs heterojunction barrier curves in the HBT shown in fig. 5.
Fig. 9 is a schematic cross-sectional structure diagram of another example (i.e., m = 3) of the Heterojunction Bipolar Transistor (HBT) shown in fig. 4.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention. It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout. It will be understood that when an element or layer is referred to as being "on 8230that the term" is used herein, it can be directly on the other element or layer or intervening elements or layers may be present. In contrast, when an element is said to be "directly over" … then there are no intervening elements or layers. Although the terms first, second, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. Spatial relationship terms such as "under 8230," "below 8230," "underlying," "at 8230," "over 8230," "overlying," "overlying," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "under" 8230; \8230; underlying "," underlying "or" lower "would then be oriented" on "the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising" are used in an inclusive sense to specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 4, an embodiment of the invention further provides a heterojunction bipolar transistor, taking the first conductivity type as n-type and the second conductivity type as p-type as an example, and including a GaAs substrate layer 100, an n GaAs sub-collector region layer 101, an n GaAs collector region layer 102, a p GaAs base region layer 103, an n-type 1 st InGaP emitter region layer to an m-th InGaP emitter region layer 1041-104 m, an n GaAs contact layer 105, and an n InGaAs contact layer 106 stacked in sequence from bottom to top.
The p GaAs base layer 103 is used to form the base region of the npn HBT transistor, and may be highly doped with C (carbon) or the like inside thereofp-type impurity, the doping concentration of the p-type impurity is, for example, 5e17 to 5e19/cm 3 To provide a high hole concentration and to reduce the resistance of the base region. The film thickness of the p GaAs base layer 103 can be small, for example, controlled to be less than 100nm (for example, within 50 nm), so that the recombination effect of electrons in the base region can be reduced, the transit time of electrons can be reduced, and the gain and the frequency of the device can be improved.
The n GaAs sub-collector layer 101 and the n GaAs collector layer 102 may use GaAs of the same material as the GaAs substrate layer 100, or may also use other semiconductors substantially free from lattice mismatch with the GaAs substrate layer 100, such as GaAs, alGaAs, or a stacked structure of these semiconductors. Wherein nGaAs subcollector layer 101 serves as a contact layer for the collector of an npn type HBT transistor, the doped n-type impurity of which may comprise Si or the like, and has a doping concentration of, for example, 5e15/cm 3 ～5e18/cm 3 . The high n-type doping is beneficial to realizing good ohmic contact and reducing series resistance. The n GaAs collector region layer 102 is used for forming a collector region of an npn HBT transistor, and is used for collecting electrons transmitted from the emitter region, and an electric field exists in the n GaAs collector region layer to accelerate the electrons; the capacitance is reduced.
The 1 st to m-th InGaP emitter layers 1041 to 104m constitute an emitter layer 104 of an npn-type HBT transistor as a whole, for forming an emitter of the npn-type HBT transistor, which emits electrons.
In this embodiment, each of the InGaP emitter layers 1041 to 104m contains In y Ga1- y P, from the 1 st InGaP emitter layer to the mth InGaP emitter layer 1041-104 m, decreases layer by layer, m is not less than 3 and is an integer. Specifically, in is In from the 1 st InGaP emitter layer to the m-th InGaP emitter layer 1041 to 104m y Ga1- y P stands for In y1 Ga1- y1 P、In y2 Ga1- y2 P、……、In ym Ga1- ym P, then 0.7. Gtoreq. Y1>>y2……>ym-1 is not less than 0.4 and 0<ym<0.4, alternatively, 0.7. Gtoreq.y 1>>y2……>ym-1 is not less than 0.45 and 0<ym<0.45。
Optionally, from the 1 st InGaP emitter layer to the m-1 st InGaP emitter layers 1041 to 104m-1, y of each InGaP emitter layer is constant respectively, i.e. y1 to ym-1 are different constant values respectively. Ym of the mth InGaP emitter layer 104m is gradually decreased with increasing thickness of the bottom-up film stack. The advantage of this is that the barrier at the interface of the InGaP emitter region layer 104 and the p GaAs base region layer 103 is gradually changed by the y value which is gradually decreased from bottom to top, and the barrier peak at the InGaP/GaAs heterojunction is effectively reduced.
It should be understood that the thickness of each emitter layer from the 1 st InGaP emitter layer to the mth InGaP emitter layers 1041 to 104m is also designed, and if the overall thickness of the InGaP emitter layer 104 is too thick, the formed base electrode 108 cannot effectively penetrate through the InGaP emitter layer 104 serving as a passivation layer after annealing, resulting in poor ohmic contact and increasing Vbe; if the InGaP emitter region layer 104 is too thin, the reverse breakdown voltage between emitter and base, bvbo, will be reduced, affecting the device performance. Thus, further optionally, the sum of the stack thicknesses X1+ X2+ \ 8230 \ 8230 @ -2, where Xm-2 is 1nm to 200nm, the film thickness Xm-1 of the (m-1) th InGaP emitter layer 104m-1 is 1nm to 100nm, and the film thickness Xm of the (m) th InGaP emitter layer 104m is not higher than 50nm, from the 1 st InGaP emitter layer to the (m-2) th InGaP emitter layers 1041 to 104 m-2.
Further, the n-type impurity of Si or the like of the m-th InGaP emitter region layer 104m may be highly doped, for example, with the doping concentration of the n-type impurity being 5e17/cm 3 ～5e19/cm 3 Thereby facilitating good ohmic contact to base 108 and reducing series resistance. The doping concentration of n-type impurities from the 1 st InGaP emitter region layer to at least one of the m-1 st InGaP emitter region layers 1041 to 104m-1 is 5e15/cm 3 ～5e18/cm 3 So as to control the lattice defects generated therein and ensure the performance of the device.
The n-type impurities in the n GaAs contact layer 105 may be highly doped, which is beneficial to achieving good ohmic contact of the emitter and reducing the series resistance.
The n InGaAs contact layer 106 serves as a contact layer of the emitter 109 on the surface, and n-type impurities of the n InGaAs contact layer can be highly doped, so that good ohmic contact is realized, the series resistance is reduced, and the surface recombination effect of electrons can be reduced.
Optionally, a ratio V/III between a composition ratio of a group V element (P) In at least one InGaP emitter layer from the 1 st InGaP emitter layer 1041 to the m-th InGaP emitter layer 104m and a sum of composition ratios of group III elements (In + Ga) is 0.5 to 100.
Referring to fig. 5, taking m =5 as an example, the npn HBT transistor includes a GaAs substrate layer 100, an n GaAs sub-collector layer 101, an n GaAs collector layer 102, a p GaAs base layer 103, an n type 1 st InGaP emitter layer 1041, an n type 2 nd InGaP emitter layer 1042, an n type 3 rd InGaP emitter layer 1043, an n type 4 th InGaP emitter layer 1044, an n type 5 th InGaP emitter layer 1045, an n GaAs contact layer 105, and an n InGaAs contact layer 106, which are sequentially stacked from bottom to top.
Wherein the 1 st InGaP emitter region layer 1041 has a thickness of X1 and contains In y1 Ga1- y1 P, the InGaP emitter region layer 1042 of the 2 nd layer has a thickness of X2 and contains In y2 Ga1- y2 P, the 3 rd InGaP emitter region layer 1043 having a thickness of X3 and containing In y3 Ga1- y3 P, 4 th InGaP emitter region layer 1044 has a thickness of X4 and contains In y4 Ga1- y4 P, 5 th InGaP emitter layer 1045 thickness X5, and In y5 Ga1- y5 P。
Further, along the direction in which the film layer stacking depth THK from the top gradually deepens, the change curve of the y value from the n GaAs contact layer 105 into the pGaAs base layer 103 is as shown in fig. 6, THK1 represents the stacking depth from the top surface of the ngaas contact layer 106 to the bottom surface of the n GaAs contact layer 105, X5= THK2-THK1, X4= THK3-THK2, X3= THK4-THK3, X2= THK5-THK4, and X1= THK6-THK5. As can be seen from fig. 6, y1 in the InGaP 1 st emitter layer 1041 is a constant and does not vary with the top-down stacking depth THK or the bottom-up stacking height. Y2 in the 2 nd InGaP emitter layer 1042 is a constant less than y1 and also does not vary with the top-down stack depth THK or the bottom-up stack height. Y3 in the 3 rd InGaP emitter layer 1043 is a constant less than y2 and also does not vary with the top-down stack depth THK or the bottom-up stack height. Y4 in the 4 th InGaP emitter layer 1044 is a constant less than y3 and also does not vary with top-to-bottom stack depth THK or bottom-to-top stack height. Y5 in the 5 th InGaP emitter layer 1045 is a variable that decreases with a top-down stacking depth THK or with an increasing bottom-up stacking height.
Wherein X1+ X2+ X3=1 nm-200nm, 1nm and X4 are constructed as 100nm and 0 and X5 are constructed as 50nm.0.7 is more than or equal to y1, y2, y3, y4 is more than or equal to 0.4, and 0-y5-straw 0.4.
That is, in the direction from the 5 th InGaP emitter region layer 1045 to the 1 st InGaP emitter region layer 1041, the value of y is increased layer by layer, and the larger the value of y, the smaller the band gap, whereby the barrier of the heterojunction formed by the InGaP emitter region layer 104 as a whole with the p GaAs base region layer 103 can be made gradual. Comparing fig. 3 and fig. 8, it can be found that the technical solution of this embodiment can reduce the potential barrier peak at the heterojunction formed by the InGaP emitter region layer 104 and the p GaAs base region layer 103 as a whole, avoid the high Vbe of the start voltage when the HBT operates, and improve the device performance.
Referring to fig. 7, further, in order to extract or connect electrical signals such as voltage to the base region, the emitter region, and the collector region of the heterojunction bipolar transistor, the heterojunction bipolar transistor further includes a collector 107, a base 108, and an emitter 109. The emitter 109 is formed on the top surface of the n InGaAs contact layer 106, and the bottom of the emitter is in electrical contact (e.g., ohmic contact) with the top surface of the n InGaAs contact layer 106. A collector 107 is formed on the top surface of the n GaAs sub-collector layer 101, the bottom of the collector 107 is in electrical contact (e.g., ohmic contact) with the top surface of the n GaAs sub-collector layer 101, and the top of the collector 107 is exposed by the film layer above the n GaAs sub-collector layer 101 (i.e., from the n GaAs collector layer 102 to the ngaas contact layer 109). The base 108 sequentially penetrates from the 1 st InGaP emitter layer 1041 to the mth InGaP emitter layer 104m from bottom to top, and the bottom of the base 108 is electrically contacted (for example, ohmic contact) with the p GaAs base layer 103. The top of the base 108 is exposed by the n InGaAs contact layer 106 and the n GaAs contact layer 105.
It should be understood that the above example illustrates the structure of the heterojunction bipolar transistor of the present invention by taking m =5 as an example, but the technical solution of the present invention is not limited thereto, and in other examples of the present invention, m may also be equal to 3, as shown in fig. 9, where y1 and y2 are different constant constants, y3 is a variable that gradually increases with increasing stacking depth from top to bottom, and 0.7 ≧ y1> y2 ≧ 0.4,0< y3<0.4. In other examples of the present invention, m may also be 4 or any suitable integer greater than 5, and the larger m, the smoother the barrier transition of the heterojunction formed by the InGaP emitter region layer 104 and the GaAs base region layer 103, and the better the barrier spike improvement effect.
Based on the same inventive concept, referring to fig. 4 to 7, an embodiment of the invention further provides a method for manufacturing a heterojunction bipolar transistor, which can manufacture the heterojunction bipolar transistor of the invention. The manufacturing method comprises the following steps:
s1, providing a GaAs substrate layer 00;
s2, forming a GaAs collector region layer 102 of a first conduction type on the GaAs substrate layer 100;
s3, forming a GaAs base region layer 103 of a second conduction type on the GaAs collector region layer 102;
s4, sequentially laminating a1 st InGaP emission region layer to an m & ltth & gt InGaP emission region layer 1041-104 m of a first conduction type on the GaAs base region layer 103, wherein each InGaP emission region layer contains InGa 1-yP, y from the 1 st InGaP emission region layer to the m & ltth & gt InGaP emission region layer is reduced layer by layer, m is not less than 3 and is an integer, namely y1 is more than y2 and more than y3 is 8230, y 8230, ym;
s5, the InGaAs contact layer 106 of the first conductivity type is formed on the mth InGaP emitter region layer 104 m.
In step S2, the 1 st InGaP emitter layer to the m-th InGaP emitter layer 1041-104 m are sequentially grown, and the process parameters for growing each InGaP emitter layer include: the growth temperature is 400-800 ℃, the growth pressure is 50-200 mbar, and the element content ratio V/III is 0.5-100.
Because the band gap of the InGaP material is related to the In and Ga arrangement order, the band gap is reduced when the InGaP material is changed from disorder to more order, and the growth temperature can change the order of the InGaP material, in step S3, when the 1 st InGaP emitting region layer to the m th InGaP emitting region layer 1041-104 m are grown In sequence, the band gap of each InGaP emitting region layer can be controlled to gradually change by controlling the growth temperature.
As an example, in step S3, when the InGaP emitter layers 1 to m are sequentially grown, the growth temperatures may be controlled to decrease layer by layer, that is, when the growth temperatures of the InGaP emitter layers 1 to m 1041 to 104m are T1, T2, 8230, and when Tm, T1> T2> T3> \8230, tm is satisfied.
As an example, in step S3, when the InGaP emitter region layer 1 to the InGaP emitter region layer m 1041 to 104m are grown sequentially, the growth temperature from the InGaP emitter region layer 1 to the InGaP emitter region layer m-2 may be controlled to decrease sequentially, so as to satisfy T1> T2> T3 \ > 823030tm-2, the growth temperature from the InGaP emitter region layer m-2 to the InGaP emitter region layer m 104m may decrease layer by layer or at least the growth temperature of two adjacent InGaP emitter region layers may be the same. For example, when m =5, when the growth temperatures of the InGaP emitter layer 1 to the InGaP emitter layer 5 are T1, T2, T3, and T5 in this order, T1> T2> T3 ≧ T4 ≧ T5 are satisfied.
Optionally, the forming process conditions of at least one InGaP emitter region layer from the 1 st InGaP emitter region layer to the mth InGaP emitter region layer include: the growth temperature is 400-800 ℃, the growth pressure is 50-200mbar, and the ratio of the content of the V group elements to the total content of the III group elements is 0.5-100.
Optionally, the manufacturing method of this embodiment further includes:
after step S1 and before step S2, that is, before forming the GaAs collector region layer 102 of the first conductivity type on the GaAs substrate layer 100, forming a GaAs sub-collector region layer 101 of the first conductivity type on the GaAs substrate layer 100;
and after step S4 and before step S5, i.e., before forming the InGaAs contact layer 106 on the mth InGaP emitter region layer 104m, forming a GaAs contact layer 105 of the first conductivity type on the mth InGaP emitter region layer 104 m.
Further, the manufacturing method of the present embodiment, after step S5, further includes:
firstly, forming an emitter 109, a collector 107 and a base 108, wherein the emitter 109 is formed on the InGaAs contact layer 106 and the bottom of the emitter 109 is in electrical contact with the InGaAs contact layer 106, the collector 107 is formed on the GaAs sub-collector region 101 and the bottom of the collector is in electrical contact with the GaAs sub-collector region 101, the top of the collector 107 is exposed by a film layer above the GaAs sub-collector region 101, the base 108 sequentially penetrates through the InGaP 1 st InGaP emitter region layer 1041 to the InGaP m emitter region layer 104m from bottom to top, and the bottom of the base 108 is in electrical contact with the GaAs base region layer 103;
then, the mth InGaP emitter region layer 104m in at least a partial region between the emitter 109 and the base 108 is etched away to prevent leakage between both electrodes of the emitter 109 and the base 108.
In summary, in the technical solution of the present invention, the InGaP emitter region layer of the bulk block in the prior art is replaced by the 1 st InGaP emitter region layer to the m th InGaP emitter region layer, which are y decreased layer by layer, so that a gradual band gap difference is formed between the whole 1 st to m InGaP emitter region layers and the material of the P GaAs base region layer, thereby effectively reducing the barrier peak at the InGaP/GaAs heterojunction, and lowering the turn-on voltage Vbe when the HBT operates. And further, the growth temperature of each InGaP emission region layer is controlled, so that each InGaP emission region layer is changed from disorder to more order, the band gap is reduced, and the turn-on voltage Vbe during the HBT operation is further reduced.
The above description is only for describing the preferred embodiment of the present invention, and it is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the protection scope of the present invention.

Claims (13)

1. A heterojunction bipolar transistor, comprising, stacked in order from bottom to top:
a GaAs substrate layer;
a first conductivity type GaAs collector layer;
a GaAs base region layer of a second conductivity type;
from the 1 st InGaP emitter region layer to the m-th InGaP emitter region layer of the first conductivity type, each of the InGaP emitter region layers containing In y Ga 1-y P, and y from the 1 st InGaP emitting area layer to the mth InGaP emitting area layer is reduced layer by layer, m is not less than 3 and is an integer;
and an InGaAs contact layer of the first conductivity type.
2. The heterojunction bipolar transistor of claim 1 wherein each of said InGaP emitter layers from the 1 st InGaP emitter layer to the m-1 st InGaP emitter layer has 0.4 < y < 0.7, and the m-th InGaP emitter layer has 0< -y < -0.4; or, y is more than or equal to 0.45 and less than or equal to 0.7 in each InGaP emission area layer from the 1 st InGaP emission area layer to the m-1 st InGaP emission area layer, and the m-th InGaP emission area layer is provided with 0-y-0.45.
3. The heterojunction bipolar transistor of claim 1 wherein y is constant for each InGaP emitter layer from the 1 st InGaP emitter layer to the m-1 st InGaP emitter layer; the y of the m-th InGaP emitter region layer gradually decreases with increasing stack thickness.
4. The heterojunction bipolar transistor of claim 1, wherein the sum of the thicknesses of the stacks from the 1 st InGaP emitter layer to the m-2 nd InGaP emitter layer is 1nm to 200nm, the film thickness of the m-1 st InGaP emitter layer is 1nm to 100nm, and the film thickness of the m-th InGaP emitter layer is not higher than 50nm.
5. The heterojunction bipolar transistor of claim 1, wherein said impurity of the first conductivity type in said mth InGaP emitter layer has a doping concentration of 5e17/cm 3 ～5e19/cm 3 (ii) a And/or the doping concentration of the impurity of the first conductivity type in at least one InGaP emitter region layer from the 1 st InGaP emitter region layer to the m-1 st InGaP emitter region layer is 5e15/cm 3 ～5e18/cm 3 。
6. The heterojunction bipolar transistor of claim 1, wherein the ratio of the content of the group V element to the total content of the group III elements in at least one InGaP emitter layer from the 1 st InGaP emitter layer to the m-th InGaP emitter layer is 0.5 to 100.
7. A heterojunction bipolar transistor according to any of claims 1 to 6, further comprising: the GaAs sub-collector region layer of the first conduction type is positioned between the GaAs substrate layer and the GaAs collector region layer; and/or a GaAs contact layer of the first conduction type positioned between the InGaAs contact layer and the m-th InGaP emitter region layer.
8. The heterojunction bipolar transistor of claim 7, further comprising:
an emitter formed on the InGaAs contact layer and having a bottom electrically contacting the InGaAs contact layer;
a collector formed on the GaAs subcollector layer, wherein the bottom of the collector is electrically contacted with the GaAs subcollector layer, and the top of the collector is exposed by the film layer above the GaAs subcollector layer;
and the base sequentially penetrates through the 1 st InGaP emitter region layer to the mth InGaP emitter region layer from bottom to top, and the bottom of the base is electrically contacted with the GaAs base region layer.
9. A method of fabricating a heterojunction bipolar transistor, comprising:
providing a GaAs substrate layer;
forming a GaAs collector region layer of a first conduction type on the GaAs substrate layer;
forming a GaAs base region layer of a second conduction type on the GaAs collector region layer;
sequentially laminating a1 st InGaP emission region layer to an m-th InGaP emission region layer of a first conduction type on the GaAs base region layer, wherein each InGaP emission region layer contains In y Ga 1-y P, and from the 1 st InGaP emitter layerDecreasing the y layer by layer of the InGaP emitting area layer of the mth layer, wherein m is not less than 3 and is an integer;
an InGaAs contact layer of the first conductivity type is formed on the mth InGaP emitter region layer.
10. The manufacturing method of claim 9, wherein the growth temperatures of the InGaP emitter region layer from the 1 st layer to the m-2 th layer are decreased layer by layer, the growth temperatures of the InGaP emitter region layer from the m-2 th layer to the m-2 th layer are decreased layer by layer or the growth temperatures of at least two adjacent layers are the same.
11. The manufacturing method of claim 9, wherein the process conditions for forming at least one InGaP emitter layer from the 1 st InGaP emitter layer to the mth InGaP emitter layer comprise: the growth temperature is 400-800 ℃, the growth pressure is 50-200mbar, the ratio of the content of the V group element to the content sum of the III group element is 0.5-100.
12. The method of manufacturing of claim 9, further comprising:
forming a GaAs sub-collector region layer of a first conduction type on the GaAs substrate layer before forming the GaAs collector region layer of the first conduction type on the GaAs substrate layer;
and before the InGaAs contact layer is formed on the mth InGaP emitter region layer, a GaAs contact layer of the first conduction type is formed on the mth InGaP emitter region layer.
13. The method of manufacturing of claim 9, further comprising:
forming an emitter, a collector and a base, wherein the emitter is formed on the InGaAs contact layer, the bottom of the emitter is in electrical contact with the InGaAs contact layer, the collector is formed on the GaAs sub-collector region layer, the bottom of the collector is in electrical contact with the GaAs sub-collector region layer, the top of the collector is exposed by a film layer above the GaAs sub-collector region layer, the base sequentially penetrates through the 1 st InGaP emitter region layer to the m < th > InGaP emitter region layer from bottom to top, and the bottom of the base is in electrical contact with the GaAs base region layer;
and etching to remove the mth InGaP emitter region layer in at least partial region between the emitter and the base.
CN202211393727.1A 2022-11-08 2022-11-08 Heterojunction bipolar transistor and manufacturing method thereof Pending CN115566057A (en)

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