CA2223199C - Montage a couplage par les grilles permettant d'ameliorer la protection contre les perturbations electrostatiques a l'entree et a la sortie de circuits integres cmos - Google Patents
Montage a couplage par les grilles permettant d'ameliorer la protection contre les perturbations electrostatiques a l'entree et a la sortie de circuits integres cmos Download PDFInfo
- Publication number
- CA2223199C CA2223199C CA002223199A CA2223199A CA2223199C CA 2223199 C CA2223199 C CA 2223199C CA 002223199 A CA002223199 A CA 002223199A CA 2223199 A CA2223199 A CA 2223199A CA 2223199 C CA2223199 C CA 2223199C
- Authority
- CA
- Canada
- Prior art keywords
- fet
- source
- gate
- drain
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/866,120 US5910874A (en) | 1997-05-30 | 1997-05-30 | Gate-coupled structure for enhanced ESD input/output pad protection in CMOS ICs |
US08/866,120 | 1997-05-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2223199A1 CA2223199A1 (fr) | 1998-11-30 |
CA2223199C true CA2223199C (fr) | 2001-10-09 |
Family
ID=25346952
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002223199A Expired - Fee Related CA2223199C (fr) | 1997-05-30 | 1997-12-01 | Montage a couplage par les grilles permettant d'ameliorer la protection contre les perturbations electrostatiques a l'entree et a la sortie de circuits integres cmos |
Country Status (2)
Country | Link |
---|---|
US (2) | US5910874A (fr) |
CA (1) | CA2223199C (fr) |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5910874A (en) * | 1997-05-30 | 1999-06-08 | Pmc-Sierra Ltd. | Gate-coupled structure for enhanced ESD input/output pad protection in CMOS ICs |
JP3270364B2 (ja) * | 1997-07-28 | 2002-04-02 | エヌイーシーマイクロシステム株式会社 | 静電保護回路 |
JP3993927B2 (ja) * | 1997-12-22 | 2007-10-17 | 沖電気工業株式会社 | 静電破壊保護回路 |
US6091594A (en) * | 1998-02-18 | 2000-07-18 | Vlsi Technology, Inc. | Protection circuits and methods of protecting a semiconductor device |
TW373317B (en) * | 1998-03-25 | 1999-11-01 | United Microelectronics Corporaiton | Gate voltage control electrostatic discharge protection circuit |
KR100295053B1 (ko) | 1998-09-03 | 2001-07-12 | 윤종용 | 부하적응형저잡음출력버퍼 |
US6242942B1 (en) | 1998-11-13 | 2001-06-05 | Integrated Device Technology, Inc. | Integrated circuit output buffers having feedback switches therein for reducing simultaneous switching noise and improving impedance matching characteristics |
US6356102B1 (en) | 1998-11-13 | 2002-03-12 | Integrated Device Technology, Inc. | Integrated circuit output buffers having control circuits therein that utilize output signal feedback to control pull-up and pull-down time intervals |
US6091260A (en) * | 1998-11-13 | 2000-07-18 | Integrated Device Technology, Inc. | Integrated circuit output buffers having low propagation delay and improved noise characteristics |
TW471152B (en) * | 2000-03-10 | 2002-01-01 | United Microelectronics Corp | Electrostatic discharge protection circuit of integrated circuit |
US6437407B1 (en) | 2000-11-07 | 2002-08-20 | Industrial Technology Research Institute | Charged device model electrostatic discharge protection for integrated circuits |
US6617649B2 (en) | 2000-12-28 | 2003-09-09 | Industrial Technology Research Institute | Low substrate-noise electrostatic discharge protection circuits with bi-directional silicon diodes |
US7205641B2 (en) * | 2000-12-28 | 2007-04-17 | Industrial Technology Research Institute | Polydiode structure for photo diode |
US6690065B2 (en) * | 2000-12-28 | 2004-02-10 | Industrial Technology Research Institute | Substrate-biased silicon diode for electrostatic discharge protection and fabrication method |
TW486804B (en) | 2001-04-24 | 2002-05-11 | United Microelectronics Corp | Double-triggered electrostatic discharge protection circuit |
US6633068B2 (en) | 2001-05-10 | 2003-10-14 | Industrial Technology Research Institute | Low-noise silicon controlled rectifier for electrostatic discharge protection |
DE10128740B4 (de) * | 2001-06-13 | 2006-07-06 | Infineon Technologies Ag | Aktive Überspannungsschutzschaltung |
US6747501B2 (en) | 2001-07-13 | 2004-06-08 | Industrial Technology Research Institute | Dual-triggered electrostatic discharge protection circuit |
US6750515B2 (en) | 2002-02-05 | 2004-06-15 | Industrial Technology Research Institute | SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection |
US6576974B1 (en) | 2002-03-12 | 2003-06-10 | Industrial Technology Research Institute | Bipolar junction transistors for on-chip electrostatic discharge protection and methods thereof |
US6734504B1 (en) | 2002-04-05 | 2004-05-11 | Cypress Semiconductor Corp. | Method of providing HBM protection with a decoupled HBM structure |
US6838707B2 (en) | 2002-05-06 | 2005-01-04 | Industrial Technology Research Institute | Bi-directional silicon controlled rectifier for electrostatic discharge protection |
US6762918B2 (en) * | 2002-05-20 | 2004-07-13 | International Business Machines Corporation | Fault free fuse network |
TW560038B (en) * | 2002-05-29 | 2003-11-01 | Ind Tech Res Inst | Electrostatic discharge protection circuit using whole chip trigger technique |
TWI225501B (en) * | 2002-11-06 | 2004-12-21 | Delta Optoelectronics Inc | Packaging material used for a display device and method of forming thereof |
US20040105202A1 (en) * | 2002-12-03 | 2004-06-03 | Industrial Technology Research Institute | Electrostatic discharge protection device and method using depletion switch |
US7304827B2 (en) * | 2003-05-02 | 2007-12-04 | Zi-Ping Chen | ESD protection circuits for mixed-voltage buffers |
US7253453B2 (en) * | 2003-05-21 | 2007-08-07 | Industrial Technology Research Institute | Charge-device model electrostatic discharge protection using active device for CMOS circuits |
US7244992B2 (en) | 2003-07-17 | 2007-07-17 | Ming-Dou Ker | Turn-on-efficient bipolar structures with deep N-well for on-chip ESD protection |
US20050237682A1 (en) * | 2004-04-26 | 2005-10-27 | Taiwan Semiconductor Manufacturing Co. | Novel ESD protection scheme for core devices |
TWI273634B (en) | 2004-12-21 | 2007-02-11 | Transpacific Ip Ltd | Novel poly diode structure for photo diode |
CN100426618C (zh) * | 2004-12-29 | 2008-10-15 | 鸿富锦精密工业(深圳)有限公司 | 静电放电防护电路 |
TWI264248B (en) * | 2005-03-25 | 2006-10-11 | Avision Inc | A method of electrostatic discharge prevention for a systematic circuit |
KR100741925B1 (ko) * | 2005-12-30 | 2007-07-23 | 동부일렉트로닉스 주식회사 | 구동 용량의 미세 조절이 가능한 입출력 셀 |
TWI329965B (en) * | 2006-06-20 | 2010-09-01 | Via Tech Inc | Voltage pull-up device |
GB2464538A (en) | 2008-10-17 | 2010-04-28 | Cambridge Silicon Radio Ltd | An ESD protection circuit for a transmitter output |
JP2012203528A (ja) * | 2011-03-24 | 2012-10-22 | Seiko Instruments Inc | ボルテージ・レギュレータ |
US10191108B2 (en) * | 2015-11-19 | 2019-01-29 | Globalfoundries Inc. | On-chip sensor for monitoring active circuits on integrated circuit (IC) chips |
US10574066B2 (en) * | 2017-12-04 | 2020-02-25 | Bell Helicopter Textron Inc. | Integrated capacitive discharge electrical bonding assurance system |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5400202A (en) * | 1992-06-15 | 1995-03-21 | Hewlett-Packard Company | Electrostatic discharge protection circuit for integrated circuits |
US5910874A (en) * | 1997-05-30 | 1999-06-08 | Pmc-Sierra Ltd. | Gate-coupled structure for enhanced ESD input/output pad protection in CMOS ICs |
-
1997
- 1997-05-30 US US08/866,120 patent/US5910874A/en not_active Expired - Lifetime
- 1997-12-01 CA CA002223199A patent/CA2223199C/fr not_active Expired - Fee Related
-
1999
- 1999-01-25 US US09/236,100 patent/US6128171A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5910874A (en) | 1999-06-08 |
CA2223199A1 (fr) | 1998-11-30 |
US6128171A (en) | 2000-10-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |
Effective date: 20131203 |