CA2149076C - Integrated user network interface device - Google Patents
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- CA2149076C CA2149076C CA002149076A CA2149076A CA2149076C CA 2149076 C CA2149076 C CA 2149076C CA 002149076 A CA002149076 A CA 002149076A CA 2149076 A CA2149076 A CA 2149076A CA 2149076 C CA2149076 C CA 2149076C
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
Abstract
A user network interface device for interfacing between synchronous optical network (SONET)/synchronous digital hierarchy (SDH) which is , characterized by a continuous stream of frames of data and an asynchronous transfer mode (ATM) characterized by a non-continuous stream of cells of data. The user network interface device includes an integral phase lock loop circuit to recover clock and data from an encoded incoming stream of data. In another embodiment, the network interface device synthesizes a high speed transmit clock from a low frequency reference source.
Claims (38)
1. A user network interface (UNI) device for interfacing between a synchronous optical network (SONET) and an asynchronous transfer mode (ATM) network, the user network interface device comprising:
(a) a transmit section operative to receive an incoming non-continuous stream of data cells from the ATM
network, generate and insert idle cells into the incoming non-continuous stream of data cells to form a continuous stream of cells, map the continuous stream of cells into frames of data, and synchronously transmit the frames of data in an outgoing continuous stream of data, wherein the transmit section includes an integral clock synthesis circuit operative to synthesize a high speed transmit clock from a low frequency reference source; and (b) a receive section operative to receive incoming frames of data in an incoming continuous stream of data, extract ATM cells from the incoming frames of data, and transmit the extracted ATM cells in an outgoing non-continuous stream of data cells, wherein the receive section includes an integral clock recovery circuit operative to sample and recover clock from the incoming continuous stream of data.
(a) a transmit section operative to receive an incoming non-continuous stream of data cells from the ATM
network, generate and insert idle cells into the incoming non-continuous stream of data cells to form a continuous stream of cells, map the continuous stream of cells into frames of data, and synchronously transmit the frames of data in an outgoing continuous stream of data, wherein the transmit section includes an integral clock synthesis circuit operative to synthesize a high speed transmit clock from a low frequency reference source; and (b) a receive section operative to receive incoming frames of data in an incoming continuous stream of data, extract ATM cells from the incoming frames of data, and transmit the extracted ATM cells in an outgoing non-continuous stream of data cells, wherein the receive section includes an integral clock recovery circuit operative to sample and recover clock from the incoming continuous stream of data.
2. A device according to claim 1, wherein the integral clock recovery circuit includes:
(aa) a first voltage control oscillator (VCO), having an input and a divided down output, operative to lock on to the incoming continuous stream of data;
(bb) a phase/frequency detector operative to compare a first reference clock signal and a divided down output signal from the first VCO and to drive the first VCO to lock on to the first reference clock signal; and (cc) a data phase detector operative to compare a phase of the incoming continuous stream of data and the divided down output signal from the first VCO and to drive the first VCO towards a lock condition with the incoming continuous stream of data; and wherein the first VCO is switched from the phase/frequency detector to the data phase detector when a frequency difference between a frequency of the divided down output signal from the first VCO and that of the first reference clock signal is less than or equal to a predetermined threshold, and the first VCO is switched back to the phase/frequency detector when the frequency difference exceeds the predetermined threshold.
(aa) a first voltage control oscillator (VCO), having an input and a divided down output, operative to lock on to the incoming continuous stream of data;
(bb) a phase/frequency detector operative to compare a first reference clock signal and a divided down output signal from the first VCO and to drive the first VCO to lock on to the first reference clock signal; and (cc) a data phase detector operative to compare a phase of the incoming continuous stream of data and the divided down output signal from the first VCO and to drive the first VCO towards a lock condition with the incoming continuous stream of data; and wherein the first VCO is switched from the phase/frequency detector to the data phase detector when a frequency difference between a frequency of the divided down output signal from the first VCO and that of the first reference clock signal is less than or equal to a predetermined threshold, and the first VCO is switched back to the phase/frequency detector when the frequency difference exceeds the predetermined threshold.
3. A device according to claim 2, wherein said user network interface includes means for monitoring a transition density of the incoming continuous stream of data, wherein clock is recovered from the incoming continuous stream of data only if the incoming continuous stream of data has a number of transitions greater than or equal to a preset value for an n-bit interval.
4. A method according to claim 3, wherein the preset value is 1 and the n-bit interval is an 80-bit interval.
5. A device according to claim 1, wherein the integral clock recovery circuit includes:
(aa) a first reference clock input line for receiving a first reference clock signal and a data input line for receiving the incoming continuous stream of data;
(bb) a first voltage control oscillator (VCO), having an input and output, operative to lock on to the incoming continuous stream of data;
(cc) a first divider circuit operative to divide down output signals from the first VCO;
(dd) a phase/frequency detector operative to compare the phase and frequency of the first reference clock signal and the divided down output signal from the first divider circuit;
(ee) a data phase detector operative to compare the phase of the incoming continuous stream of data and the divided down output signal from the first divider circuit;
and (ff) driving and controlling means for driving and controlling the first VCO from one of the data phase detector and the phase/frequency detector; and wherein said driving and controlling means drives the first VCO from the phase/frequency detector when a frequency difference between the frequency of the divided down output signal from the first divider circuit and that of the external reference clock signal exceeds a predetermined threshold, and drives the first VCO from the data phase detector when the frequency difference is less than or equal to the predetermined threshold.
(aa) a first reference clock input line for receiving a first reference clock signal and a data input line for receiving the incoming continuous stream of data;
(bb) a first voltage control oscillator (VCO), having an input and output, operative to lock on to the incoming continuous stream of data;
(cc) a first divider circuit operative to divide down output signals from the first VCO;
(dd) a phase/frequency detector operative to compare the phase and frequency of the first reference clock signal and the divided down output signal from the first divider circuit;
(ee) a data phase detector operative to compare the phase of the incoming continuous stream of data and the divided down output signal from the first divider circuit;
and (ff) driving and controlling means for driving and controlling the first VCO from one of the data phase detector and the phase/frequency detector; and wherein said driving and controlling means drives the first VCO from the phase/frequency detector when a frequency difference between the frequency of the divided down output signal from the first divider circuit and that of the external reference clock signal exceeds a predetermined threshold, and drives the first VCO from the data phase detector when the frequency difference is less than or equal to the predetermined threshold.
6. A device according to claim 5, wherein said user network interface includes means for monitoring a transition density of the incoming continuous stream of data, wherein clock is recovered from the incoming continuous stream of data only if the incoming continuous stream of data has a number of transitions greater than or equal to a preset value for an n-bit interval.
7. A device according to claim 6, wherein the preset value is 1 and the n-bit interval is an 80-bit interval.
8. A device according to claim 5, wherein the predetermined threshold is 244 parts per million (ppm).
9. A device according to claim 5, wherein the driving and controlling means for driving and controlling the first VCO includes:
a loop control multiplexer operative to selectively drive and control the first VCO from one of the phase/frequency detector and the data phase detector, having an output coupled to the first VCO and an input coupled to an output of each of the phase/frequency detector and the data phase detector.
a loop control multiplexer operative to selectively drive and control the first VCO from one of the phase/frequency detector and the data phase detector, having an output coupled to the first VCO and an input coupled to an output of each of the phase/frequency detector and the data phase detector.
10. A device according to claim 9, wherein the clock recovery circuit includes a loop filter operative to cut out high frequency components of input signals and to control input of the first VCO, the loop filter having an output coupled to the input of the first VCO, and an input coupled to an output of the loop control multiplexer.
11. A device according to claim 6, wherein the external reference clock signal is 19.44 MHz or 6.48 MHz.
12. A device according to claim 6, wherein the first divider circuit includes a divide-by-three circuit coupled to a divide-by-eight circuit.
13. A device according to claim 6, wherein the transmit section includes an integral clock synthesis circuit operative to synthesize a high speed transmit clock from a low frequency reference source.
14. A user network interface (UNI) device for interfacing between a synchronous optical network (SONET) and an asynchronous transfer mode (ATM) network, the user network interface device comprising:
(a) a transmit section operative to receive an incoming non-continuous stream of data cells from the ATM
network, generate and insert idle cells into the incoming non-continuous stream of data cells to form a continuous stream of cells, map the continuous stream of cells into frames of data, and synchronously transmit the frames of data in an outgoing continuous stream of data, the transmit section including:
(i) an integral clock synthesis circuit operative to synthesize a high speed transmit clock from a low frequency reference source; and (b) a receive section operative to receive incoming frames of data in an incoming continuous stream of data, extract ATM cells from the incoming frames of data, and transmit the extracted ATM cells in an outgoing non-continuous stream of data cells.
(a) a transmit section operative to receive an incoming non-continuous stream of data cells from the ATM
network, generate and insert idle cells into the incoming non-continuous stream of data cells to form a continuous stream of cells, map the continuous stream of cells into frames of data, and synchronously transmit the frames of data in an outgoing continuous stream of data, the transmit section including:
(i) an integral clock synthesis circuit operative to synthesize a high speed transmit clock from a low frequency reference source; and (b) a receive section operative to receive incoming frames of data in an incoming continuous stream of data, extract ATM cells from the incoming frames of data, and transmit the extracted ATM cells in an outgoing non-continuous stream of data cells.
15. A device according to claim 14, wherein the integral clock synthesis circuit includes:
(aa) a voltage control oscillator (VCO);
(bb) a divider circuit having an input coupled to an output of the VCO;
(cc) a loop filter having an output coupled to an input of the VCO;
(dd) a charge pump coupled to the loop filter and operative to send source currents and sink currents into the loop filter to control the VCO;
(ee) a reference clock line for receiving a reference clock signal; and (ff) a dual phase/frequency detector operative to drive the charge pump, having an input coupled to an output of the divider circuit and the reference clock line.
(aa) a voltage control oscillator (VCO);
(bb) a divider circuit having an input coupled to an output of the VCO;
(cc) a loop filter having an output coupled to an input of the VCO;
(dd) a charge pump coupled to the loop filter and operative to send source currents and sink currents into the loop filter to control the VCO;
(ee) a reference clock line for receiving a reference clock signal; and (ff) a dual phase/frequency detector operative to drive the charge pump, having an input coupled to an output of the divider circuit and the reference clock line.
16. A device according to claim 15, wherein the loop filter has a transfer function optimized to enable the integral clock synthesis circuit to track the reference clock signal and attenuate high frequency jitter on the reference clock signal.
17. A device according to claim 16, wherein the transfer function yields a low pass corner frequency of 736 KHz when referenced to a 19.44 MHz crystal.
18. A device according to claim 16, wherein the transfer function yields a low pass corner frequency of 245 KHz when referenced to a 6.48 MHz crystal.
19. A user network interface (UNI) device for interfacing between a synchronous optical network (SONET) and an asynchronous transfer mode (ATM) network, the user network interface device comprising:
(a) a transmit section operative to receive an incoming non-continuous stream of data cells from the ATM
network, generate and insert idle cells into the incoming non-continuous stream of data cells to form a continuous stream of cells, map the continuous stream of cells into frames of data, and synchronously transmit the frames of data in an outgoing continuous stream of data, the transmit section including:
(i) an integral clock synthesis circuit operative to synthesize a high speed transmit clock from a low frequency reference source; and (b) a receive section operative to receive incoming frames of data in an incoming continuous stream of data, extract ATM cells from the incoming frames of data, and transmit the extracted ATM cells in an outgoing non-continuous stream of data cells, the receive section having an integral clock recovery circuit operative to sample and recover clock from an incoming encoded stream of data, the integral clock recovery circuit including:
(i) a first reference clock input line for receiving a first reference clock signal and a data input line for receiving the incoming continuous stream of data;
(ii) a first voltage control oscillator (VCO) operative to lock on to the incoming continuous stream of data;
(iii) a first divider circuit operative to divide down output signals from the first VCO, and having an input coupled to an output of the first VCO;
(iv) a first loop filter operative to cut out high frequency components of input signals and to control input of the first VCO, having an output coupled to an input of the first VCO;
(v) a phase/frequency detector, operative to compare phase and frequency of the first reference clock signal and a divided down first VCO output from the first divider circuit, having an input coupled to an output of the first divider circuit and the first reference clock input line;
(vi) a data phase detector operative to compare phase of the incoming continuous stream of data and the divided down first VCO output signal, having an input coupled to the data input line and to the first divider circuit;
(vii) a loop control multiplexer operative to selectively drive the loop filter and control the first VCO from one of the phase/frequency detector and the data phase detector, having an output coupled to an input of the loop filter and an input coupled to an output of the phase/frequency detector and the data phase detector;
(viii) a transition detector operative to monitor a transition density of the incoming continuous stream of data;
(ix) a clock difference detector, operative to compare a frequency of the first reference clock signal and the divided down output signal of the first VCO, having an input coupled to the first reference clock input line and the first divider circuit; and (x) a control state machine operative to control the control loop multiplexer, having an input coupled to each of the clock difference detector, the transition detector and the first divider circuit, and an output coupled to the loop control multiplexer;
wherein the control state machine operates the control loop multiplexer to drive and control the first VCO
from the data phase detector when a frequency difference between the divided down output signal from the first VCO
and the first reference clock signal is less than or equal to a predetermined threshold and clock is recovered from the incoming continuous stream of data only if the incoming continuous stream of data has a number of transitions greater than or equal to a preset value for an n-bit interval and where otherwise the control state machine operates the control loop multiplexer to drive and control the first VCO from the phase/frequency detector.
(a) a transmit section operative to receive an incoming non-continuous stream of data cells from the ATM
network, generate and insert idle cells into the incoming non-continuous stream of data cells to form a continuous stream of cells, map the continuous stream of cells into frames of data, and synchronously transmit the frames of data in an outgoing continuous stream of data, the transmit section including:
(i) an integral clock synthesis circuit operative to synthesize a high speed transmit clock from a low frequency reference source; and (b) a receive section operative to receive incoming frames of data in an incoming continuous stream of data, extract ATM cells from the incoming frames of data, and transmit the extracted ATM cells in an outgoing non-continuous stream of data cells, the receive section having an integral clock recovery circuit operative to sample and recover clock from an incoming encoded stream of data, the integral clock recovery circuit including:
(i) a first reference clock input line for receiving a first reference clock signal and a data input line for receiving the incoming continuous stream of data;
(ii) a first voltage control oscillator (VCO) operative to lock on to the incoming continuous stream of data;
(iii) a first divider circuit operative to divide down output signals from the first VCO, and having an input coupled to an output of the first VCO;
(iv) a first loop filter operative to cut out high frequency components of input signals and to control input of the first VCO, having an output coupled to an input of the first VCO;
(v) a phase/frequency detector, operative to compare phase and frequency of the first reference clock signal and a divided down first VCO output from the first divider circuit, having an input coupled to an output of the first divider circuit and the first reference clock input line;
(vi) a data phase detector operative to compare phase of the incoming continuous stream of data and the divided down first VCO output signal, having an input coupled to the data input line and to the first divider circuit;
(vii) a loop control multiplexer operative to selectively drive the loop filter and control the first VCO from one of the phase/frequency detector and the data phase detector, having an output coupled to an input of the loop filter and an input coupled to an output of the phase/frequency detector and the data phase detector;
(viii) a transition detector operative to monitor a transition density of the incoming continuous stream of data;
(ix) a clock difference detector, operative to compare a frequency of the first reference clock signal and the divided down output signal of the first VCO, having an input coupled to the first reference clock input line and the first divider circuit; and (x) a control state machine operative to control the control loop multiplexer, having an input coupled to each of the clock difference detector, the transition detector and the first divider circuit, and an output coupled to the loop control multiplexer;
wherein the control state machine operates the control loop multiplexer to drive and control the first VCO
from the data phase detector when a frequency difference between the divided down output signal from the first VCO
and the first reference clock signal is less than or equal to a predetermined threshold and clock is recovered from the incoming continuous stream of data only if the incoming continuous stream of data has a number of transitions greater than or equal to a preset value for an n-bit interval and where otherwise the control state machine operates the control loop multiplexer to drive and control the first VCO from the phase/frequency detector.
20. A device according to claim 19, wherein the preset value is 1 and the n-bit interval is an 80-bit interval.
21. A device according to claim 19, wherein the first reference clock signal is 19.44 MHz or 6.48 MHz.
22. A device according to claim 19, wherein the predetermined threshold is 244 parts per million (ppm).
23. A device according to claim 19, wherein the integral clock synthesis circuit includes:
(aa) a second voltage control oscillator (VCO);
(bb) a second divider circuit having an input coupled to an output of the second VCO;
(cc) a second loop filter having an output coupled to an input of the second VCO;
(dd) a charge pump coupled to the second loop filter and operative to send source currents and sink currents into the second loop filter to control the second VCO;
(ee) a second reference clock line for receiving a second reference clock signal; and (ff) a dual phase/frequency detector operative to drive the charge pump, having an input coupled to an output of the second divider circuit and the second reference clock line.
(aa) a second voltage control oscillator (VCO);
(bb) a second divider circuit having an input coupled to an output of the second VCO;
(cc) a second loop filter having an output coupled to an input of the second VCO;
(dd) a charge pump coupled to the second loop filter and operative to send source currents and sink currents into the second loop filter to control the second VCO;
(ee) a second reference clock line for receiving a second reference clock signal; and (ff) a dual phase/frequency detector operative to drive the charge pump, having an input coupled to an output of the second divider circuit and the second reference clock line.
24. A device according to claim 23, wherein the second divider circuit includes a divide-by three circuit coupled to a divide-by eight circuit.
25. A device according to claim 23, wherein the second loop filter has a transfer function optimized to enable the integral clock synthesis circuit to track the second reference clock signal and attenuate high frequency jitter on the second reference clock signal.
26. A device according to claim 25, wherein the transfer function yields a low pass corner frequency of 736 KHz when referenced to a 19.44 MHz crystal.
27. A device according to claim 25, wherein the transfer function yields a low pass corner frequency of 245 KHz when referenced to a 6.48 MHz crystal.
28. A user network interface (UNI) device for interfacing between a synchronous optical network (SONET) and an asynchronous transfer mode (ATM) network, the user network interface device comprising:
(a) a transmit section operative to receive an incoming non-continuous stream of data cells from the ATM
network, the transmit section comprising:
(i) a transmit cell buffer operative to receive and store incoming data cells from the incoming non-continuous stream of data cells;
(ii) a transmit section processor operative to generate and insert idle cells into the incoming non-continuous stream of data cells to form a continuous stream of cells and to map the continuous stream of cells into outgoing frames of data, the transmit section processor having an input coupled to an output of the transmit cell buffer;
(iii)a parallel-to-serial converter having an input coupled to an output of the transmit section processor;
(iv) an encoder, having an input coupled to an output of the parallel-to-serial converter, operative to encode data received from the parallel-to-serial converter;
and (v) an integral clock synthesis circuit coupled to the encoder and operative to synthesize a high speed transmit clock from a low frequency reference source;
wherein the receive section transmits the outgoing frames of data in an outgoing continuous stream of data directed to the synchronous optical network; and (b) a receive section operative to receive incoming frames of data in an incoming continuous stream of data from the synchronous optical network, each incoming frame of data having a synchronous payload envelop for storing data cells, the receive section comprising:
(i) a serial interface;
(ii) a decoder operative to recover data from the incoming continuous stream of data and having an input coupled to the serial interface;
(iii)an integral clock recovery circuit operative to sample and recover clock from the incoming continuous stream of data, having an output coupled to an input of the decoder;
(iv) a serial-to-parallel converter having an input coupled to an output of the decoder;
(v) a receive section processor operative to extract data cells from the incoming frames of data, having an input coupled to an output of the serial-to-parallel converter; and (vi) a receive cell buffer operative to store the extracted data cells for transmission in an outgoing non-continuous stream of data cells, having an input coupled to an output of the receive section processor;
wherein the receive section transmits the extracted data cells in an outgoing non-continuous stream of data to the ATM network.
(a) a transmit section operative to receive an incoming non-continuous stream of data cells from the ATM
network, the transmit section comprising:
(i) a transmit cell buffer operative to receive and store incoming data cells from the incoming non-continuous stream of data cells;
(ii) a transmit section processor operative to generate and insert idle cells into the incoming non-continuous stream of data cells to form a continuous stream of cells and to map the continuous stream of cells into outgoing frames of data, the transmit section processor having an input coupled to an output of the transmit cell buffer;
(iii)a parallel-to-serial converter having an input coupled to an output of the transmit section processor;
(iv) an encoder, having an input coupled to an output of the parallel-to-serial converter, operative to encode data received from the parallel-to-serial converter;
and (v) an integral clock synthesis circuit coupled to the encoder and operative to synthesize a high speed transmit clock from a low frequency reference source;
wherein the receive section transmits the outgoing frames of data in an outgoing continuous stream of data directed to the synchronous optical network; and (b) a receive section operative to receive incoming frames of data in an incoming continuous stream of data from the synchronous optical network, each incoming frame of data having a synchronous payload envelop for storing data cells, the receive section comprising:
(i) a serial interface;
(ii) a decoder operative to recover data from the incoming continuous stream of data and having an input coupled to the serial interface;
(iii)an integral clock recovery circuit operative to sample and recover clock from the incoming continuous stream of data, having an output coupled to an input of the decoder;
(iv) a serial-to-parallel converter having an input coupled to an output of the decoder;
(v) a receive section processor operative to extract data cells from the incoming frames of data, having an input coupled to an output of the serial-to-parallel converter; and (vi) a receive cell buffer operative to store the extracted data cells for transmission in an outgoing non-continuous stream of data cells, having an input coupled to an output of the receive section processor;
wherein the receive section transmits the extracted data cells in an outgoing non-continuous stream of data to the ATM network.
29. A device according to claim 28, wherein the integral clock recovery circuit includes:
(aa) a first voltage control oscillator (VCO), having an input and a divided down output, operative to lock on to the incoming continuous stream of data;
(bb) a phase/frequency detector operative to compare a first reference clock signal and a divided down output signal from the first VCO and to drive the first VCO to lock on to the first reference clock signal; and (cc) a data phase detector operative to compare a phase of the incoming continuous stream of data and the divided down output signal from the first VCO and to drive the first VCO towards a lock condition with the incoming continuous stream of data; and wherein the first VCO is switched from the phase/frequency detector to the data phase detector when a frequency difference between a frequency of the divided down output signal from the first VCO and that of the first reference clock signal is less than or equal to a predetermined threshold, and the first VCO is switched back to the phase/frequency detector when the frequency difference exceeds the predetermined threshold.
(aa) a first voltage control oscillator (VCO), having an input and a divided down output, operative to lock on to the incoming continuous stream of data;
(bb) a phase/frequency detector operative to compare a first reference clock signal and a divided down output signal from the first VCO and to drive the first VCO to lock on to the first reference clock signal; and (cc) a data phase detector operative to compare a phase of the incoming continuous stream of data and the divided down output signal from the first VCO and to drive the first VCO towards a lock condition with the incoming continuous stream of data; and wherein the first VCO is switched from the phase/frequency detector to the data phase detector when a frequency difference between a frequency of the divided down output signal from the first VCO and that of the first reference clock signal is less than or equal to a predetermined threshold, and the first VCO is switched back to the phase/frequency detector when the frequency difference exceeds the predetermined threshold.
30. A device according to claim 29, wherein the integral clock synthesis circuit includes:
(aa) a second voltage control oscillator (VCO);
(bb) a second divider circuit having an input coupled to an output of the second VCO;
(cc) a second loop filter having an output coupled to an input of the second VCO;
(dd) a charge pump coupled to the second loop filter and operative to send source currents and sink currents into the second loop filter to control the second VCO;
(ee) a second reference clock line for receiving a second reference clock signal; and (ff) a dual phase/frequency detector operative to drive the charge pump, having an input coupled to an output of the second divider circuit and the second reference clock line.
(aa) a second voltage control oscillator (VCO);
(bb) a second divider circuit having an input coupled to an output of the second VCO;
(cc) a second loop filter having an output coupled to an input of the second VCO;
(dd) a charge pump coupled to the second loop filter and operative to send source currents and sink currents into the second loop filter to control the second VCO;
(ee) a second reference clock line for receiving a second reference clock signal; and (ff) a dual phase/frequency detector operative to drive the charge pump, having an input coupled to an output of the second divider circuit and the second reference clock line.
31. A device according to claim 30, wherein said user network interface includes means for monitoring a transition density of the incoming continuous stream of data, and wherein clock is recovered from the incoming continuous stream of data only if the incoming continuous stream of data has a number of transitions greater than or equal to a preset value for an n-bit interval.
32. A device according to claim 31, wherein said transmit section processor includes:
(aa) a transmit cell processor operative to generate and insert cells into the incoming non-continuous stream of data cells to form the continuous stream of cells; and (bb) a transmit framer and overhead processor having an input coupled to an output of the transmit cell processor and operative to map the continuous stream of cells into the outgoing frames of data.
(aa) a transmit cell processor operative to generate and insert cells into the incoming non-continuous stream of data cells to form the continuous stream of cells; and (bb) a transmit framer and overhead processor having an input coupled to an output of the transmit cell processor and operative to map the continuous stream of cells into the outgoing frames of data.
33. A method according to claim 31, wherein the preset value is 1 and the n-bit interval is an 80-bit interval.
34. A device according to claim 31, wherein the predetermined threshold is 244 parts per million (ppm).
35. A method, in a user network interface (UNI) device interfacing between a synchronous optical network (SONET) and an asynchronous transfer mode (ATM) network, for recovering clock from an incoming continuous stream of data received by the UNI device from the synchronous optical network, the UNI device having an integral clock recovery circuit which includes a first voltage control oscillator (VCO), a divider circuit and a phase/frequency detector, the method comprising the steps of:
(a) generating a divided down clock signal in the UNI
device, including:
(i) driving the first VCO with the phase/frequency detector; and (ii) dividing down output from the first VCO
with the divider circuit;
(b) testing if a frequency of a reference clock signal and a frequency of the divided down clock signal differs by no more than a predetermined threshold;
(c) synchronizing the integral clock recovery circuit to a phase and a frequency of the incoming continuous stream of data, if the test in step (b) produces a result of true; and (d) recovering clock from the incoming continuous data stream in the event the phase and frequency are synchronized in step (c), including testing if the incoming continuous stream of data has a number of transitions greater than or equal to a preset value for an n-bit interval;
wherein the clock from the incoming continuous stream of data is recovered in step (d) if the number of transitions is greater than or equal to the preset value for the n-bit interval.
(a) generating a divided down clock signal in the UNI
device, including:
(i) driving the first VCO with the phase/frequency detector; and (ii) dividing down output from the first VCO
with the divider circuit;
(b) testing if a frequency of a reference clock signal and a frequency of the divided down clock signal differs by no more than a predetermined threshold;
(c) synchronizing the integral clock recovery circuit to a phase and a frequency of the incoming continuous stream of data, if the test in step (b) produces a result of true; and (d) recovering clock from the incoming continuous data stream in the event the phase and frequency are synchronized in step (c), including testing if the incoming continuous stream of data has a number of transitions greater than or equal to a preset value for an n-bit interval;
wherein the clock from the incoming continuous stream of data is recovered in step (d) if the number of transitions is greater than or equal to the preset value for the n-bit interval.
36. A method according to claim 35, wherein the clock recovery circuit further includes a data phase detector, and step (c) includes the step of:
switching from the phase/frequency detector to the data phase detector to drive the first VCO.
switching from the phase/frequency detector to the data phase detector to drive the first VCO.
37. A method, in a user network interface (UNI) device interfacing between a synchronous optical network (SONET) and an asynchronous transfer mode (ATM) network, for recovering clock from an incoming continuous stream of data received by the UNI device from the synchronous optical network, the UNI device having an integral clock recovery circuit, the method comprising the steps of:
(a) driving a first voltage control oscillator (VCO) in the integral clock recovery circuit with a phase/frequency detector;
(b) dividing down a signal from the first VCO to produce a divided down clock signal;
(c) testing if a frequency of a reference clock signal and a frequency of the divided down clock signal differs by no more than a predetermined threshold;
(d) switching control of the first VCO from the phase/frequency detector to a data phase detector so as to synchronize to a phase and a frequency of the incoming continuous stream of data, when the test in step (c) produces a result of true;
(e) testing if the incoming continuous stream of data has a number of transitions greater than or equal to a preset value for an n-bit interval; and (f) signaling to the UNI device that the integral clock recovery circuit is locked on to the clock of the incoming continuous stream of data in the event the phase and frequency are synchronized in step (c) and the number of transitions is greater than or equal to the preset value in step (e).
(a) driving a first voltage control oscillator (VCO) in the integral clock recovery circuit with a phase/frequency detector;
(b) dividing down a signal from the first VCO to produce a divided down clock signal;
(c) testing if a frequency of a reference clock signal and a frequency of the divided down clock signal differs by no more than a predetermined threshold;
(d) switching control of the first VCO from the phase/frequency detector to a data phase detector so as to synchronize to a phase and a frequency of the incoming continuous stream of data, when the test in step (c) produces a result of true;
(e) testing if the incoming continuous stream of data has a number of transitions greater than or equal to a preset value for an n-bit interval; and (f) signaling to the UNI device that the integral clock recovery circuit is locked on to the clock of the incoming continuous stream of data in the event the phase and frequency are synchronized in step (c) and the number of transitions is greater than or equal to the preset value in step (e).
38. A method, in a user network interface (UNI) device interfacing between a synchronous optical network (SONET) and an asynchronous transfer mode (ATM) connection, of synthesizing a high speed transmit clock from a low frequency reference source, the UNI device having an integral clock synthesis phase lock loop circuit, the method comprising the steps of:
(a) controlling a voltage control oscillator (VCO) with a charge pump;
(b) generating a divided down output signal from the VCO with a divider circuit;
(c) comparing the divided down output signal to a reference clock signal; and (d) driving the charge pump with a dual phase/frequency detector so as to synchronize the divided down output signal with the reference clock signal.
(a) controlling a voltage control oscillator (VCO) with a charge pump;
(b) generating a divided down output signal from the VCO with a divider circuit;
(c) comparing the divided down output signal to a reference clock signal; and (d) driving the charge pump with a dual phase/frequency detector so as to synchronize the divided down output signal with the reference clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002149076A CA2149076C (en) | 1995-05-10 | 1995-05-10 | Integrated user network interface device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002149076A CA2149076C (en) | 1995-05-10 | 1995-05-10 | Integrated user network interface device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2149076A1 CA2149076A1 (en) | 1996-11-11 |
| CA2149076C true CA2149076C (en) | 2001-02-20 |
Family
ID=4155816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002149076A Expired - Fee Related CA2149076C (en) | 1995-05-10 | 1995-05-10 | Integrated user network interface device |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2149076C (en) |
-
1995
- 1995-05-10 CA CA002149076A patent/CA2149076C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2149076A1 (en) | 1996-11-11 |
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