CA2095226A1 - Appareil pour engendrer un signal ds-3 a partir de la composante donnees d'un signal sts-1 - Google Patents
Appareil pour engendrer un signal ds-3 a partir de la composante donnees d'un signal sts-1Info
- Publication number
- CA2095226A1 CA2095226A1 CA2095226A CA2095226A CA2095226A1 CA 2095226 A1 CA2095226 A1 CA 2095226A1 CA 2095226 A CA2095226 A CA 2095226A CA 2095226 A CA2095226 A CA 2095226A CA 2095226 A1 CA2095226 A1 CA 2095226A1
- Authority
- CA
- Canada
- Prior art keywords
- signal
- fifo
- sts
- measuring circuit
- output clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 102100040338 Ubiquitin-associated and SH3 domain-containing protein B Human genes 0.000 abstract 3
- 101710143616 Ubiquitin-associated and SH3 domain-containing protein B Proteins 0.000 abstract 3
- 239000013078 crystal Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
- G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
- H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
- G06F2205/061—Adapt frequency, i.e. clock frequency at one side is adapted to clock frequency, or average clock frequency, at the other side; Not pulse stuffing only
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
L'appareil reçoit une composante données à intervalles d'un signal STS-1 et en dérive un signal de données DS-3 sans intervalles. L'appareil comprend un système premier entré, premier sorti (FIFO) (20) destiné à recevoir la composante données (12) du signal STS-1, un circuit de mesure (40) possédant à titre d'entrées un signal d'horloge d'entrée associé au signal STS-1 et le signal d'horloge de sortie de l'appareil pour mesurer efficacement la relative saturation du FIFO, ainsi qu'un oscillateur à quartz commandé en tension (VCXO) (90) destiné à recevoir un signal de commande envoyé par le circuit de mesure et à générer le signal d'horloge de sortie de l'appareil en fonction de ce signal, les données présentes dans le FIFO étant extraites de celui-ci sous forme de signal DS-3 en fonction de la fréquence du signal d'horloge de sortie. Le FIFO est de préférence une mémoire vive sur un octet, et le circuit de mesure est constitué de deux compteurs, d'une porte OU exclusif, et d'un filtre passe-bas. On obtient un système en boucle fermée en renvoyant le signal d'horloge de sortie à l'un des compteurs du circuit de mesure.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US606,482 | 1990-10-31 | ||
US07/606,482 US5157655A (en) | 1990-10-31 | 1990-10-31 | Apparatus for generating a ds-3 signal from the data component of an sts-1 payload signal |
PCT/US1991/008208 WO1992008304A1 (fr) | 1990-10-31 | 1991-10-31 | Appareil generateur d'un signal ds-3 a partir de la composante donnees d'un signal de charge utile sts-1 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2095226A1 true CA2095226A1 (fr) | 1992-05-01 |
CA2095226C CA2095226C (fr) | 2000-06-27 |
Family
ID=24428161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002095226A Expired - Fee Related CA2095226C (fr) | 1990-10-31 | 1991-10-31 | Appareil pour engendrer un signal ds-3 a partir de la composante donnees d'un signal sts-1 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5157655A (fr) |
CA (1) | CA2095226C (fr) |
WO (1) | WO1992008304A1 (fr) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5331641A (en) * | 1990-07-27 | 1994-07-19 | Transwitch Corp. | Methods and apparatus for retiming and realignment of STS-1 signals into STS-3 type signal |
DE4108429A1 (de) * | 1991-03-15 | 1992-09-17 | Philips Patentverwaltung | Uebertragungssystem fuer die digitale synchrone hierarchie |
DE4110933A1 (de) * | 1991-04-04 | 1992-10-08 | Philips Patentverwaltung | Uebertragungssystem fuer die synchrone digitale hierachie |
CA2078632C (fr) * | 1991-09-19 | 1997-12-30 | Tatsuhiko Nakagawa | Methode et dispositif de traitement de signaux sts-1 pouvant empecher les equipements terminaux de declencher de fausses alarmes |
DE69227820T2 (de) * | 1991-10-10 | 1999-05-12 | Nec Corp., Tokio/Tokyo | Sonet DS-N-Desynchronisiereinrichtung |
US5390180A (en) * | 1991-10-10 | 1995-02-14 | Nec America, Inc. | SONET DS-N desynchronizer |
US5267236A (en) * | 1991-12-16 | 1993-11-30 | Alcatel Network Systems, Inc. | Asynchronous parallel data formatter |
JPH05199199A (ja) * | 1992-01-20 | 1993-08-06 | Fujitsu Ltd | スタッフ同期制御方式 |
US5691976A (en) * | 1992-04-02 | 1997-11-25 | Applied Digital Access | Performance monitoring and test system for a telephone network |
US5479608A (en) * | 1992-07-17 | 1995-12-26 | Alcatel Network Systems, Inc. | Group facility protection in a digital telecommunications system |
US5404380A (en) * | 1992-08-25 | 1995-04-04 | Alcatel Network Systems, Inc. | Desynchronizer for adjusting the read data rate of payload data received over a digital communication network transmitting payload data within frames |
US5285206A (en) * | 1992-08-25 | 1994-02-08 | Alcatel Network Systems, Inc. | Phase detector for elastic store |
US5274635A (en) * | 1992-11-18 | 1993-12-28 | Stratacom, Inc. | Method and apparatus for aligning a digital communication data stream across a cell network |
EP0691768A1 (fr) * | 1994-07-07 | 1996-01-10 | International Business Machines Corporation | Procédé et dispositif pour effectuer une discrimination relative dans le temps dans un réseau à haute vitesse |
US5548534A (en) * | 1994-07-08 | 1996-08-20 | Transwitch Corporation | Two stage clock dejitter circuit for regenerating an E4 telecommunications signal from the data component of an STS-3C signal |
GB2303981A (en) * | 1995-07-29 | 1997-03-05 | Northern Telecom Ltd | Broadcast video desynchroniser |
US5982772A (en) * | 1995-11-06 | 1999-11-09 | Sun Microsystems, Inc. | Cell interface block partitioning for segmentation and re-assembly engine |
US6088413A (en) * | 1997-05-09 | 2000-07-11 | Alcatel | Apparatus for reducing jitter in a desynchronizer |
US6501809B1 (en) * | 1999-03-19 | 2002-12-31 | Conexant Systems, Inc. | Producing smoothed clock and data signals from gapped clock and data signals |
US6463111B1 (en) | 2001-05-25 | 2002-10-08 | Transwitch Corporaton | Method and apparatus for desynchronizing a DS-3 signal and/or an E3 signal from the data portion of an STS-STM payload |
US20030014763A1 (en) * | 2001-06-29 | 2003-01-16 | Chappell Christopher L. | Method and apparatus facilitating synchronization in a broadband communications system |
CN100449967C (zh) * | 2001-12-22 | 2009-01-07 | 中兴通讯股份有限公司 | 一种从同步数字传送体系中恢复e3/t3支路信号的装置 |
US7227876B1 (en) | 2002-01-28 | 2007-06-05 | Pmc-Sierra, Inc. | FIFO buffer depth estimation for asynchronous gapped payloads |
US20040123004A1 (en) * | 2002-12-19 | 2004-06-24 | International Business Machines Corporation | An improved fifo based controller circuit for slave devices attached to a cpu bus |
US7349444B2 (en) * | 2004-08-23 | 2008-03-25 | Transwitch Corporation | SONET/SDH SPE/virtual container retiming with adaptive dual pointer leak rate computation |
CN101217329B (zh) * | 2008-01-17 | 2011-05-25 | 中兴通讯股份有限公司 | 使用pdh的支路再定时系统 |
US8666011B1 (en) | 2011-04-20 | 2014-03-04 | Applied Micro Circuits Corporation | Jitter-attenuated clock using a gapped clock reference |
US8855258B1 (en) | 2011-04-20 | 2014-10-07 | Applied Micro Circuits Corporation | Transmitters and receivers using a jitter-attenuated clock derived from a gapped clock reference |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4053715A (en) * | 1976-03-22 | 1977-10-11 | Trw Inc. | Stuffing channel unit for telephone pcm system |
US4159535A (en) * | 1978-01-23 | 1979-06-26 | Rockwell International Corporation | Framing and elastic store circuit apparatus |
US4513427A (en) * | 1982-08-30 | 1985-04-23 | Xerox Corporation | Data and clock recovery system for data communication controller |
US4551830A (en) * | 1984-03-19 | 1985-11-05 | Rockwell International Corporation | Apparatus for providing loopback of signals where the signals being looped back have an overhead data format which is incompatible with a high speed intermediate carrier overhead format |
US4685101A (en) * | 1984-12-20 | 1987-08-04 | Siemens Aktiengesellschaft | Digital multiplexer for PCM voice channels having a cross-connect capability |
US4674088A (en) * | 1985-03-07 | 1987-06-16 | Northern Telecom Limited | Method and apparatus for detecting frame synchronization |
CA1232693A (fr) * | 1985-09-05 | 1988-02-09 | Alan F. Graves | Structure de multiplexage pour reseau |
US4791652A (en) * | 1987-06-04 | 1988-12-13 | Northern Telecom Limited | Synchronization of asynchronous data signals |
US4833673A (en) * | 1987-11-10 | 1989-05-23 | Bell Communications Research, Inc. | Time division multiplexer for DTDM bit streams |
US5040170A (en) * | 1988-12-09 | 1991-08-13 | Transwitch Corporation | System for cross-connecting high speed digital signals |
US5033064A (en) * | 1988-12-09 | 1991-07-16 | Transwitch Corporation | Clock dejitter circuit for regenerating DS1 signal |
US4928275A (en) * | 1989-05-26 | 1990-05-22 | Northern Telecom Limited | Synchronization of asynchronous data signals |
CA1326719C (fr) * | 1989-05-30 | 1994-02-01 | Thomas E. Moore | Circuit d'interface sonet monte entre un ds3 et 28vt1.5 |
US5052025A (en) * | 1990-08-24 | 1991-09-24 | At&T Bell Laboratories | Synchronous digital signal to asynchronous digital signal desynchronizer |
-
1990
- 1990-10-31 US US07/606,482 patent/US5157655A/en not_active Expired - Lifetime
-
1991
- 1991-10-31 WO PCT/US1991/008208 patent/WO1992008304A1/fr active Application Filing
- 1991-10-31 CA CA002095226A patent/CA2095226C/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO1992008304A1 (fr) | 1992-05-14 |
CA2095226C (fr) | 2000-06-27 |
US5157655A (en) | 1992-10-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |