CA2079623A1 - Methode et dispositif pour permettre a deux utilisateurs d'avoir acces de facon transparente a une memoire a port unique - Google Patents

Methode et dispositif pour permettre a deux utilisateurs d'avoir acces de facon transparente a une memoire a port unique

Info

Publication number
CA2079623A1
CA2079623A1 CA2079623A CA2079623A CA2079623A1 CA 2079623 A1 CA2079623 A1 CA 2079623A1 CA 2079623 A CA2079623 A CA 2079623A CA 2079623 A CA2079623 A CA 2079623A CA 2079623 A1 CA2079623 A1 CA 2079623A1
Authority
CA
Canada
Prior art keywords
access control
memory
control unit
port
memory access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2079623A
Other languages
English (en)
Other versions
CA2079623C (fr
Inventor
James L. Mckenna
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Standard Microsystems LLC
Original Assignee
James L. Mckenna
Standard Microsystems Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by James L. Mckenna, Standard Microsystems Corporation filed Critical James L. Mckenna
Publication of CA2079623A1 publication Critical patent/CA2079623A1/fr
Application granted granted Critical
Publication of CA2079623C publication Critical patent/CA2079623C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Multi Processors (AREA)
CA002079623A 1991-10-03 1992-10-01 Methode et dispositif pour permettre a deux utilisateurs d'avoir acces de facon transparente a une memoire a port unique Expired - Fee Related CA2079623C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/770,695 US5392412A (en) 1991-10-03 1991-10-03 Data communication controller for use with a single-port data packet buffer
US770,695 1991-10-03

Publications (2)

Publication Number Publication Date
CA2079623A1 true CA2079623A1 (fr) 1993-04-04
CA2079623C CA2079623C (fr) 2000-12-12

Family

ID=25089395

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002079623A Expired - Fee Related CA2079623C (fr) 1991-10-03 1992-10-01 Methode et dispositif pour permettre a deux utilisateurs d'avoir acces de facon transparente a une memoire a port unique

Country Status (2)

Country Link
US (1) US5392412A (fr)
CA (1) CA2079623C (fr)

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US5745732A (en) * 1994-11-15 1998-04-28 Cherukuri; Ravikrishna V. Computer system including system controller with a write buffer and plural read buffers for decoupled busses
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US6427196B1 (en) * 1999-08-31 2002-07-30 Intel Corporation SRAM controller for parallel processor architecture including address and command queue and arbiter
US6668317B1 (en) * 1999-08-31 2003-12-23 Intel Corporation Microengine for parallel processor architecture
US6983350B1 (en) 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
US7191309B1 (en) 1999-09-01 2007-03-13 Intel Corporation Double shift instruction for micro engine used in multithreaded parallel processor architecture
AU7098500A (en) 1999-09-01 2001-03-26 Intel Corporation Branch instruction for processor
US7546444B1 (en) 1999-09-01 2009-06-09 Intel Corporation Register set used in multithreaded parallel processor architecture
US6532509B1 (en) 1999-12-22 2003-03-11 Intel Corporation Arbitrating command requests in a parallel multi-threaded processing system
US6694380B1 (en) * 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US6307789B1 (en) * 1999-12-28 2001-10-23 Intel Corporation Scratchpad memory
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
US6631430B1 (en) * 1999-12-28 2003-10-07 Intel Corporation Optimizations to receive packet status from fifo bus
US7620702B1 (en) 1999-12-28 2009-11-17 Intel Corporation Providing real-time control data for a network processor
US6661794B1 (en) * 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US7480706B1 (en) 1999-12-30 2009-01-20 Intel Corporation Multi-threaded round-robin receive for fast network port
US6584522B1 (en) * 1999-12-30 2003-06-24 Intel Corporation Communication between processors
US6952824B1 (en) 1999-12-30 2005-10-04 Intel Corporation Multi-threaded sequenced receive for fast network port stream of packets
US6976095B1 (en) 1999-12-30 2005-12-13 Intel Corporation Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
US6631462B1 (en) * 2000-01-05 2003-10-07 Intel Corporation Memory shared between processing threads
US7681018B2 (en) * 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US20020053017A1 (en) * 2000-09-01 2002-05-02 Adiletta Matthew J. Register instructions for a multithreaded processor
US7020871B2 (en) * 2000-12-21 2006-03-28 Intel Corporation Breakpoint method for parallel hardware threads in multithreaded processor
US7225281B2 (en) 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7487505B2 (en) 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7216204B2 (en) * 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7126952B2 (en) * 2001-09-28 2006-10-24 Intel Corporation Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US20030144970A1 (en) * 2001-12-10 2003-07-31 Coyne Patrick J. Project management database and method of managing project related information
US8935297B2 (en) * 2001-12-10 2015-01-13 Patrick J. Coyne Method and system for the management of professional services project information
US7158964B2 (en) * 2001-12-12 2007-01-02 Intel Corporation Queue management
US7107413B2 (en) * 2001-12-17 2006-09-12 Intel Corporation Write queue descriptor count instruction for high speed queuing
US7269179B2 (en) * 2001-12-18 2007-09-11 Intel Corporation Control mechanisms for enqueue and dequeue operations in a pipelined network processor
US7895239B2 (en) 2002-01-04 2011-02-22 Intel Corporation Queue arrays in network devices
US7181573B2 (en) * 2002-01-07 2007-02-20 Intel Corporation Queue array caching in network devices
US6934951B2 (en) 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US7610451B2 (en) 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US7181594B2 (en) * 2002-01-25 2007-02-20 Intel Corporation Context pipelines
US7149226B2 (en) * 2002-02-01 2006-12-12 Intel Corporation Processing data packets
US7437724B2 (en) * 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
US7471688B2 (en) * 2002-06-18 2008-12-30 Intel Corporation Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US7337275B2 (en) 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US7352769B2 (en) 2002-09-12 2008-04-01 Intel Corporation Multiple calendar schedule reservation structure and method
US7433307B2 (en) * 2002-11-05 2008-10-07 Intel Corporation Flow control in a network environment
US6941438B2 (en) * 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US7443836B2 (en) 2003-06-16 2008-10-28 Intel Corporation Processing a data packet
US7213099B2 (en) * 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches
CN100388252C (zh) * 2004-12-14 2008-05-14 威瀚科技股份有限公司 实现双端口同步存储装置的方法及相关装置
US7739433B2 (en) * 2008-03-05 2010-06-15 Microchip Technology Incorporated Sharing bandwidth of a single port SRAM between at least one DMA peripheral and a CPU operating with a quadrature clock
US8819663B2 (en) * 2012-06-18 2014-08-26 Lsi Corporation Acceleration of software modifications in networked devices

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4604683A (en) * 1984-12-10 1986-08-05 Advanced Computer Communications Communication controller using multiported random access memory
JPH02117243A (ja) * 1988-10-27 1990-05-01 Toshiba Corp パケット通信装置
CA2011935A1 (fr) * 1989-04-07 1990-10-07 Desiree A. Awiszio Systeme d'interconnexion d'ordinateurs a deux trajets a controleur de memoire a paquets a quatre ports
US4967398A (en) * 1989-08-09 1990-10-30 Ford Motor Company Read/write random access memory with data prefetch
US5210749A (en) * 1990-05-29 1993-05-11 Advanced Micro Devices, Inc. Configuration of srams as logical fifos for transmit and receive of packet data
US5175732A (en) * 1991-02-15 1992-12-29 Standard Microsystems Corp. Method and apparatus for controlling data communication operations within stations of a local-area network

Also Published As

Publication number Publication date
CA2079623C (fr) 2000-12-12
US5392412A (en) 1995-02-21

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