CA2077048A1 - Ordinateur personnel dote d'une memoire a antememoire a double ecriture et a cycles de furetage en pipeline - Google Patents
Ordinateur personnel dote d'une memoire a antememoire a double ecriture et a cycles de furetage en pipelineInfo
- Publication number
- CA2077048A1 CA2077048A1 CA2077048A CA2077048A CA2077048A1 CA 2077048 A1 CA2077048 A1 CA 2077048A1 CA 2077048 A CA2077048 A CA 2077048A CA 2077048 A CA2077048 A CA 2077048A CA 2077048 A1 CA2077048 A1 CA 2077048A1
- Authority
- CA
- Canada
- Prior art keywords
- cycle
- write
- cache
- personal computer
- memory system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US812,196 | 1985-12-23 | ||
US07/812,196 US5341487A (en) | 1991-12-20 | 1991-12-20 | Personal computer having memory system with write-through cache and pipelined snoop cycles |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2077048A1 true CA2077048A1 (fr) | 1993-06-21 |
CA2077048C CA2077048C (fr) | 1996-10-22 |
Family
ID=25208830
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002077048A Expired - Fee Related CA2077048C (fr) | 1991-12-20 | 1992-08-27 | Ordinateur personnel dote d'une memoire a antememoire a double ecriture et a cycles de furetage en pipeline |
Country Status (6)
Country | Link |
---|---|
US (1) | US5341487A (fr) |
EP (1) | EP0549164B1 (fr) |
JP (1) | JPH0727493B2 (fr) |
BR (1) | BR9204884A (fr) |
CA (1) | CA2077048C (fr) |
DE (1) | DE69203842T2 (fr) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6249481B1 (en) * | 1991-10-15 | 2001-06-19 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US5966728A (en) * | 1992-01-02 | 1999-10-12 | International Business Machines Corp. | Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device |
JP3027843B2 (ja) * | 1993-04-23 | 2000-04-04 | 株式会社日立製作所 | バススヌ−プ方法 |
JP2675981B2 (ja) * | 1993-09-20 | 1997-11-12 | インターナショナル・ビジネス・マシーンズ・コーポレイション | スヌープ・プッシュ・オペレーションを回避する方法 |
US5797026A (en) * | 1994-02-28 | 1998-08-18 | Intel Corporation | Method and apparatus for self-snooping a bus during a boundary transaction |
US5572702A (en) * | 1994-02-28 | 1996-11-05 | Intel Corporation | Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency |
US5600802A (en) * | 1994-03-14 | 1997-02-04 | Apple Computer, Inc. | Methods and apparatus for translating incompatible bus transactions |
US5485572A (en) * | 1994-04-26 | 1996-01-16 | Unisys Corporation | Response stack state validation check |
US5539895A (en) * | 1994-05-12 | 1996-07-23 | International Business Machines Corporation | Hierarchical computer cache system |
US5615334A (en) * | 1994-10-07 | 1997-03-25 | Industrial Technology Research Institute | Memory reflection system and method for reducing bus utilization and device idle time in the event of faults |
US5634073A (en) * | 1994-10-14 | 1997-05-27 | Compaq Computer Corporation | System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation |
US5630094A (en) * | 1995-01-20 | 1997-05-13 | Intel Corporation | Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions |
US5893921A (en) * | 1995-02-10 | 1999-04-13 | International Business Machines Corporation | Method for maintaining memory coherency in a computer system having a cache utilizing snoop address injection during a read transaction by a dual memory bus controller |
US5704058A (en) * | 1995-04-21 | 1997-12-30 | Derrick; John E. | Cache bus snoop protocol for optimized multiprocessor computer system |
US5737756A (en) * | 1995-04-28 | 1998-04-07 | Unisys Corporation | Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue |
US5710906A (en) * | 1995-07-07 | 1998-01-20 | Opti Inc. | Predictive snooping of cache memory for master-initiated accesses |
JP3782840B2 (ja) | 1995-07-14 | 2006-06-07 | 株式会社ルネサステクノロジ | 外部記憶装置およびそのメモリアクセス制御方法 |
US5652859A (en) * | 1995-08-17 | 1997-07-29 | Institute For The Development Of Emerging Architectures, L.L.C. | Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues |
US5778438A (en) * | 1995-12-06 | 1998-07-07 | Intel Corporation | Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests |
US5809537A (en) * | 1995-12-08 | 1998-09-15 | International Business Machines Corp. | Method and system for simultaneous processing of snoop and cache operations |
KR100308173B1 (ko) | 1996-02-29 | 2001-11-02 | 가나이 쓰도무 | 부분불량메모리를탑재한반도체기억장치 |
US6748463B1 (en) * | 1996-03-13 | 2004-06-08 | Hitachi, Ltd. | Information processor with snoop suppressing function, memory controller, and direct memory access processing method |
US5809534A (en) * | 1996-06-13 | 1998-09-15 | Compaq Computer Corporation | Performing a write cycle to memory in a multi-processor system |
US5875469A (en) * | 1996-08-26 | 1999-02-23 | International Business Machines Corporation | Apparatus and method of snooping processors and look-aside caches |
US5960457A (en) * | 1997-05-01 | 1999-09-28 | Advanced Micro Devices, Inc. | Cache coherency test system and methodology for testing cache operation in the presence of an external snoop |
KR100255510B1 (ko) * | 1997-05-09 | 2000-05-01 | 김영환 | 원포트램셀구조로이루어진캐시데이터램 |
US5900017A (en) * | 1997-05-14 | 1999-05-04 | International Business Machines Corporation | Snooping a variable number of cache addresses in a multiple processor system by a single snoop request |
US6065101A (en) * | 1997-06-12 | 2000-05-16 | International Business Machines Corporation | Pipelined snooping of multiple L1 cache lines |
US5912906A (en) * | 1997-06-23 | 1999-06-15 | Sun Microsystems, Inc. | Method and apparatus for recovering from correctable ECC errors |
US6076147A (en) * | 1997-06-24 | 2000-06-13 | Sun Microsystems, Inc. | Non-inclusive cache system using pipelined snoop bus |
US6061766A (en) * | 1997-06-24 | 2000-05-09 | Sun Microsystems, Inc. | Non-inclusive cache method using pipelined snoop bus |
US6385703B1 (en) * | 1998-12-03 | 2002-05-07 | Intel Corporation | Speculative request pointer advance for fast back-to-back reads |
US6615323B1 (en) | 1999-09-02 | 2003-09-02 | Thomas Albert Petersen | Optimizing pipelined snoop processing |
US6609171B1 (en) * | 1999-12-29 | 2003-08-19 | Intel Corporation | Quad pumped bus architecture and protocol |
US6658545B1 (en) * | 2000-02-16 | 2003-12-02 | Lucent Technologies Inc. | Passing internal bus data external to a completed system |
US6728869B1 (en) * | 2000-04-21 | 2004-04-27 | Ati International Srl | Method and apparatus for memory latency avoidance in a processing system |
US7085889B2 (en) * | 2002-03-22 | 2006-08-01 | Intel Corporation | Use of a context identifier in a cache memory |
US7080198B1 (en) * | 2002-07-31 | 2006-07-18 | Adaptec, Inc. | Method for snooping RAID 1 write transactions by a storage device |
US20070147115A1 (en) * | 2005-12-28 | 2007-06-28 | Fong-Long Lin | Unified memory and controller |
US7519754B2 (en) * | 2005-12-28 | 2009-04-14 | Silicon Storage Technology, Inc. | Hard disk drive cache memory and playback device |
JP5218228B2 (ja) * | 2008-04-23 | 2013-06-26 | 新東工業株式会社 | 搬送装置及びブラスト加工装置 |
KR102490104B1 (ko) | 2017-10-30 | 2023-01-19 | 삼성전자주식회사 | 데이터 보호를 사용하는 인-밴드 메모리에 액세스하기 위한 장치 및 방법 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4392200A (en) * | 1980-01-28 | 1983-07-05 | Digital Equipment Corporation | Cached multiprocessor system with pipeline timing |
US4638431A (en) * | 1984-09-17 | 1987-01-20 | Nec Corporation | Data processing system for vector processing having a cache invalidation control unit |
US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
US5025365A (en) * | 1988-11-14 | 1991-06-18 | Unisys Corporation | Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors |
US5119485A (en) * | 1989-05-15 | 1992-06-02 | Motorola, Inc. | Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation |
US5193170A (en) * | 1990-10-26 | 1993-03-09 | International Business Machines Corporation | Methods and apparatus for maintaining cache integrity whenever a cpu write to rom operation is performed with rom mapped to ram |
-
1991
- 1991-12-20 US US07/812,196 patent/US5341487A/en not_active Expired - Fee Related
-
1992
- 1992-08-27 CA CA002077048A patent/CA2077048C/fr not_active Expired - Fee Related
- 1992-10-29 JP JP4291228A patent/JPH0727493B2/ja not_active Expired - Lifetime
- 1992-12-03 EP EP92311061A patent/EP0549164B1/fr not_active Expired - Lifetime
- 1992-12-03 DE DE69203842T patent/DE69203842T2/de not_active Expired - Fee Related
- 1992-12-07 BR BR9204884A patent/BR9204884A/pt not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
EP0549164B1 (fr) | 1995-08-02 |
CA2077048C (fr) | 1996-10-22 |
US5341487A (en) | 1994-08-23 |
JPH0628254A (ja) | 1994-02-04 |
JPH0727493B2 (ja) | 1995-03-29 |
BR9204884A (pt) | 1993-06-22 |
DE69203842T2 (de) | 1996-05-02 |
DE69203842D1 (de) | 1995-09-07 |
EP0549164A1 (fr) | 1993-06-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |